[mirror_ubuntu-hirsute-kernel.git] / arch / mips / pci / pci-bcm1480.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2001,2002,2005 Broadcom Corporation
 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
 */

/*
 * BCM1x80/1x55-specific PCI support
 *
 * This module provides the glue between Linux's PCI subsystem
 * and the hardware.  We basically provide glue for accessing
 * configuration space, and set up the translation for I/O
 * space accesses.
 *
 * To access configuration space, we use ioremap.  In the 32-bit
 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
 * kernel mapped memory.  Hopefully neither of these should be a huge
 * problem.
 *
 * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
 */
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/console.h>
#include <linux/tty.h>
#include <linux/vt.h>

#include <asm/sibyte/bcm1480_regs.h>
#include <asm/sibyte/bcm1480_scd.h>
#include <asm/sibyte/board.h>
#include <asm/io.h>

/*
 * Macros for calculating offsets into config space given a device
 * structure or dev/fun/reg
 */
#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
#define CFGADDR(bus, devfn, where)   CFGOFFSET((bus)->number, (devfn), where)

static void *cfg_space;

#define PCI_BUS_ENABLED 1
#define PCI_DEVICE_MODE 2

static int bcm1480_bus_status;

#define PCI_BRIDGE_DEVICE  0

/*
 * Read/write 32-bit values in config space.
 */
static inline u32 READCFG32(u32 addr)
{
	return *(u32 *)(cfg_space + (addr&~3));
}

static inline void WRITECFG32(u32 addr, u32 data)
{
	*(u32 *)(cfg_space + (addr & ~3)) = data;
}

int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	if (pin == 0)
		return -1;

	return K_BCM1480_INT_PCI_INTA - 1 + pin;
}

/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
	return 0;
}

/*
 * Some checks before doing config cycles:
 * In PCI Device Mode, hide everything on bus 0 except the LDT host
 * bridge.  Otherwise, access is controlled by bridge MasterEn bits.
 */
static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
{
	u32 devno;

	if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
		return 0;

	if (bus->number == 0) {
		devno = PCI_SLOT(devfn);
		if (bcm1480_bus_status & PCI_DEVICE_MODE)
			return 0;
		else
			return 1;
	} else
		return 1;
}

/*
 * Read/write access functions for various sizes of values
 * in config space.  Return all 1's for disallowed accesses
 * for a kludgy but adequate simulation of master aborts.
 */

static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
				int where, int size, u32 * val)
{
	u32 data = 0;

	if ((size == 2) && (where & 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;
	else if ((size == 4) && (where & 3))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (bcm1480_pci_can_access(bus, devfn))
		data = READCFG32(CFGADDR(bus, devfn, where));
	else
		data = 0xFFFFFFFF;

	if (size == 1)
		*val = (data >> ((where & 3) << 3)) & 0xff;
	else if (size == 2)
		*val = (data >> ((where & 3) << 3)) & 0xffff;
	else
		*val = data;

	return PCIBIOS_SUCCESSFUL;
}

static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
				int where, int size, u32 val)
{
	u32 cfgaddr = CFGADDR(bus, devfn, where);
	u32 data = 0;

	if ((size == 2) && (where & 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;
	else if ((size == 4) && (where & 3))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (!bcm1480_pci_can_access(bus, devfn))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	data = READCFG32(cfgaddr);

	if (size == 1)
		data = (data & ~(0xff << ((where & 3) << 3))) |
		    (val << ((where & 3) << 3));
	else if (size == 2)
		data = (data & ~(0xffff << ((where & 3) << 3))) |
		    (val << ((where & 3) << 3));
	else
		data = val;

	WRITECFG32(cfgaddr, data);

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops bcm1480_pci_ops = {
	.read	= bcm1480_pcibios_read,
	.write	= bcm1480_pcibios_write,
};

static struct resource bcm1480_mem_resource = {
	.name	= "BCM1480 PCI MEM",
	.start	= A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES,
	.end	= A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES + 0xfffffffUL,
	.flags	= IORESOURCE_MEM,
};

static struct resource bcm1480_io_resource = {
	.name	= "BCM1480 PCI I/O",
	.start	= A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
	.end	= A_BCM1480_PHYS_PCI_IO_MATCH_BYTES + 0x1ffffffUL,
	.flags	= IORESOURCE_IO,
};

struct pci_controller bcm1480_controller = {
	.pci_ops	= &bcm1480_pci_ops,
	.mem_resource	= &bcm1480_mem_resource,
	.io_resource	= &bcm1480_io_resource,
	.io_offset	= A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
};


static int __init bcm1480_pcibios_init(void)
{
	uint32_t cmdreg;
	uint64_t reg;

	/* CFE will assign PCI resources */
	pci_set_flags(PCI_PROBE_ONLY);

	/* Avoid ISA compat ranges.  */
	PCIBIOS_MIN_IO = 0x00008000UL;
	PCIBIOS_MIN_MEM = 0x01000000UL;

	/* Set I/O resource limits. - unlimited for now to accommodate HT */
	ioport_resource.end = 0xffffffffUL;
	iomem_resource.end = 0xffffffffUL;

	cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024);

	/*
	 * See if the PCI bus has been configured by the firmware.
	 */
	reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
	if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
		bcm1480_bus_status |= PCI_DEVICE_MODE;
	} else {
		cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
					     PCI_COMMAND));
		if (!(cmdreg & PCI_COMMAND_MASTER)) {
			printk
			    ("PCI: Skipping PCI probe.	Bus is not initialized.\n");
			iounmap(cfg_space);
			return 1; /* XXX */
		}
		bcm1480_bus_status |= PCI_BUS_ENABLED;
	}

	/* turn on ExpMemEn */
	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
	WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
			cmdreg | 0x10);
	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));

	/*
	 * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
	 * space.  Use "match bytes" policy to make everything look
	 * little-endian.  So, you need to also set
	 * CONFIG_SWAP_IO_SPACE, but this is the combination that
	 * works correctly with most of Linux's drivers.
	 * XXX ehs: Should this happen in PCI Device mode?
	 */

	bcm1480_controller.io_map_base = (unsigned long)
		ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536);
	bcm1480_controller.io_map_base -= bcm1480_controller.io_offset;
	set_io_port_base(bcm1480_controller.io_map_base);

	register_pci_controller(&bcm1480_controller);

#ifdef CONFIG_VGA_CONSOLE
	console_lock();
	do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
	console_unlock();
#endif
	return 0;
}

arch_initcall(bcm1480_pcibios_init);
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
dc41f94f AI	2	/*
	3	* Copyright (C) 2001,2002,2005 Broadcom Corporation
	4	* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
dc41f94f AI	5	*/
	6
	7	/*
	8	* BCM1x80/1x55-specific PCI support
	9	*
	10	* This module provides the glue between Linux's PCI subsystem
	11	* and the hardware. We basically provide glue for accessing
	12	* configuration space, and set up the translation for I/O
	13	* space accesses.
	14	*
	15	* To access configuration space, we use ioremap. In the 32-bit
	16	* kernel, this consumes either 4 or 8 page table pages, and 16MB of
	17	* kernel mapped memory. Hopefully neither of these should be a huge
	18	* problem.
	19	*
	20	* XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
	21	*/
dc41f94f AI	22	#include <linux/types.h>
	23	#include <linux/pci.h>
	24	#include <linux/kernel.h>
	25	#include <linux/init.h>
	26	#include <linux/mm.h>
	27	#include <linux/console.h>
	28	#include <linux/tty.h>
88f02518	29	#include <linux/vt.h>
dc41f94f AI	30
	31	#include <asm/sibyte/bcm1480_regs.h>
	32	#include <asm/sibyte/bcm1480_scd.h>
	33	#include <asm/sibyte/board.h>
	34	#include <asm/io.h>
	35
	36	/*
	37	* Macros for calculating offsets into config space given a device
	38	* structure or dev/fun/reg
	39	*/
21a151d8 RB	40	#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
21a151d8 RB	41	#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
dc41f94f AI	42
	43	static void *cfg_space;
	44
70342287 RB	45	#define PCI_BUS_ENABLED 1
70342287 RB	46	#define PCI_DEVICE_MODE 2
dc41f94f	47
982f6ffe	48	static int bcm1480_bus_status;
dc41f94f AI	49
dc41f94f AI	50	#define PCI_BRIDGE_DEVICE 0
dc41f94f AI	51
	52	/*
	53	* Read/write 32-bit values in config space.
	54	*/
	55	static inline u32 READCFG32(u32 addr)
	56	{
	57	return (u32 )(cfg_space + (addr&~3));
	58	}
	59
	60	static inline void WRITECFG32(u32 addr, u32 data)
	61	{
	62	(u32 )(cfg_space + (addr & ~3)) = data;
	63	}
	64
19df0d11	65	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
dc41f94f	66	{
f435a91e RB	67	if (pin == 0)
	68	return -1;
	69
	70	return K_BCM1480_INT_PCI_INTA - 1 + pin;
dc41f94f AI	71	}
	72
	73	/* Do platform specific device initialization at pci_enable_device() time */
	74	int pcibios_plat_dev_init(struct pci_dev *dev)
	75	{
	76	return 0;
	77	}
	78
	79	/*
	80	* Some checks before doing config cycles:
	81	* In PCI Device Mode, hide everything on bus 0 except the LDT host
	82	* bridge. Otherwise, access is controlled by bridge MasterEn bits.
	83	*/
	84	static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
	85	{
8a1417de AI	86	u32 devno;
8a1417de AI	87
dc41f94f AI	88	if (!(bcm1480_bus_status & (PCI_BUS_ENABLED \| PCI_DEVICE_MODE)))
	89	return 0;
	90
	91	if (bus->number == 0) {
8a1417de	92	devno = PCI_SLOT(devfn);
a3dddd56	93	if (bcm1480_bus_status & PCI_DEVICE_MODE)
dc41f94f AI	94	return 0;
	95	else
	96	return 1;
	97	} else
	98	return 1;
	99	}
	100
	101	/*
	102	* Read/write access functions for various sizes of values
	103	* in config space. Return all 1's for disallowed accesses
	104	* for a kludgy but adequate simulation of master aborts.
	105	*/
	106
	107	static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
	108	int where, int size, u32 * val)
	109	{
	110	u32 data = 0;
	111
	112	if ((size == 2) && (where & 1))
	113	return PCIBIOS_BAD_REGISTER_NUMBER;
	114	else if ((size == 4) && (where & 3))
	115	return PCIBIOS_BAD_REGISTER_NUMBER;
	116
	117	if (bcm1480_pci_can_access(bus, devfn))
	118	data = READCFG32(CFGADDR(bus, devfn, where));
	119	else
	120	data = 0xFFFFFFFF;
	121
	122	if (size == 1)
	123	*val = (data >> ((where & 3) << 3)) & 0xff;
	124	else if (size == 2)
	125	*val = (data >> ((where & 3) << 3)) & 0xffff;
	126	else
	127	*val = data;
	128
	129	return PCIBIOS_SUCCESSFUL;
	130	}
	131
	132	static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
	133	int where, int size, u32 val)
	134	{
	135	u32 cfgaddr = CFGADDR(bus, devfn, where);
	136	u32 data = 0;
	137
	138	if ((size == 2) && (where & 1))
	139	return PCIBIOS_BAD_REGISTER_NUMBER;
	140	else if ((size == 4) && (where & 3))
	141	return PCIBIOS_BAD_REGISTER_NUMBER;
	142
	143	if (!bcm1480_pci_can_access(bus, devfn))
	144	return PCIBIOS_BAD_REGISTER_NUMBER;
	145
	146	data = READCFG32(cfgaddr);
	147
	148	if (size == 1)
	149	data = (data & ~(0xff << ((where & 3) << 3))) \|
	150	(val << ((where & 3) << 3));
	151	else if (size == 2)
	152	data = (data & ~(0xffff << ((where & 3) << 3))) \|
	153	(val << ((where & 3) << 3));
	154	else
	155	data = val;
	156
	157	WRITECFG32(cfgaddr, data);
158
159	return PCIBIOS_SUCCESSFUL;
160	}
161
162	struct pci_ops bcm1480_pci_ops = {
7b09777c RH	163	.read = bcm1480_pcibios_read,
7b09777c RH	164	.write = bcm1480_pcibios_write,
dc41f94f AI	165	};
	166
	167	static struct resource bcm1480_mem_resource = {
	168	.name = "BCM1480 PCI MEM",
07c019bc RB	169	.start = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES,
07c019bc RB	170	.end = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES + 0xfffffffUL,
dc41f94f AI	171	.flags = IORESOURCE_MEM,
	172	};
	173
	174	static struct resource bcm1480_io_resource = {
	175	.name = "BCM1480 PCI I/O",
cf7b7e0b TB	176	.start = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
cf7b7e0b TB	177	.end = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES + 0x1ffffffUL,
dc41f94f AI	178	.flags = IORESOURCE_IO,
	179	};
	180
	181	struct pci_controller bcm1480_controller = {
	182	.pci_ops = &bcm1480_pci_ops,
	183	.mem_resource = &bcm1480_mem_resource,
	184	.io_resource = &bcm1480_io_resource,
70342287	185	.io_offset = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
dc41f94f AI	186	};
	187
	188
	189	static int __init bcm1480_pcibios_init(void)
	190	{
	191	uint32_t cmdreg;
	192	uint64_t reg;
dc41f94f AI	193
dc41f94f AI	194	/* CFE will assign PCI resources */
29090606	195	pci_set_flags(PCI_PROBE_ONLY);
dc41f94f AI	196
	197	/* Avoid ISA compat ranges. */
	198	PCIBIOS_MIN_IO = 0x00008000UL;
	199	PCIBIOS_MIN_MEM = 0x01000000UL;
	200
25985edc	201	/* Set I/O resource limits. - unlimited for now to accommodate HT */
8a1417de AI	202	ioport_resource.end = 0xffffffffUL;
8a1417de AI	203	iomem_resource.end = 0xffffffffUL;
dc41f94f AI	204
	205	cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 1610241024);
	206
	207	/*
	208	* See if the PCI bus has been configured by the firmware.
	209	*/
8fb303c7	210	reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
dc41f94f AI	211	if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
	212	bcm1480_bus_status \|= PCI_DEVICE_MODE;
	213	} else {
	214	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
	215	PCI_COMMAND));
	216	if (!(cmdreg & PCI_COMMAND_MASTER)) {
	217	printk
70342287	218	("PCI: Skipping PCI probe. Bus is not initialized.\n");
dc41f94f AI	219	iounmap(cfg_space);
	220	return 1; /* XXX */
	221	}
	222	bcm1480_bus_status \|= PCI_BUS_ENABLED;
	223	}
	224
cb426248 AI	225	/* turn on ExpMemEn */
cb426248 AI	226	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
cb426248 AI	227	WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
	228	cmdreg \| 0x10);
	229	cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
cb426248	230
dc41f94f AI	231	/*
	232	* Establish mappings in KSEG2 (kernel virtual) to PCI I/O
	233	* space. Use "match bytes" policy to make everything look
	234	* little-endian. So, you need to also set
	235	* CONFIG_SWAP_IO_SPACE, but this is the combination that
	236	* works correctly with most of Linux's drivers.
	237	* XXX ehs: Should this happen in PCI Device mode?
	238	*/
	239
e790a464 TB	240	bcm1480_controller.io_map_base = (unsigned long)
e790a464 TB	241	ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536);
cf7b7e0b	242	bcm1480_controller.io_map_base -= bcm1480_controller.io_offset;
e790a464	243	set_io_port_base(bcm1480_controller.io_map_base);
dc41f94f AI	244
	245	register_pci_controller(&bcm1480_controller);
	246
	247	#ifdef CONFIG_VGA_CONSOLE
155957f5 WY	248	console_lock();
	249	do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
	250	console_unlock();
dc41f94f AI	251	#endif
	252	return 0;
	253	}
	254
	255	arch_initcall(bcm1480_pcibios_init);