[mirror_ubuntu-hirsute-kernel.git] / arch / mips / pci / pci-legacy.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *
 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2011 Wind River Systems,
 *   written by Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/memblock.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/of_address.h>

#include <asm/cpu-info.h>

/*
 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
 * assignments.
 */

/*
 * The PCI controller list.
 */
static LIST_HEAD(controllers);

static int pci_initialized;

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
		       resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_controller *hose = dev->sysdata;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
			start = PCIBIOS_MIN_IO + hose->io_resource->start;

		/*
		 * Put everything into 0x00-0xff region modulo 0x400
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	} else if (res->flags & IORESOURCE_MEM) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	}

	return start;
}

static void pcibios_scanbus(struct pci_controller *hose)
{
	static int next_busno;
	static int need_domain_info;
	LIST_HEAD(resources);
	struct pci_bus *bus;
	struct pci_host_bridge *bridge;
	int ret;

	bridge = pci_alloc_host_bridge(0);
	if (!bridge)
		return;

	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
		next_busno = (*hose->get_busno)();

	pci_add_resource_offset(&resources,
				hose->mem_resource, hose->mem_offset);
	pci_add_resource_offset(&resources,
				hose->io_resource, hose->io_offset);
	pci_add_resource(&resources, hose->busn_resource);
	list_splice_init(&resources, &bridge->windows);
	bridge->dev.parent = NULL;
	bridge->sysdata = hose;
	bridge->busnr = next_busno;
	bridge->ops = hose->pci_ops;
	bridge->swizzle_irq = pci_common_swizzle;
	bridge->map_irq = pcibios_map_irq;
	ret = pci_scan_root_bus_bridge(bridge);
	if (ret) {
		pci_free_host_bridge(bridge);
		return;
	}

	hose->bus = bus = bridge->bus;

	need_domain_info = need_domain_info || pci_domain_nr(bus);
	set_pci_need_domain_info(hose, need_domain_info);

	next_busno = bus->busn_res.end + 1;
	/* Don't allow 8-bit bus number overflow inside the hose -
	   reserve some space for bridges. */
	if (next_busno > 224) {
		next_busno = 0;
		need_domain_info = 1;
	}

	/*
	 * We insert PCI resources into the iomem_resource and
	 * ioport_resource trees in either pci_bus_claim_resources()
	 * or pci_bus_assign_resources().
	 */
	if (pci_has_flag(PCI_PROBE_ONLY)) {
		pci_bus_claim_resources(bus);
	} else {
		struct pci_bus *child;

		pci_bus_size_bridges(bus);
		pci_bus_assign_resources(bus);
		list_for_each_entry(child, &bus->children, node)
			pcie_bus_configure_settings(child);
	}
	pci_bus_add_devices(bus);
}

#ifdef CONFIG_OF
void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
{
	struct of_pci_range range;
	struct of_pci_range_parser parser;

	pr_info("PCI host bridge %pOF ranges:\n", node);
	hose->of_node = node;

	if (of_pci_range_parser_init(&parser, node))
		return;

	for_each_of_pci_range(&parser, &range) {
		struct resource *res = NULL;

		switch (range.flags & IORESOURCE_TYPE_BITS) {
		case IORESOURCE_IO:
			pr_info("  IO 0x%016llx..0x%016llx\n",
				range.cpu_addr,
				range.cpu_addr + range.size - 1);
			hose->io_map_base =
				(unsigned long)ioremap(range.cpu_addr,
						       range.size);
			res = hose->io_resource;
			break;
		case IORESOURCE_MEM:
			pr_info(" MEM 0x%016llx..0x%016llx\n",
				range.cpu_addr,
				range.cpu_addr + range.size - 1);
			res = hose->mem_resource;
			break;
		}
		if (res != NULL) {
			res->name = node->full_name;
			res->flags = range.flags;
			res->start = range.cpu_addr;
			res->end = range.cpu_addr + range.size - 1;
			res->parent = res->child = res->sibling = NULL;
		}
	}
}

struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
{
	struct pci_controller *hose = bus->sysdata;

	return of_node_get(hose->of_node);
}
#endif

static DEFINE_MUTEX(pci_scan_mutex);

void register_pci_controller(struct pci_controller *hose)
{
	struct resource *parent;

	parent = hose->mem_resource->parent;
	if (!parent)
		parent = &iomem_resource;

	if (request_resource(parent, hose->mem_resource) < 0)
		goto out;

	parent = hose->io_resource->parent;
	if (!parent)
		parent = &ioport_resource;

	if (request_resource(parent, hose->io_resource) < 0) {
		release_resource(hose->mem_resource);
		goto out;
	}

	INIT_LIST_HEAD(&hose->list);
	list_add_tail(&hose->list, &controllers);

	/*
	 * Do not panic here but later - this might happen before console init.
	 */
	if (!hose->io_map_base) {
		printk(KERN_WARNING
		       "registering PCI controller with io_map_base unset\n");
	}

	/*
	 * Scan the bus if it is register after the PCI subsystem
	 * initialization.
	 */
	if (pci_initialized) {
		mutex_lock(&pci_scan_mutex);
		pcibios_scanbus(hose);
		mutex_unlock(&pci_scan_mutex);
	}

	return;

out:
	printk(KERN_WARNING
	       "Skipping PCI bus scan due to resource conflict\n");
}

static int __init pcibios_init(void)
{
	struct pci_controller *hose;

	/* Scan all of the recorded PCI controllers.  */
	list_for_each_entry(hose, &controllers, list)
		pcibios_scanbus(hose);

	pci_initialized = 1;

	return 0;
}

subsys_initcall(pcibios_init);

static int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
		/* Only set up the requested stuff */
		if (!(mask & (1<<idx)))
			continue;

		r = &dev->resource[idx];
		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((idx == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;
		if (!r->start && r->end) {
			pci_err(dev,
				"can't enable device: resource collisions\n");
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (cmd != old_cmd) {
		pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;

	if ((err = pcibios_enable_resources(dev, mask)) < 0)
		return err;

	return pcibios_plat_dev_init(dev);
}

void pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_dev *dev = bus->self;

	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
		pci_read_bridge_bases(bus);
	}
}

char * (*pcibios_plat_setup)(char *str) __initdata;

char *__init pcibios_setup(char *str)
{
	if (pcibios_plat_setup)
		return pcibios_plat_setup(str);
	return str;
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
f8091a88	2	/*
f8091a88 PB	3	*
	4	* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
	5	* Copyright (C) 2011 Wind River Systems,
	6	* written by Ralf Baechle (ralf@linux-mips.org)
	7	*/
	8	#include <linux/bug.h>
	9	#include <linux/kernel.h>
	10	#include <linux/mm.h>
57c8a661	11	#include <linux/memblock.h>
f8091a88 PB	12	#include <linux/export.h>
	13	#include <linux/init.h>
	14	#include <linux/types.h>
	15	#include <linux/pci.h>
	16	#include <linux/of_address.h>
	17
	18	#include <asm/cpu-info.h>
	19
	20	/*
	21	* If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
	22	* assignments.
	23	*/
	24
	25	/*
	26	* The PCI controller list.
	27	*/
	28	static LIST_HEAD(controllers);
	29
	30	static int pci_initialized;
	31
	32	/*
	33	* We need to avoid collisions with `mirrored' VGA ports
	34	* and other strange ISA hardware, so we always want the
	35	* addresses to be allocated in the 0x000-0x0ff region
	36	* modulo 0x400.
	37	*
	38	* Why? Because some silly external IO cards only decode
	39	* the low 10 bits of the IO address. The 0x00-0xff region
	40	* is reserved for motherboard devices that decode all 16
	41	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	42	* but we want to try to avoid allocating at 0x2900-0x2bff
	43	* which might have be mirrored at 0x0100-0x03ff..
	44	*/
	45	resource_size_t
	46	pcibios_align_resource(void data, const struct resource res,
	47	resource_size_t size, resource_size_t align)
	48	{
	49	struct pci_dev *dev = data;
	50	struct pci_controller *hose = dev->sysdata;
	51	resource_size_t start = res->start;
	52
	53	if (res->flags & IORESOURCE_IO) {
	54	/* Make sure we start at our min on all hoses */
	55	if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
	56	start = PCIBIOS_MIN_IO + hose->io_resource->start;
	57
	58	/*
	59	* Put everything into 0x00-0xff region modulo 0x400
	60	*/
	61	if (start & 0x300)
	62	start = (start + 0x3ff) & ~0x3ff;
	63	} else if (res->flags & IORESOURCE_MEM) {
	64	/* Make sure we start at our min on all hoses */
	65	if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
	66	start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	67	}
	68
	69	return start;
	70	}
	71
	72	static void pcibios_scanbus(struct pci_controller *hose)
	73	{
	74	static int next_busno;
	75	static int need_domain_info;
76	LIST_HEAD(resources);
77	struct pci_bus *bus;
04c81c72 LP	78	struct pci_host_bridge *bridge;
	79	int ret;
	80
	81	bridge = pci_alloc_host_bridge(0);
	82	if (!bridge)
	83	return;
f8091a88 PB	84
	85	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
	86	next_busno = (*hose->get_busno)();
	87
	88	pci_add_resource_offset(&resources,
	89	hose->mem_resource, hose->mem_offset);
	90	pci_add_resource_offset(&resources,
	91	hose->io_resource, hose->io_offset);
7ee214b5	92	pci_add_resource(&resources, hose->busn_resource);
04c81c72 LP	93	list_splice_init(&resources, &bridge->windows);
	94	bridge->dev.parent = NULL;
	95	bridge->sysdata = hose;
	96	bridge->busnr = next_busno;
	97	bridge->ops = hose->pci_ops;
	98	bridge->swizzle_irq = pci_common_swizzle;
	99	bridge->map_irq = pcibios_map_irq;
	100	ret = pci_scan_root_bus_bridge(bridge);
	101	if (ret) {
	102	pci_free_host_bridge(bridge);
f8091a88 PB	103	return;
	104	}
	105
04c81c72	106	hose->bus = bus = bridge->bus;
902d886d LP	107
	108	need_domain_info = need_domain_info \|\| pci_domain_nr(bus);
	109	set_pci_need_domain_info(hose, need_domain_info);
	110
f8091a88 PB	111	next_busno = bus->busn_res.end + 1;
	112	/* Don't allow 8-bit bus number overflow inside the hose -
	113	reserve some space for bridges. */
	114	if (next_busno > 224) {
	115	next_busno = 0;
	116	need_domain_info = 1;
	117	}
	118
	119	/*
	120	* We insert PCI resources into the iomem_resource and
	121	* ioport_resource trees in either pci_bus_claim_resources()
	122	* or pci_bus_assign_resources().
	123	*/
	124	if (pci_has_flag(PCI_PROBE_ONLY)) {
	125	pci_bus_claim_resources(bus);
	126	} else {
2794f688 HC	127	struct pci_bus *child;
2794f688 HC	128
f8091a88 PB	129	pci_bus_size_bridges(bus);
f8091a88 PB	130	pci_bus_assign_resources(bus);
2794f688 HC	131	list_for_each_entry(child, &bus->children, node)
2794f688 HC	132	pcie_bus_configure_settings(child);
f8091a88 PB	133	}
	134	pci_bus_add_devices(bus);
	135	}
	136
	137	#ifdef CONFIG_OF
	138	void pci_load_of_ranges(struct pci_controller hose, struct device_node node)
	139	{
	140	struct of_pci_range range;
	141	struct of_pci_range_parser parser;
	142
7f27b5b8	143	pr_info("PCI host bridge %pOF ranges:\n", node);
f8091a88 PB	144	hose->of_node = node;
	145
	146	if (of_pci_range_parser_init(&parser, node))
	147	return;
	148
	149	for_each_of_pci_range(&parser, &range) {
	150	struct resource *res = NULL;
	151
	152	switch (range.flags & IORESOURCE_TYPE_BITS) {
	153	case IORESOURCE_IO:
	154	pr_info(" IO 0x%016llx..0x%016llx\n",
	155	range.cpu_addr,
	156	range.cpu_addr + range.size - 1);
	157	hose->io_map_base =
	158	(unsigned long)ioremap(range.cpu_addr,
	159	range.size);
	160	res = hose->io_resource;
	161	break;
	162	case IORESOURCE_MEM:
	163	pr_info(" MEM 0x%016llx..0x%016llx\n",
	164	range.cpu_addr,
	165	range.cpu_addr + range.size - 1);
	166	res = hose->mem_resource;
	167	break;
	168	}
34a0d318 IL	169	if (res != NULL) {
	170	res->name = node->full_name;
	171	res->flags = range.flags;
	172	res->start = range.cpu_addr;
	173	res->end = range.cpu_addr + range.size - 1;
	174	res->parent = res->child = res->sibling = NULL;
	175	}
f8091a88 PB	176	}
	177	}
	178
	179	struct device_node pcibios_get_phb_of_node(struct pci_bus bus)
	180	{
	181	struct pci_controller *hose = bus->sysdata;
	182
	183	return of_node_get(hose->of_node);
	184	}
	185	#endif
	186
	187	static DEFINE_MUTEX(pci_scan_mutex);
	188
	189	void register_pci_controller(struct pci_controller *hose)
	190	{
	191	struct resource *parent;
	192
	193	parent = hose->mem_resource->parent;
	194	if (!parent)
	195	parent = &iomem_resource;
	196
	197	if (request_resource(parent, hose->mem_resource) < 0)
	198	goto out;
	199
	200	parent = hose->io_resource->parent;
	201	if (!parent)
	202	parent = &ioport_resource;
	203
	204	if (request_resource(parent, hose->io_resource) < 0) {
	205	release_resource(hose->mem_resource);
	206	goto out;
	207	}
	208
	209	INIT_LIST_HEAD(&hose->list);
edb0b6a0	210	list_add_tail(&hose->list, &controllers);
f8091a88 PB	211
	212	/*
	213	* Do not panic here but later - this might happen before console init.
	214	*/
	215	if (!hose->io_map_base) {
	216	printk(KERN_WARNING
	217	"registering PCI controller with io_map_base unset\n");
	218	}
	219
	220	/*
	221	* Scan the bus if it is register after the PCI subsystem
	222	* initialization.
	223	*/
	224	if (pci_initialized) {
	225	mutex_lock(&pci_scan_mutex);
	226	pcibios_scanbus(hose);
	227	mutex_unlock(&pci_scan_mutex);
	228	}
	229
	230	return;
	231
	232	out:
	233	printk(KERN_WARNING
	234	"Skipping PCI bus scan due to resource conflict\n");
	235	}
	236
	237	static int __init pcibios_init(void)
	238	{
	239	struct pci_controller *hose;
	240
	241	/* Scan all of the recorded PCI controllers. */
	242	list_for_each_entry(hose, &controllers, list)
	243	pcibios_scanbus(hose);
	244
f8091a88 PB	245	pci_initialized = 1;
	246
	247	return 0;
	248	}
	249
	250	subsys_initcall(pcibios_init);
	251
	252	static int pcibios_enable_resources(struct pci_dev *dev, int mask)
	253	{
	254	u16 cmd, old_cmd;
	255	int idx;
	256	struct resource *r;
	257
	258	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	259	old_cmd = cmd;
	260	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
	261	/* Only set up the requested stuff */
	262	if (!(mask & (1<<idx)))
	263	continue;
	264
	265	r = &dev->resource[idx];
	266	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	267	continue;
	268	if ((idx == PCI_ROM_RESOURCE) &&
	269	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	270	continue;
	271	if (!r->start && r->end) {
77edfac4 BH	272	pci_err(dev,
77edfac4 BH	273	"can't enable device: resource collisions\n");
f8091a88 PB	274	return -EINVAL;
	275	}
	276	if (r->flags & IORESOURCE_IO)
	277	cmd \|= PCI_COMMAND_IO;
	278	if (r->flags & IORESOURCE_MEM)
	279	cmd \|= PCI_COMMAND_MEMORY;
	280	}
	281	if (cmd != old_cmd) {
77edfac4	282	pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
f8091a88 PB	283	pci_write_config_word(dev, PCI_COMMAND, cmd);
	284	}
	285	return 0;
	286	}
	287
	288	int pcibios_enable_device(struct pci_dev *dev, int mask)
	289	{
	290	int err;
	291
	292	if ((err = pcibios_enable_resources(dev, mask)) < 0)
	293	return err;
	294
	295	return pcibios_plat_dev_init(dev);
	296	}
	297
	298	void pcibios_fixup_bus(struct pci_bus *bus)
	299	{
	300	struct pci_dev *dev = bus->self;
	301
	302	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
	303	(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
	304	pci_read_bridge_bases(bus);
	305	}
	306	}
	307
	308	char * (pcibios_plat_setup)(char str) __initdata;
	309
	310	char __init pcibios_setup(char str)
	311	{
	312	if (pcibios_plat_setup)
	313	return pcibios_plat_setup(str);
	314	return str;
	315	}