[mirror_ubuntu-jammy-kernel.git] / arch / mips / pci / pci-mt7620.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *  Ralink MT7620A SoC PCI support
 *
 *  Copyright (C) 2007-2013 Bruce Chang (Mediatek)
 *  Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
 */

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/reset.h>
#include <linux/platform_device.h>

#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7620.h>

#define RALINK_PCI_IO_MAP_BASE		0x10160000
#define RALINK_PCI_MEMORY_BASE		0x0

#define RALINK_INT_PCIE0		4

#define RALINK_CLKCFG1			0x30
#define RALINK_GPIOMODE			0x60

#define PPLL_CFG1			0x9c

#define PPLL_DRV			0xa0
#define PDRV_SW_SET			BIT(31)
#define LC_CKDRVPD			BIT(19)
#define LC_CKDRVOHZ			BIT(18)
#define LC_CKDRVHZ			BIT(17)
#define LC_CKTEST			BIT(16)

/* PCI Bridge registers */
#define RALINK_PCI_PCICFG_ADDR		0x00
#define PCIRST				BIT(1)

#define RALINK_PCI_PCIENA		0x0C
#define PCIINT2				BIT(20)

#define RALINK_PCI_CONFIG_ADDR		0x20
#define RALINK_PCI_CONFIG_DATA_VIRT_REG	0x24
#define RALINK_PCI_MEMBASE		0x28
#define RALINK_PCI_IOBASE		0x2C

/* PCI RC registers */
#define RALINK_PCI0_BAR0SETUP_ADDR	0x10
#define RALINK_PCI0_IMBASEBAR0_ADDR	0x18
#define RALINK_PCI0_ID			0x30
#define RALINK_PCI0_CLASS		0x34
#define RALINK_PCI0_SUBID		0x38
#define RALINK_PCI0_STATUS		0x50
#define PCIE_LINK_UP_ST			BIT(0)

#define PCIEPHY0_CFG			0x90

#define RALINK_PCIEPHY_P0_CTL_OFFSET	0x7498
#define RALINK_PCIE0_CLK_EN		BIT(26)

#define BUSY				0x80000000
#define WAITRETRY_MAX			10
#define WRITE_MODE			(1UL << 23)
#define DATA_SHIFT			0
#define ADDR_SHIFT			8


static void __iomem *bridge_base;
static void __iomem *pcie_base;

static struct reset_control *rstpcie0;

static inline void bridge_w32(u32 val, unsigned reg)
{
	iowrite32(val, bridge_base + reg);
}

static inline u32 bridge_r32(unsigned reg)
{
	return ioread32(bridge_base + reg);
}

static inline void pcie_w32(u32 val, unsigned reg)
{
	iowrite32(val, pcie_base + reg);
}

static inline u32 pcie_r32(unsigned reg)
{
	return ioread32(pcie_base + reg);
}

static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
{
	u32 val = pcie_r32(reg);

	val &= ~clr;
	val |= set;
	pcie_w32(val, reg);
}

static int wait_pciephy_busy(void)
{
	unsigned long reg_value = 0x0, retry = 0;

	while (1) {
		reg_value = pcie_r32(PCIEPHY0_CFG);

		if (reg_value & BUSY)
			mdelay(100);
		else
			break;
		if (retry++ > WAITRETRY_MAX) {
			pr_warn("PCIE-PHY retry failed.\n");
			return -1;
		}
	}
	return 0;
}

static void pcie_phy(unsigned long addr, unsigned long val)
{
	wait_pciephy_busy();
	pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT),
		 PCIEPHY0_CFG);
	mdelay(1);
	wait_pciephy_busy();
}

static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
			   int size, u32 *val)
{
	unsigned int slot = PCI_SLOT(devfn);
	u8 func = PCI_FUNC(devfn);
	u32 address;
	u32 data;
	u32 num = 0;

	if (bus)
		num = bus->number;

	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
		  (func << 8) | (where & 0xfc) | 0x80000000;
	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);

	switch (size) {
	case 1:
		*val = (data >> ((where & 3) << 3)) & 0xff;
		break;
	case 2:
		*val = (data >> ((where & 3) << 3)) & 0xffff;
		break;
	case 4:
		*val = data;
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
			    int size, u32 val)
{
	unsigned int slot = PCI_SLOT(devfn);
	u8 func = PCI_FUNC(devfn);
	u32 address;
	u32 data;
	u32 num = 0;

	if (bus)
		num = bus->number;

	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
		  (func << 8) | (where & 0xfc) | 0x80000000;
	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);

	switch (size) {
	case 1:
		data = (data & ~(0xff << ((where & 3) << 3))) |
			(val << ((where & 3) << 3));
		break;
	case 2:
		data = (data & ~(0xffff << ((where & 3) << 3))) |
			(val << ((where & 3) << 3));
		break;
	case 4:
		data = val;
		break;
	}

	bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops mt7620_pci_ops = {
	.read	= pci_config_read,
	.write	= pci_config_write,
};

static struct resource mt7620_res_pci_mem1;
static struct resource mt7620_res_pci_io1;
struct pci_controller mt7620_controller = {
	.pci_ops	= &mt7620_pci_ops,
	.mem_resource	= &mt7620_res_pci_mem1,
	.mem_offset	= 0x00000000UL,
	.io_resource	= &mt7620_res_pci_io1,
	.io_offset	= 0x00000000UL,
	.io_map_base	= 0xa0000000,
};

static int mt7620_pci_hw_init(struct platform_device *pdev)
{
	/* bypass PCIe DLL */
	pcie_phy(0x0, 0x80);
	pcie_phy(0x1, 0x04);

	/* Elastic buffer control */
	pcie_phy(0x68, 0xB4);

	/* put core into reset */
	pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
	reset_control_assert(rstpcie0);

	/* disable power and all clocks */
	rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
	rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);

	/* bring core out of reset */
	reset_control_deassert(rstpcie0);
	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
	mdelay(100);

	if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
		dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
		reset_control_assert(rstpcie0);
		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
		return -1;
	}

	/* power up the bus */
	rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
		    PPLL_DRV);

	return 0;
}

static int mt7628_pci_hw_init(struct platform_device *pdev)
{
	u32 val = 0;

	/* bring the core out of reset */
	rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
	reset_control_deassert(rstpcie0);

	/* enable the pci clk */
	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
	mdelay(100);

	/* voodoo from the SDK driver */
	pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);

	pci_config_read(NULL, 0, 0x70c, 4, &val);
	val &= ~(0xff) << 8;
	val |= 0x50 << 8;
	pci_config_write(NULL, 0, 0x70c, 4, val);

	pci_config_read(NULL, 0, 0x70c, 4, &val);
	dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);

	return 0;
}

static int mt7620_pci_probe(struct platform_device *pdev)
{
	struct resource *bridge_res = platform_get_resource(pdev,
							    IORESOURCE_MEM, 0);
	struct resource *pcie_res = platform_get_resource(pdev,
							  IORESOURCE_MEM, 1);
	u32 val = 0;

	rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
	if (IS_ERR(rstpcie0))
		return PTR_ERR(rstpcie0);

	bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
	if (IS_ERR(bridge_base))
		return PTR_ERR(bridge_base);

	pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
	if (IS_ERR(pcie_base))
		return PTR_ERR(pcie_base);

	iomem_resource.start = 0;
	iomem_resource.end = ~0;
	ioport_resource.start = 0;
	ioport_resource.end = ~0;

	/* bring up the pci core */
	switch (ralink_soc) {
	case MT762X_SOC_MT7620A:
		if (mt7620_pci_hw_init(pdev))
			return -1;
		break;

	case MT762X_SOC_MT7628AN:
	case MT762X_SOC_MT7688:
		if (mt7628_pci_hw_init(pdev))
			return -1;
		break;

	default:
		dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
		return -1;
	}
	mdelay(50);

	/* enable write access */
	pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
	mdelay(100);

	/* check if there is a card present */
	if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
		reset_control_assert(rstpcie0);
		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
		if (ralink_soc == MT762X_SOC_MT7620A)
			rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
		dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
		return -1;
	}

	/* setup ranges */
	bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
	bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);

	pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
	pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
	pcie_w32(0x06040001, RALINK_PCI0_CLASS);

	/* enable interrupts */
	pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);

	/* voodoo from the SDK driver */
	pci_config_read(NULL, 0, 4, 4, &val);
	pci_config_write(NULL, 0, 4, 4, val | 0x7);

	pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
	register_pci_controller(&mt7620_controller);

	return 0;
}

int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	u16 cmd;
	u32 val;
	int irq = 0;

	if ((dev->bus->number == 0) && (slot == 0)) {
		pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
		pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
				 RALINK_PCI_MEMORY_BASE);
		pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
	} else if ((dev->bus->number == 1) && (slot == 0x0)) {
		irq = RALINK_INT_PCIE0;
	} else {
		dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
			dev->bus->number, slot);
		return 0;
	}
	dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
		dev->bus->number, slot, irq);

	/* configure the cache line size to 0x14 */
	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);

	/* configure latency timer to 0xff */
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
	pci_read_config_word(dev, PCI_COMMAND, &cmd);

	/* setup the slot */
	cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
	pci_write_config_word(dev, PCI_COMMAND, cmd);
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);

	return irq;
}

int pcibios_plat_dev_init(struct pci_dev *dev)
{
	return 0;
}

static const struct of_device_id mt7620_pci_ids[] = {
	{ .compatible = "mediatek,mt7620-pci" },
	{},
};

static struct platform_driver mt7620_pci_driver = {
	.probe = mt7620_pci_probe,
	.driver = {
		.name = "mt7620-pci",
		.of_match_table = of_match_ptr(mt7620_pci_ids),
	},
};

static int __init mt7620_pci_init(void)
{
	return platform_driver_register(&mt7620_pci_driver);
}

arch_initcall(mt7620_pci_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
7e5873d3 JC	2	/*
	3	* Ralink MT7620A SoC PCI support
	4	*
	5	* Copyright (C) 2007-2013 Bruce Chang (Mediatek)
97b92108	6	* Copyright (C) 2013-2016 John Crispin <john@phrozen.org>
7e5873d3 JC	7	*/
	8
	9	#include <linux/types.h>
	10	#include <linux/pci.h>
	11	#include <linux/io.h>
	12	#include <linux/init.h>
	13	#include <linux/delay.h>
	14	#include <linux/interrupt.h>
7e5873d3 JC	15	#include <linux/of.h>
	16	#include <linux/of_irq.h>
	17	#include <linux/of_pci.h>
	18	#include <linux/reset.h>
	19	#include <linux/platform_device.h>
	20
	21	#include <asm/mach-ralink/ralink_regs.h>
	22	#include <asm/mach-ralink/mt7620.h>
	23
	24	#define RALINK_PCI_IO_MAP_BASE 0x10160000
	25	#define RALINK_PCI_MEMORY_BASE 0x0
	26
	27	#define RALINK_INT_PCIE0 4
	28
	29	#define RALINK_CLKCFG1 0x30
	30	#define RALINK_GPIOMODE 0x60
	31
	32	#define PPLL_CFG1 0x9c
7e5873d3 JC	33
7e5873d3 JC	34	#define PPLL_DRV 0xa0
b54fcf6a JC	35	#define PDRV_SW_SET BIT(31)
	36	#define LC_CKDRVPD BIT(19)
	37	#define LC_CKDRVOHZ BIT(18)
	38	#define LC_CKDRVHZ BIT(17)
	39	#define LC_CKTEST BIT(16)
7e5873d3 JC	40
	41	/* PCI Bridge registers */
	42	#define RALINK_PCI_PCICFG_ADDR 0x00
	43	#define PCIRST BIT(1)
	44
	45	#define RALINK_PCI_PCIENA 0x0C
	46	#define PCIINT2 BIT(20)
	47
	48	#define RALINK_PCI_CONFIG_ADDR 0x20
	49	#define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
	50	#define RALINK_PCI_MEMBASE 0x28
	51	#define RALINK_PCI_IOBASE 0x2C
	52
	53	/* PCI RC registers */
	54	#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
	55	#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
	56	#define RALINK_PCI0_ID 0x30
	57	#define RALINK_PCI0_CLASS 0x34
	58	#define RALINK_PCI0_SUBID 0x38
	59	#define RALINK_PCI0_STATUS 0x50
	60	#define PCIE_LINK_UP_ST BIT(0)
	61
	62	#define PCIEPHY0_CFG 0x90
	63
	64	#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
b54fcf6a	65	#define RALINK_PCIE0_CLK_EN BIT(26)
7e5873d3 JC	66
	67	#define BUSY 0x80000000
	68	#define WAITRETRY_MAX 10
	69	#define WRITE_MODE (1UL << 23)
	70	#define DATA_SHIFT 0
	71	#define ADDR_SHIFT 8
	72
	73
	74	static void __iomem *bridge_base;
	75	static void __iomem *pcie_base;
	76
	77	static struct reset_control *rstpcie0;
	78
	79	static inline void bridge_w32(u32 val, unsigned reg)
	80	{
	81	iowrite32(val, bridge_base + reg);
	82	}
	83
	84	static inline u32 bridge_r32(unsigned reg)
	85	{
	86	return ioread32(bridge_base + reg);
	87	}
	88
	89	static inline void pcie_w32(u32 val, unsigned reg)
	90	{
	91	iowrite32(val, pcie_base + reg);
	92	}
	93
	94	static inline u32 pcie_r32(unsigned reg)
	95	{
	96	return ioread32(pcie_base + reg);
	97	}
	98
	99	static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
	100	{
	101	u32 val = pcie_r32(reg);
	102
	103	val &= ~clr;
	104	val \|= set;
	105	pcie_w32(val, reg);
	106	}
	107
	108	static int wait_pciephy_busy(void)
	109	{
	110	unsigned long reg_value = 0x0, retry = 0;
	111
	112	while (1) {
	113	reg_value = pcie_r32(PCIEPHY0_CFG);
	114
	115	if (reg_value & BUSY)
	116	mdelay(100);
	117	else
	118	break;
	119	if (retry++ > WAITRETRY_MAX) {
8593b18a	120	pr_warn("PCIE-PHY retry failed.\n");
7e5873d3 JC	121	return -1;
	122	}
	123	}
	124	return 0;
	125	}
	126
	127	static void pcie_phy(unsigned long addr, unsigned long val)
	128	{
	129	wait_pciephy_busy();
	130	pcie_w32(WRITE_MODE \| (val << DATA_SHIFT) \| (addr << ADDR_SHIFT),
	131	PCIEPHY0_CFG);
	132	mdelay(1);
	133	wait_pciephy_busy();
	134	}
	135
	136	static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
	137	int size, u32 *val)
	138	{
	139	unsigned int slot = PCI_SLOT(devfn);
	140	u8 func = PCI_FUNC(devfn);
	141	u32 address;
	142	u32 data;
	143	u32 num = 0;
	144
	145	if (bus)
	146	num = bus->number;
	147
	148	address = (((where & 0xF00) >> 8) << 24) \| (num << 16) \| (slot << 11) \|
	149	(func << 8) \| (where & 0xfc) \| 0x80000000;
	150	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
	151	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
	152
	153	switch (size) {
	154	case 1:
	155	*val = (data >> ((where & 3) << 3)) & 0xff;
	156	break;
	157	case 2:
	158	*val = (data >> ((where & 3) << 3)) & 0xffff;
	159	break;
	160	case 4:
	161	*val = data;
	162	break;
	163	}
	164
	165	return PCIBIOS_SUCCESSFUL;
	166	}
	167
	168	static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
	169	int size, u32 val)
	170	{
	171	unsigned int slot = PCI_SLOT(devfn);
	172	u8 func = PCI_FUNC(devfn);
	173	u32 address;
	174	u32 data;
	175	u32 num = 0;
	176
	177	if (bus)
	178	num = bus->number;
	179
	180	address = (((where & 0xF00) >> 8) << 24) \| (num << 16) \| (slot << 11) \|
	181	(func << 8) \| (where & 0xfc) \| 0x80000000;
	182	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
	183	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
	184
185	switch (size) {
186	case 1:
187	data = (data & ~(0xff << ((where & 3) << 3))) \|
188	(val << ((where & 3) << 3));
189	break;
190	case 2:
191	data = (data & ~(0xffff << ((where & 3) << 3))) \|
192	(val << ((where & 3) << 3));
193	break;
194	case 4:
195	data = val;
196	break;
197	}
198
199	bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
200
201	return PCIBIOS_SUCCESSFUL;
202	}
203
204	struct pci_ops mt7620_pci_ops = {
205	.read = pci_config_read,
206	.write = pci_config_write,
207	};
208
209	static struct resource mt7620_res_pci_mem1;
210	static struct resource mt7620_res_pci_io1;
211	struct pci_controller mt7620_controller = {
212	.pci_ops = &mt7620_pci_ops,
213	.mem_resource = &mt7620_res_pci_mem1,
214	.mem_offset = 0x00000000UL,
215	.io_resource = &mt7620_res_pci_io1,
216	.io_offset = 0x00000000UL,
217	.io_map_base = 0xa0000000,
218	};
219
220	static int mt7620_pci_hw_init(struct platform_device *pdev)
221	{
222	/* bypass PCIe DLL */
223	pcie_phy(0x0, 0x80);
224	pcie_phy(0x1, 0x04);
225
226	/* Elastic buffer control */
227	pcie_phy(0x68, 0xB4);
228
229	/* put core into reset */
230	pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
231	reset_control_assert(rstpcie0);
232
233	/* disable power and all clocks */
234	rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
235	rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
236
237	/* bring core out of reset */
238	reset_control_deassert(rstpcie0);
239	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
240	mdelay(100);
241
242	if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
243	dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
244	reset_control_assert(rstpcie0);
245	rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
246	return -1;
247	}
248
249	/* power up the bus */
250	rt_sysc_m32(LC_CKDRVHZ \| LC_CKDRVOHZ, LC_CKDRVPD \| PDRV_SW_SET,
251	PPLL_DRV);
252
253	return 0;
254	}
255
256	static int mt7628_pci_hw_init(struct platform_device *pdev)
257	{
258	u32 val = 0;
259
260	/* bring the core out of reset */
261	rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
262	reset_control_deassert(rstpcie0);
263
264	/* enable the pci clk */
265	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
266	mdelay(100);
267
268	/* voodoo from the SDK driver */
269	pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
270
271	pci_config_read(NULL, 0, 0x70c, 4, &val);
272	val &= ~(0xff) << 8;
273	val \|= 0x50 << 8;
274	pci_config_write(NULL, 0, 0x70c, 4, val);
275
276	pci_config_read(NULL, 0, 0x70c, 4, &val);
277	dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
278
279	return 0;
280	}
281
282	static int mt7620_pci_probe(struct platform_device *pdev)
283	{
284	struct resource *bridge_res = platform_get_resource(pdev,
285	IORESOURCE_MEM, 0);
286	struct resource *pcie_res = platform_get_resource(pdev,
287	IORESOURCE_MEM, 1);
288	u32 val = 0;
289
0c4037b9	290	rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
7e5873d3 JC	291	if (IS_ERR(rstpcie0))
	292	return PTR_ERR(rstpcie0);
	293
	294	bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
aaa0bf22 WY	295	if (IS_ERR(bridge_base))
aaa0bf22 WY	296	return PTR_ERR(bridge_base);
7e5873d3 JC	297
7e5873d3 JC	298	pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
aaa0bf22 WY	299	if (IS_ERR(pcie_base))
aaa0bf22 WY	300	return PTR_ERR(pcie_base);
7e5873d3 JC	301
	302	iomem_resource.start = 0;
	303	iomem_resource.end = ~0;
	304	ioport_resource.start = 0;
	305	ioport_resource.end = ~0;
	306
	307	/* bring up the pci core */
	308	switch (ralink_soc) {
	309	case MT762X_SOC_MT7620A:
	310	if (mt7620_pci_hw_init(pdev))
	311	return -1;
	312	break;
	313
	314	case MT762X_SOC_MT7628AN:
60c5d893	315	case MT762X_SOC_MT7688:
7e5873d3 JC	316	if (mt7628_pci_hw_init(pdev))
	317	return -1;
	318	break;
	319
	320	default:
	321	dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
	322	return -1;
	323	}
	324	mdelay(50);
	325
	326	/* enable write access */
	327	pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
	328	mdelay(100);
	329
	330	/* check if there is a card present */
	331	if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
	332	reset_control_assert(rstpcie0);
	333	rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
	334	if (ralink_soc == MT762X_SOC_MT7620A)
	335	rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
	336	dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
	337	return -1;
	338	}
	339
	340	/* setup ranges */
	341	bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
	342	bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
	343
	344	pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
	345	pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
	346	pcie_w32(0x06040001, RALINK_PCI0_CLASS);
	347
	348	/* enable interrupts */
	349	pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
	350
	351	/* voodoo from the SDK driver */
	352	pci_config_read(NULL, 0, 4, 4, &val);
	353	pci_config_write(NULL, 0, 4, 4, val \| 0x7);
	354
	355	pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
	356	register_pci_controller(&mt7620_controller);
	357
	358	return 0;
	359	}
	360
8eba3651	361	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
7e5873d3 JC	362	{
	363	u16 cmd;
	364	u32 val;
	365	int irq = 0;
	366
	367	if ((dev->bus->number == 0) && (slot == 0)) {
	368	pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
	369	pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
	370	RALINK_PCI_MEMORY_BASE);
	371	pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
	372	} else if ((dev->bus->number == 1) && (slot == 0x0)) {
	373	irq = RALINK_INT_PCIE0;
	374	} else {
	375	dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
	376	dev->bus->number, slot);
	377	return 0;
	378	}
	379	dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
	380	dev->bus->number, slot, irq);
	381
	382	/* configure the cache line size to 0x14 */
	383	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
	384
	385	/* configure latency timer to 0xff */
	386	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
	387	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	388
	389	/* setup the slot */
	390	cmd = cmd \| PCI_COMMAND_MASTER \| PCI_COMMAND_IO \| PCI_COMMAND_MEMORY;
	391	pci_write_config_word(dev, PCI_COMMAND, cmd);
	392	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
	393
	394	return irq;
	395	}
	396
	397	int pcibios_plat_dev_init(struct pci_dev *dev)
	398	{
	399	return 0;
	400	}
	401
	402	static const struct of_device_id mt7620_pci_ids[] = {
	403	{ .compatible = "mediatek,mt7620-pci" },
	404	{},
	405	};
7e5873d3 JC	406
	407	static struct platform_driver mt7620_pci_driver = {
	408	.probe = mt7620_pci_probe,
	409	.driver = {
	410	.name = "mt7620-pci",
7e5873d3 JC	411	.of_match_table = of_match_ptr(mt7620_pci_ids),
	412	},
	413	};
	414
	415	static int __init mt7620_pci_init(void)
	416	{
	417	return platform_driver_register(&mt7620_pci_driver);
	418	}
	419
	420	arch_initcall(mt7620_pci_init);