]>
Commit | Line | Data |
---|---|---|
e8635b48 DD |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
01a6221a | 6 | * Copyright (C) 2005-2009 Cavium Networks |
e8635b48 DD |
7 | */ |
8 | #include <linux/kernel.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/time.h> | |
13 | #include <linux/delay.h> | |
f65aad41 | 14 | #include <linux/platform_device.h> |
b93b2abc | 15 | #include <linux/swiotlb.h> |
e8635b48 DD |
16 | |
17 | #include <asm/time.h> | |
18 | ||
19 | #include <asm/octeon/octeon.h> | |
20 | #include <asm/octeon/cvmx-npi-defs.h> | |
21 | #include <asm/octeon/cvmx-pci-defs.h> | |
01a6221a | 22 | #include <asm/octeon/pci-octeon.h> |
e8635b48 | 23 | |
b93b2abc DD |
24 | #include <dma-coherence.h> |
25 | ||
e8635b48 DD |
26 | #define USE_OCTEON_INTERNAL_ARBITER |
27 | ||
28 | /* | |
29 | * Octeon's PCI controller uses did=3, subdid=2 for PCI IO | |
30 | * addresses. Use PCI endian swapping 1 so no address swapping is | |
31 | * necessary. The Linux io routines will endian swap the data. | |
32 | */ | |
70342287 RB |
33 | #define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull |
34 | #define OCTEON_PCI_IOSPACE_SIZE (1ull<<32) | |
e8635b48 DD |
35 | |
36 | /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */ | |
37 | #define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull) | |
38 | ||
b93b2abc DD |
39 | u64 octeon_bar1_pci_phys; |
40 | ||
e8635b48 DD |
41 | /** |
42 | * This is the bit decoding used for the Octeon PCI controller addresses | |
43 | */ | |
44 | union octeon_pci_address { | |
45 | uint64_t u64; | |
46 | struct { | |
47 | uint64_t upper:2; | |
48 | uint64_t reserved:13; | |
49 | uint64_t io:1; | |
50 | uint64_t did:5; | |
51 | uint64_t subdid:3; | |
52 | uint64_t reserved2:4; | |
53 | uint64_t endian_swap:2; | |
54 | uint64_t reserved3:10; | |
55 | uint64_t bus:8; | |
56 | uint64_t dev:5; | |
57 | uint64_t func:3; | |
58 | uint64_t reg:8; | |
59 | } s; | |
60 | }; | |
61 | ||
3cf5ae6e | 62 | int __initconst (*octeon_pcibios_map_irq)(const struct pci_dev *dev, |
01a6221a DD |
63 | u8 slot, u8 pin); |
64 | enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID; | |
65 | ||
66 | /** | |
67 | * Map a PCI device to the appropriate interrupt line | |
68 | * | |
69 | * @dev: The Linux PCI device structure for the device to map | |
70 | * @slot: The slot number for this device on __BUS 0__. Linux | |
70342287 RB |
71 | * enumerates through all the bridges and figures out the |
72 | * slot on Bus 0 where this device eventually hooks to. | |
01a6221a | 73 | * @pin: The PCI interrupt pin read from the device, then swizzled |
70342287 | 74 | * as it goes through each bridge. |
01a6221a DD |
75 | * Returns Interrupt number for the device |
76 | */ | |
77 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | |
78 | { | |
79 | if (octeon_pcibios_map_irq) | |
80 | return octeon_pcibios_map_irq(dev, slot, pin); | |
81 | else | |
82 | panic("octeon_pcibios_map_irq not set."); | |
83 | } | |
84 | ||
85 | ||
86 | /* | |
87 | * Called to perform platform specific PCI setup | |
88 | */ | |
89 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
90 | { | |
91 | uint16_t config; | |
92 | uint32_t dconfig; | |
93 | int pos; | |
94 | /* | |
95 | * Force the Cache line setting to 64 bytes. The standard | |
96 | * Linux bus scan doesn't seem to set it. Octeon really has | |
97 | * 128 byte lines, but Intel bridges get really upset if you | |
98 | * try and set values above 64 bytes. Value is specified in | |
99 | * 32bit words. | |
100 | */ | |
101 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4); | |
102 | /* Set latency timers for all devices */ | |
53efc98e | 103 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
01a6221a DD |
104 | |
105 | /* Enable reporting System errors and parity errors on all devices */ | |
106 | /* Enable parity checking and error reporting */ | |
107 | pci_read_config_word(dev, PCI_COMMAND, &config); | |
108 | config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
109 | pci_write_config_word(dev, PCI_COMMAND, config); | |
110 | ||
111 | if (dev->subordinate) { | |
112 | /* Set latency timers on sub bridges */ | |
53efc98e | 113 | pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64); |
01a6221a DD |
114 | /* More bridge error detection */ |
115 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); | |
116 | config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; | |
117 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); | |
118 | } | |
119 | ||
120 | /* Enable the PCIe normal error reporting */ | |
39a3612e JL |
121 | config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ |
122 | config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */ | |
70342287 RB |
123 | config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */ |
124 | config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */ | |
39a3612e | 125 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config); |
01a6221a DD |
126 | |
127 | /* Find the Advanced Error Reporting capability */ | |
128 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
129 | if (pos) { | |
130 | /* Clear Uncorrectable Error Status */ | |
131 | pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, | |
132 | &dconfig); | |
133 | pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, | |
134 | dconfig); | |
135 | /* Enable reporting of all uncorrectable errors */ | |
136 | /* Uncorrectable Error Mask - turned on bits disable errors */ | |
137 | pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); | |
138 | /* | |
139 | * Leave severity at HW default. This only controls if | |
140 | * errors are reported as uncorrectable or | |
141 | * correctable, not if the error is reported. | |
142 | */ | |
143 | /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ | |
144 | /* Clear Correctable Error Status */ | |
145 | pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); | |
146 | pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); | |
147 | /* Enable reporting of all correctable errors */ | |
148 | /* Correctable Error Mask - turned on bits disable errors */ | |
149 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); | |
150 | /* Advanced Error Capabilities */ | |
151 | pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); | |
152 | /* ECRC Generation Enable */ | |
153 | if (config & PCI_ERR_CAP_ECRC_GENC) | |
154 | config |= PCI_ERR_CAP_ECRC_GENE; | |
155 | /* ECRC Check Enable */ | |
156 | if (config & PCI_ERR_CAP_ECRC_CHKC) | |
157 | config |= PCI_ERR_CAP_ECRC_CHKE; | |
158 | pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); | |
159 | /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ | |
160 | /* Report all errors to the root complex */ | |
161 | pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, | |
162 | PCI_ERR_ROOT_CMD_COR_EN | | |
163 | PCI_ERR_ROOT_CMD_NONFATAL_EN | | |
164 | PCI_ERR_ROOT_CMD_FATAL_EN); | |
165 | /* Clear the Root status register */ | |
166 | pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); | |
167 | pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); | |
168 | } | |
169 | ||
b93b2abc DD |
170 | dev->dev.archdata.dma_ops = octeon_pci_dma_map_ops; |
171 | ||
01a6221a DD |
172 | return 0; |
173 | } | |
174 | ||
e8635b48 DD |
175 | /** |
176 | * Return the mapping of PCI device number to IRQ line. Each | |
177 | * character in the return string represents the interrupt | |
178 | * line for the device at that position. Device 1 maps to the | |
179 | * first character, etc. The characters A-D are used for PCI | |
180 | * interrupts. | |
181 | * | |
182 | * Returns PCI interrupt mapping | |
183 | */ | |
184 | const char *octeon_get_pci_interrupts(void) | |
185 | { | |
186 | /* | |
187 | * Returning an empty string causes the interrupts to be | |
188 | * routed based on the PCI specification. From the PCI spec: | |
189 | * | |
190 | * INTA# of Device Number 0 is connected to IRQW on the system | |
191 | * board. (Device Number has no significance regarding being | |
192 | * located on the system board or in a connector.) INTA# of | |
193 | * Device Number 1 is connected to IRQX on the system | |
194 | * board. INTA# of Device Number 2 is connected to IRQY on the | |
195 | * system board. INTA# of Device Number 3 is connected to IRQZ | |
196 | * on the system board. The table below describes how each | |
197 | * agent's INTx# lines are connected to the system board | |
198 | * interrupt lines. The following equation can be used to | |
199 | * determine to which INTx# signal on the system board a given | |
200 | * device's INTx# line(s) is connected. | |
201 | * | |
202 | * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0, | |
203 | * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I = | |
204 | * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and | |
205 | * INTD# = 3) | |
206 | */ | |
207 | switch (octeon_bootinfo->board_type) { | |
208 | case CVMX_BOARD_TYPE_NAO38: | |
209 | /* This is really the NAC38 */ | |
210 | return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA"; | |
e8635b48 DD |
211 | case CVMX_BOARD_TYPE_EBH3100: |
212 | case CVMX_BOARD_TYPE_CN3010_EVB_HS5: | |
213 | case CVMX_BOARD_TYPE_CN3005_EVB_HS5: | |
214 | return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; | |
215 | case CVMX_BOARD_TYPE_BBGW_REF: | |
216 | return "AABCD"; | |
2fe06260 RK |
217 | case CVMX_BOARD_TYPE_THUNDER: |
218 | case CVMX_BOARD_TYPE_EBH3000: | |
e8635b48 DD |
219 | default: |
220 | return ""; | |
221 | } | |
222 | } | |
223 | ||
224 | /** | |
225 | * Map a PCI device to the appropriate interrupt line | |
226 | * | |
227 | * @dev: The Linux PCI device structure for the device to map | |
228 | * @slot: The slot number for this device on __BUS 0__. Linux | |
70342287 RB |
229 | * enumerates through all the bridges and figures out the |
230 | * slot on Bus 0 where this device eventually hooks to. | |
e8635b48 | 231 | * @pin: The PCI interrupt pin read from the device, then swizzled |
70342287 | 232 | * as it goes through each bridge. |
e8635b48 DD |
233 | * Returns Interrupt number for the device |
234 | */ | |
235 | int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev, | |
236 | u8 slot, u8 pin) | |
237 | { | |
238 | int irq_num; | |
239 | const char *interrupts; | |
240 | int dev_num; | |
241 | ||
242 | /* Get the board specific interrupt mapping */ | |
243 | interrupts = octeon_get_pci_interrupts(); | |
244 | ||
245 | dev_num = dev->devfn >> 3; | |
246 | if (dev_num < strlen(interrupts)) | |
247 | irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) + | |
248 | OCTEON_IRQ_PCI_INT0; | |
249 | else | |
250 | irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0; | |
251 | return irq_num; | |
252 | } | |
253 | ||
254 | ||
01a6221a | 255 | /* |
e8635b48 | 256 | * Read a value from configuration space |
e8635b48 DD |
257 | */ |
258 | static int octeon_read_config(struct pci_bus *bus, unsigned int devfn, | |
259 | int reg, int size, u32 *val) | |
260 | { | |
261 | union octeon_pci_address pci_addr; | |
262 | ||
263 | pci_addr.u64 = 0; | |
264 | pci_addr.s.upper = 2; | |
265 | pci_addr.s.io = 1; | |
266 | pci_addr.s.did = 3; | |
267 | pci_addr.s.subdid = 1; | |
268 | pci_addr.s.endian_swap = 1; | |
269 | pci_addr.s.bus = bus->number; | |
270 | pci_addr.s.dev = devfn >> 3; | |
271 | pci_addr.s.func = devfn & 0x7; | |
272 | pci_addr.s.reg = reg; | |
273 | ||
274 | #if PCI_CONFIG_SPACE_DELAY | |
275 | udelay(PCI_CONFIG_SPACE_DELAY); | |
276 | #endif | |
277 | switch (size) { | |
278 | case 4: | |
279 | *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64)); | |
280 | return PCIBIOS_SUCCESSFUL; | |
281 | case 2: | |
282 | *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64)); | |
283 | return PCIBIOS_SUCCESSFUL; | |
284 | case 1: | |
285 | *val = cvmx_read64_uint8(pci_addr.u64); | |
286 | return PCIBIOS_SUCCESSFUL; | |
287 | } | |
288 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
289 | } | |
290 | ||
291 | ||
01a6221a | 292 | /* |
e8635b48 | 293 | * Write a value to PCI configuration space |
e8635b48 DD |
294 | */ |
295 | static int octeon_write_config(struct pci_bus *bus, unsigned int devfn, | |
296 | int reg, int size, u32 val) | |
297 | { | |
298 | union octeon_pci_address pci_addr; | |
299 | ||
300 | pci_addr.u64 = 0; | |
301 | pci_addr.s.upper = 2; | |
302 | pci_addr.s.io = 1; | |
303 | pci_addr.s.did = 3; | |
304 | pci_addr.s.subdid = 1; | |
305 | pci_addr.s.endian_swap = 1; | |
306 | pci_addr.s.bus = bus->number; | |
307 | pci_addr.s.dev = devfn >> 3; | |
308 | pci_addr.s.func = devfn & 0x7; | |
309 | pci_addr.s.reg = reg; | |
310 | ||
311 | #if PCI_CONFIG_SPACE_DELAY | |
312 | udelay(PCI_CONFIG_SPACE_DELAY); | |
313 | #endif | |
314 | switch (size) { | |
315 | case 4: | |
316 | cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val)); | |
317 | return PCIBIOS_SUCCESSFUL; | |
318 | case 2: | |
319 | cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val)); | |
320 | return PCIBIOS_SUCCESSFUL; | |
321 | case 1: | |
322 | cvmx_write64_uint8(pci_addr.u64, val); | |
323 | return PCIBIOS_SUCCESSFUL; | |
324 | } | |
325 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
326 | } | |
327 | ||
328 | ||
329 | static struct pci_ops octeon_pci_ops = { | |
330 | octeon_read_config, | |
331 | octeon_write_config, | |
332 | }; | |
333 | ||
334 | static struct resource octeon_pci_mem_resource = { | |
335 | .start = 0, | |
336 | .end = 0, | |
337 | .name = "Octeon PCI MEM", | |
338 | .flags = IORESOURCE_MEM, | |
339 | }; | |
340 | ||
341 | /* | |
342 | * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI | |
343 | * bridge | |
344 | */ | |
345 | static struct resource octeon_pci_io_resource = { | |
346 | .start = 0x4000, | |
347 | .end = OCTEON_PCI_IOSPACE_SIZE - 1, | |
348 | .name = "Octeon PCI IO", | |
349 | .flags = IORESOURCE_IO, | |
350 | }; | |
351 | ||
352 | static struct pci_controller octeon_pci_controller = { | |
353 | .pci_ops = &octeon_pci_ops, | |
354 | .mem_resource = &octeon_pci_mem_resource, | |
355 | .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET, | |
356 | .io_resource = &octeon_pci_io_resource, | |
357 | .io_offset = 0, | |
358 | .io_map_base = OCTEON_PCI_IOSPACE_BASE, | |
359 | }; | |
360 | ||
361 | ||
01a6221a | 362 | /* |
e8635b48 | 363 | * Low level initialize the Octeon PCI controller |
e8635b48 DD |
364 | */ |
365 | static void octeon_pci_initialize(void) | |
366 | { | |
367 | union cvmx_pci_cfg01 cfg01; | |
368 | union cvmx_npi_ctl_status ctl_status; | |
369 | union cvmx_pci_ctl_status_2 ctl_status_2; | |
370 | union cvmx_pci_cfg19 cfg19; | |
371 | union cvmx_pci_cfg16 cfg16; | |
372 | union cvmx_pci_cfg22 cfg22; | |
373 | union cvmx_pci_cfg56 cfg56; | |
374 | ||
375 | /* Reset the PCI Bus */ | |
376 | cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1); | |
377 | cvmx_read_csr(CVMX_CIU_SOFT_PRST); | |
378 | ||
379 | udelay(2000); /* Hold PCI reset for 2 ms */ | |
380 | ||
381 | ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */ | |
382 | ctl_status.s.max_word = 1; | |
383 | ctl_status.s.timer = 1; | |
384 | cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64); | |
385 | ||
386 | /* Deassert PCI reset and advertize PCX Host Mode Device Capability | |
387 | (64b) */ | |
388 | cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4); | |
389 | cvmx_read_csr(CVMX_CIU_SOFT_PRST); | |
390 | ||
391 | udelay(2000); /* Wait 2 ms after deasserting PCI reset */ | |
392 | ||
393 | ctl_status_2.u32 = 0; | |
394 | ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set | |
395 | before any PCI reads. */ | |
396 | ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */ | |
397 | ctl_status_2.s.bar2_enb = 1; | |
398 | ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ | |
399 | ctl_status_2.s.bar2_esx = 1; | |
400 | ctl_status_2.s.pmo_amod = 1; /* Round robin priority */ | |
401 | if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { | |
402 | /* BAR1 hole */ | |
403 | ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS; | |
404 | ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ | |
405 | ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ | |
406 | ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */ | |
70342287 RB |
407 | ctl_status_2.s.bb1 = 1; /* BAR1 is big */ |
408 | ctl_status_2.s.bb0 = 1; /* BAR0 is big */ | |
e8635b48 DD |
409 | } |
410 | ||
411 | octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32); | |
412 | udelay(2000); /* Wait 2 ms before doing PCI reads */ | |
413 | ||
414 | ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2); | |
415 | pr_notice("PCI Status: %s %s-bit\n", | |
416 | ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI", | |
417 | ctl_status_2.s.ap_64ad ? "64" : "32"); | |
418 | ||
419 | if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { | |
420 | union cvmx_pci_cnt_reg cnt_reg_start; | |
421 | union cvmx_pci_cnt_reg cnt_reg_end; | |
422 | unsigned long cycles, pci_clock; | |
423 | ||
424 | cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); | |
425 | cycles = read_c0_cvmcount(); | |
426 | udelay(1000); | |
427 | cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); | |
428 | cycles = read_c0_cvmcount() - cycles; | |
429 | pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) / | |
430 | (cycles / (mips_hpt_frequency / 1000000)); | |
431 | pr_notice("PCI Clock: %lu MHz\n", pci_clock); | |
432 | } | |
433 | ||
434 | /* | |
435 | * TDOMC must be set to one in PCI mode. TDOMC should be set to 4 | |
25985edc | 436 | * in PCI-X mode to allow four outstanding splits. Otherwise, |
e8635b48 DD |
437 | * should not change from its reset value. Don't write PCI_CFG19 |
438 | * in PCI mode (0x82000001 reset value), write it to 0x82000004 | |
439 | * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero. | |
440 | * MRBCM -> must be one. | |
441 | */ | |
442 | if (ctl_status_2.s.ap_pcix) { | |
443 | cfg19.u32 = 0; | |
444 | /* | |
445 | * Target Delayed/Split request outstanding maximum | |
446 | * count. [1..31] and 0=32. NOTE: If the user | |
447 | * programs these bits beyond the Designed Maximum | |
448 | * outstanding count, then the designed maximum table | |
70342287 | 449 | * depth will be used instead. No additional |
e8635b48 DD |
450 | * Deferred/Split transactions will be accepted if |
451 | * this outstanding maximum count is | |
452 | * reached. Furthermore, no additional deferred/split | |
453 | * transactions will be accepted if the I/O delay/ I/O | |
454 | * Split Request outstanding maximum is reached. | |
455 | */ | |
456 | cfg19.s.tdomc = 4; | |
457 | /* | |
458 | * Master Deferred Read Request Outstanding Max Count | |
70342287 | 459 | * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC |
e8635b48 DD |
460 | * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101 |
461 | * 5 2 110 6 3 111 7 3 For example, if these bits are | |
462 | * programmed to 100, the core can support 2 DAC | |
463 | * cycles, 4 SAC cycles or a combination of 1 DAC and | |
464 | * 2 SAC cycles. NOTE: For the PCI-X maximum | |
465 | * outstanding split transactions, refer to | |
466 | * CRE0[22:20]. | |
467 | */ | |
468 | cfg19.s.mdrrmc = 2; | |
469 | /* | |
470 | * Master Request (Memory Read) Byte Count/Byte Enable | |
471 | * select. 0 = Byte Enables valid. In PCI mode, a | |
472 | * burst transaction cannot be performed using Memory | |
473 | * Read command=4?h6. 1 = DWORD Byte Count valid | |
474 | * (default). In PCI Mode, the memory read byte | |
475 | * enables are automatically generated by the | |
476 | * core. Note: N3 Master Request transaction sizes are | |
477 | * always determined through the | |
478 | * am_attr[<35:32>|<7:0>] field. | |
479 | */ | |
480 | cfg19.s.mrbcm = 1; | |
481 | octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32); | |
482 | } | |
483 | ||
484 | ||
485 | cfg01.u32 = 0; | |
486 | cfg01.s.msae = 1; /* Memory Space Access Enable */ | |
487 | cfg01.s.me = 1; /* Master Enable */ | |
488 | cfg01.s.pee = 1; /* PERR# Enable */ | |
489 | cfg01.s.see = 1; /* System Error Enable */ | |
490 | cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */ | |
491 | ||
492 | octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); | |
493 | ||
494 | #ifdef USE_OCTEON_INTERNAL_ARBITER | |
495 | /* | |
496 | * When OCTEON is a PCI host, most systems will use OCTEON's | |
497 | * internal arbiter, so must enable it before any PCI/PCI-X | |
498 | * traffic can occur. | |
499 | */ | |
500 | { | |
501 | union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg; | |
502 | ||
503 | pci_int_arb_cfg.u64 = 0; | |
504 | pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */ | |
505 | cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64); | |
506 | } | |
01a6221a | 507 | #endif /* USE_OCTEON_INTERNAL_ARBITER */ |
e8635b48 DD |
508 | |
509 | /* | |
25985edc | 510 | * Preferably written to 1 to set MLTD. [RDSATI,TRTAE, |
e8635b48 DD |
511 | * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to |
512 | * 1..7. | |
513 | */ | |
514 | cfg16.u32 = 0; | |
515 | cfg16.s.mltd = 1; /* Master Latency Timer Disable */ | |
516 | octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32); | |
517 | ||
518 | /* | |
519 | * Should be written to 0x4ff00. MTTV -> must be zero. | |
520 | * FLUSH -> must be 1. MRV -> should be 0xFF. | |
521 | */ | |
522 | cfg22.u32 = 0; | |
523 | /* Master Retry Value [1..255] and 0=infinite */ | |
524 | cfg22.s.mrv = 0xff; | |
525 | /* | |
526 | * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper | |
527 | * N3K operation. | |
528 | */ | |
529 | cfg22.s.flush = 1; | |
530 | octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32); | |
531 | ||
532 | /* | |
533 | * MOST Indicates the maximum number of outstanding splits (in -1 | |
534 | * notation) when OCTEON is in PCI-X mode. PCI-X performance is | |
535 | * affected by the MOST selection. Should generally be written | |
536 | * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807, | |
537 | * depending on the desired MOST of 3, 2, 1, or 0, respectively. | |
538 | */ | |
539 | cfg56.u32 = 0; | |
540 | cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */ | |
541 | cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */ | |
542 | cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */ | |
543 | cfg56.s.roe = 1; /* Relaxed Ordering Enable */ | |
544 | cfg56.s.mmbc = 1; /* Maximum Memory Byte Count | |
545 | [0=512B,1=1024B,2=2048B,3=4096B] */ | |
546 | cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1 | |
547 | .. 7=32] */ | |
548 | ||
549 | octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32); | |
550 | ||
551 | /* | |
552 | * Affects PCI performance when OCTEON services reads to its | |
70342287 | 553 | * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are |
e8635b48 DD |
554 | * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and |
555 | * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700, | |
556 | * these values need to be changed so they won't possibly prefetch off | |
557 | * of the end of memory if PCI is DMAing a buffer at the end of | |
558 | * memory. Note that these values differ from their reset values. | |
559 | */ | |
560 | octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21); | |
561 | octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31); | |
562 | octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31); | |
563 | } | |
564 | ||
565 | ||
01a6221a | 566 | /* |
e8635b48 | 567 | * Initialize the Octeon PCI controller |
e8635b48 DD |
568 | */ |
569 | static int __init octeon_pci_setup(void) | |
570 | { | |
571 | union cvmx_npi_mem_access_subidx mem_access; | |
572 | int index; | |
573 | ||
574 | /* Only these chips have PCI */ | |
575 | if (octeon_has_feature(OCTEON_FEATURE_PCIE)) | |
576 | return 0; | |
577 | ||
578 | /* Point pcibios_map_irq() to the PCI version of it */ | |
579 | octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq; | |
580 | ||
581 | /* Only use the big bars on chips that support it */ | |
582 | if (OCTEON_IS_MODEL(OCTEON_CN31XX) || | |
583 | OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || | |
584 | OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) | |
585 | octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL; | |
586 | else | |
587 | octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; | |
588 | ||
589 | /* PCI I/O and PCI MEM values */ | |
590 | set_io_port_base(OCTEON_PCI_IOSPACE_BASE); | |
591 | ioport_resource.start = 0; | |
592 | ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; | |
593 | if (!octeon_is_pci_host()) { | |
594 | pr_notice("Not in host mode, PCI Controller not initialized\n"); | |
595 | return 0; | |
596 | } | |
597 | ||
598 | pr_notice("%s Octeon big bar support\n", | |
599 | (octeon_dma_bar_type == | |
600 | OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); | |
601 | ||
602 | octeon_pci_initialize(); | |
603 | ||
604 | mem_access.u64 = 0; | |
605 | mem_access.s.esr = 1; /* Endian-Swap on read. */ | |
606 | mem_access.s.esw = 1; /* Endian-Swap on write. */ | |
607 | mem_access.s.nsr = 0; /* No-Snoop on read. */ | |
608 | mem_access.s.nsw = 0; /* No-Snoop on write. */ | |
609 | mem_access.s.ror = 0; /* Relax Read on read. */ | |
610 | mem_access.s.row = 0; /* Relax Order on write. */ | |
611 | mem_access.s.ba = 0; /* PCI Address bits [63:36]. */ | |
612 | cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64); | |
613 | ||
614 | /* | |
615 | * Remap the Octeon BAR 2 above all 32 bit devices | |
616 | * (0x8000000000ul). This is done here so it is remapped | |
617 | * before the readl()'s below. We don't want BAR2 overlapping | |
618 | * with BAR0/BAR1 during these reads. | |
619 | */ | |
b93b2abc DD |
620 | octeon_npi_write32(CVMX_NPI_PCI_CFG08, |
621 | (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull)); | |
622 | octeon_npi_write32(CVMX_NPI_PCI_CFG09, | |
623 | (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32)); | |
e8635b48 DD |
624 | |
625 | if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { | |
626 | /* Remap the Octeon BAR 0 to 0-2GB */ | |
627 | octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0); | |
628 | octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); | |
629 | ||
630 | /* | |
631 | * Remap the Octeon BAR 1 to map 2GB-4GB (minus the | |
632 | * BAR 1 hole). | |
633 | */ | |
634 | octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30); | |
635 | octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); | |
636 | ||
b93b2abc DD |
637 | /* BAR1 movable mappings set for identity mapping */ |
638 | octeon_bar1_pci_phys = 0x80000000ull; | |
639 | for (index = 0; index < 32; index++) { | |
640 | union cvmx_pci_bar1_indexx bar1_index; | |
641 | ||
642 | bar1_index.u32 = 0; | |
643 | /* Address bits[35:22] sent to L2C */ | |
644 | bar1_index.s.addr_idx = | |
645 | (octeon_bar1_pci_phys >> 22) + index; | |
646 | /* Don't put PCI accesses in L2. */ | |
647 | bar1_index.s.ca = 1; | |
648 | /* Endian Swap Mode */ | |
649 | bar1_index.s.end_swp = 1; | |
650 | /* Set '1' when the selected address range is valid. */ | |
651 | bar1_index.s.addr_v = 1; | |
652 | octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), | |
653 | bar1_index.u32); | |
654 | } | |
655 | ||
e8635b48 DD |
656 | /* Devices go after BAR1 */ |
657 | octeon_pci_mem_resource.start = | |
658 | OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) - | |
659 | (OCTEON_PCI_BAR1_HOLE_SIZE << 20); | |
660 | octeon_pci_mem_resource.end = | |
661 | octeon_pci_mem_resource.start + (1ul << 30); | |
662 | } else { | |
663 | /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */ | |
664 | octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20); | |
665 | octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); | |
666 | ||
667 | /* Remap the Octeon BAR 1 to map 0-128MB */ | |
668 | octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0); | |
669 | octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); | |
670 | ||
b93b2abc DD |
671 | /* BAR1 movable regions contiguous to cover the swiotlb */ |
672 | octeon_bar1_pci_phys = | |
673 | virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1); | |
674 | ||
675 | for (index = 0; index < 32; index++) { | |
676 | union cvmx_pci_bar1_indexx bar1_index; | |
677 | ||
678 | bar1_index.u32 = 0; | |
679 | /* Address bits[35:22] sent to L2C */ | |
680 | bar1_index.s.addr_idx = | |
681 | (octeon_bar1_pci_phys >> 22) + index; | |
682 | /* Don't put PCI accesses in L2. */ | |
683 | bar1_index.s.ca = 1; | |
684 | /* Endian Swap Mode */ | |
685 | bar1_index.s.end_swp = 1; | |
686 | /* Set '1' when the selected address range is valid. */ | |
687 | bar1_index.s.addr_v = 1; | |
688 | octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), | |
689 | bar1_index.u32); | |
690 | } | |
691 | ||
e8635b48 DD |
692 | /* Devices go after BAR0 */ |
693 | octeon_pci_mem_resource.start = | |
694 | OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) + | |
695 | (4ul << 10); | |
696 | octeon_pci_mem_resource.end = | |
697 | octeon_pci_mem_resource.start + (1ul << 30); | |
698 | } | |
699 | ||
700 | register_pci_controller(&octeon_pci_controller); | |
701 | ||
702 | /* | |
703 | * Clear any errors that might be pending from before the bus | |
704 | * was setup properly. | |
705 | */ | |
706 | cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); | |
b93b2abc | 707 | |
e1ced097 DD |
708 | if (IS_ERR(platform_device_register_simple("octeon_pci_edac", |
709 | -1, NULL, 0))) | |
f65aad41 RB |
710 | pr_err("Registation of co_pci_edac failed!\n"); |
711 | ||
b93b2abc DD |
712 | octeon_pci_dma_init(); |
713 | ||
e8635b48 DD |
714 | return 0; |
715 | } | |
716 | ||
717 | arch_initcall(octeon_pci_setup); |