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12d14e0e GJ |
1 | /* |
2 | * Ralink RT3662/RT3883 SoC PCI support | |
3 | * | |
4 | * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> | |
5 | * | |
6 | * Parts of this file are based on Ralink's 2.6.21 BSP | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published | |
10 | * by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/types.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_irq.h> | |
22 | #include <linux/of_pci.h> | |
23 | #include <linux/platform_device.h> | |
24 | ||
25 | #include <asm/mach-ralink/rt3883.h> | |
26 | #include <asm/mach-ralink/ralink_regs.h> | |
27 | ||
28 | #define RT3883_MEMORY_BASE 0x00000000 | |
29 | #define RT3883_MEMORY_SIZE 0x02000000 | |
30 | ||
31 | #define RT3883_PCI_REG_PCICFG 0x00 | |
32 | #define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf | |
33 | #define RT3883_PCICFG_P2P_BR_DEVNUM_S 16 | |
34 | #define RT3883_PCICFG_PCIRST BIT(1) | |
35 | #define RT3883_PCI_REG_PCIRAW 0x04 | |
36 | #define RT3883_PCI_REG_PCIINT 0x08 | |
37 | #define RT3883_PCI_REG_PCIENA 0x0c | |
38 | ||
39 | #define RT3883_PCI_REG_CFGADDR 0x20 | |
40 | #define RT3883_PCI_REG_CFGDATA 0x24 | |
41 | #define RT3883_PCI_REG_MEMBASE 0x28 | |
42 | #define RT3883_PCI_REG_IOBASE 0x2c | |
43 | #define RT3883_PCI_REG_ARBCTL 0x80 | |
44 | ||
45 | #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000) | |
46 | #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10) | |
47 | #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18) | |
48 | #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30) | |
49 | #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34) | |
50 | #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38) | |
51 | #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50) | |
52 | ||
53 | #define RT3883_PCI_MODE_NONE 0 | |
54 | #define RT3883_PCI_MODE_PCI BIT(0) | |
55 | #define RT3883_PCI_MODE_PCIE BIT(1) | |
56 | #define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE) | |
57 | ||
58 | #define RT3883_PCI_IRQ_COUNT 32 | |
59 | ||
60 | #define RT3883_P2P_BR_DEVNUM 1 | |
61 | ||
62 | struct rt3883_pci_controller { | |
63 | void __iomem *base; | |
64 | spinlock_t lock; | |
65 | ||
66 | struct device_node *intc_of_node; | |
67 | struct irq_domain *irq_domain; | |
68 | ||
69 | struct pci_controller pci_controller; | |
70 | struct resource io_res; | |
71 | struct resource mem_res; | |
72 | ||
73 | bool pcie_ready; | |
74 | }; | |
75 | ||
76 | static inline struct rt3883_pci_controller * | |
77 | pci_bus_to_rt3883_controller(struct pci_bus *bus) | |
78 | { | |
79 | struct pci_controller *hose; | |
80 | ||
81 | hose = (struct pci_controller *) bus->sysdata; | |
82 | return container_of(hose, struct rt3883_pci_controller, pci_controller); | |
83 | } | |
84 | ||
85 | static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc, | |
86 | unsigned reg) | |
87 | { | |
88 | return ioread32(rpc->base + reg); | |
89 | } | |
90 | ||
91 | static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc, | |
92 | u32 val, unsigned reg) | |
93 | { | |
94 | iowrite32(val, rpc->base + reg); | |
95 | } | |
96 | ||
97 | static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot, | |
98 | unsigned int func, unsigned int where) | |
99 | { | |
100 | return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | | |
101 | 0x80000000; | |
102 | } | |
103 | ||
104 | static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc, | |
105 | unsigned bus, unsigned slot, | |
106 | unsigned func, unsigned reg) | |
107 | { | |
108 | unsigned long flags; | |
109 | u32 address; | |
110 | u32 ret; | |
111 | ||
112 | address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); | |
113 | ||
114 | spin_lock_irqsave(&rpc->lock, flags); | |
115 | rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); | |
116 | ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); | |
117 | spin_unlock_irqrestore(&rpc->lock, flags); | |
118 | ||
119 | return ret; | |
120 | } | |
121 | ||
122 | static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc, | |
123 | unsigned bus, unsigned slot, | |
124 | unsigned func, unsigned reg, u32 val) | |
125 | { | |
126 | unsigned long flags; | |
127 | u32 address; | |
128 | ||
129 | address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); | |
130 | ||
131 | spin_lock_irqsave(&rpc->lock, flags); | |
132 | rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); | |
133 | rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA); | |
134 | spin_unlock_irqrestore(&rpc->lock, flags); | |
135 | } | |
136 | ||
137 | static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc) | |
138 | { | |
139 | struct rt3883_pci_controller *rpc; | |
140 | u32 pending; | |
141 | ||
142 | rpc = irq_get_handler_data(irq); | |
143 | ||
144 | pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) & | |
145 | rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); | |
146 | ||
147 | if (!pending) { | |
148 | spurious_interrupt(); | |
149 | return; | |
150 | } | |
151 | ||
152 | while (pending) { | |
153 | unsigned bit = __ffs(pending); | |
154 | ||
155 | irq = irq_find_mapping(rpc->irq_domain, bit); | |
156 | generic_handle_irq(irq); | |
157 | ||
158 | pending &= ~BIT(bit); | |
159 | } | |
160 | } | |
161 | ||
162 | static void rt3883_pci_irq_unmask(struct irq_data *d) | |
163 | { | |
164 | struct rt3883_pci_controller *rpc; | |
165 | u32 t; | |
166 | ||
167 | rpc = irq_data_get_irq_chip_data(d); | |
168 | ||
169 | t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); | |
170 | rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA); | |
171 | /* flush write */ | |
172 | rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); | |
173 | } | |
174 | ||
175 | static void rt3883_pci_irq_mask(struct irq_data *d) | |
176 | { | |
177 | struct rt3883_pci_controller *rpc; | |
178 | u32 t; | |
179 | ||
180 | rpc = irq_data_get_irq_chip_data(d); | |
181 | ||
182 | t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); | |
183 | rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA); | |
184 | /* flush write */ | |
185 | rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); | |
186 | } | |
187 | ||
188 | static struct irq_chip rt3883_pci_irq_chip = { | |
189 | .name = "RT3883 PCI", | |
190 | .irq_mask = rt3883_pci_irq_mask, | |
191 | .irq_unmask = rt3883_pci_irq_unmask, | |
192 | .irq_mask_ack = rt3883_pci_irq_mask, | |
193 | }; | |
194 | ||
195 | static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq, | |
196 | irq_hw_number_t hw) | |
197 | { | |
198 | irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq); | |
199 | irq_set_chip_data(irq, d->host_data); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | static const struct irq_domain_ops rt3883_pci_irq_domain_ops = { | |
205 | .map = rt3883_pci_irq_map, | |
206 | .xlate = irq_domain_xlate_onecell, | |
207 | }; | |
208 | ||
209 | static int rt3883_pci_irq_init(struct device *dev, | |
210 | struct rt3883_pci_controller *rpc) | |
211 | { | |
212 | int irq; | |
213 | ||
214 | irq = irq_of_parse_and_map(rpc->intc_of_node, 0); | |
215 | if (irq == 0) { | |
216 | dev_err(dev, "%s has no IRQ", | |
217 | of_node_full_name(rpc->intc_of_node)); | |
218 | return -EINVAL; | |
219 | } | |
220 | ||
221 | /* disable all interrupts */ | |
222 | rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA); | |
223 | ||
224 | rpc->irq_domain = | |
225 | irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT, | |
226 | &rt3883_pci_irq_domain_ops, | |
227 | rpc); | |
228 | if (!rpc->irq_domain) { | |
229 | dev_err(dev, "unable to add IRQ domain\n"); | |
230 | return -ENODEV; | |
231 | } | |
232 | ||
233 | irq_set_handler_data(irq, rpc); | |
234 | irq_set_chained_handler(irq, rt3883_pci_irq_handler); | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
239 | static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn, | |
240 | int where, int size, u32 *val) | |
241 | { | |
242 | struct rt3883_pci_controller *rpc; | |
243 | unsigned long flags; | |
244 | u32 address; | |
245 | u32 data; | |
246 | ||
247 | rpc = pci_bus_to_rt3883_controller(bus); | |
248 | ||
249 | if (!rpc->pcie_ready && bus->number == 1) | |
250 | return PCIBIOS_DEVICE_NOT_FOUND; | |
251 | ||
252 | address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), | |
253 | PCI_FUNC(devfn), where); | |
254 | ||
255 | spin_lock_irqsave(&rpc->lock, flags); | |
256 | rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); | |
257 | data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); | |
258 | spin_unlock_irqrestore(&rpc->lock, flags); | |
259 | ||
260 | switch (size) { | |
261 | case 1: | |
262 | *val = (data >> ((where & 3) << 3)) & 0xff; | |
263 | break; | |
264 | case 2: | |
265 | *val = (data >> ((where & 3) << 3)) & 0xffff; | |
266 | break; | |
267 | case 4: | |
268 | *val = data; | |
269 | break; | |
270 | } | |
271 | ||
272 | return PCIBIOS_SUCCESSFUL; | |
273 | } | |
274 | ||
275 | static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn, | |
276 | int where, int size, u32 val) | |
277 | { | |
278 | struct rt3883_pci_controller *rpc; | |
279 | unsigned long flags; | |
280 | u32 address; | |
281 | u32 data; | |
282 | ||
283 | rpc = pci_bus_to_rt3883_controller(bus); | |
284 | ||
285 | if (!rpc->pcie_ready && bus->number == 1) | |
286 | return PCIBIOS_DEVICE_NOT_FOUND; | |
287 | ||
288 | address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), | |
289 | PCI_FUNC(devfn), where); | |
290 | ||
291 | spin_lock_irqsave(&rpc->lock, flags); | |
292 | rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); | |
293 | data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); | |
294 | ||
295 | switch (size) { | |
296 | case 1: | |
297 | data = (data & ~(0xff << ((where & 3) << 3))) | | |
298 | (val << ((where & 3) << 3)); | |
299 | break; | |
300 | case 2: | |
301 | data = (data & ~(0xffff << ((where & 3) << 3))) | | |
302 | (val << ((where & 3) << 3)); | |
303 | break; | |
304 | case 4: | |
305 | data = val; | |
306 | break; | |
307 | } | |
308 | ||
309 | rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA); | |
310 | spin_unlock_irqrestore(&rpc->lock, flags); | |
311 | ||
312 | return PCIBIOS_SUCCESSFUL; | |
313 | } | |
314 | ||
315 | static struct pci_ops rt3883_pci_ops = { | |
316 | .read = rt3883_pci_config_read, | |
317 | .write = rt3883_pci_config_write, | |
318 | }; | |
319 | ||
320 | static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode) | |
321 | { | |
322 | u32 syscfg1; | |
323 | u32 rstctrl; | |
324 | u32 clkcfg1; | |
325 | u32 t; | |
326 | ||
327 | rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); | |
328 | syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); | |
329 | clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); | |
330 | ||
331 | if (mode & RT3883_PCI_MODE_PCIE) { | |
332 | rstctrl |= RT3883_RSTCTRL_PCIE; | |
333 | rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); | |
334 | ||
335 | /* setup PCI PAD drive mode */ | |
336 | syscfg1 &= ~(0x30); | |
337 | syscfg1 |= (2 << 4); | |
338 | rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); | |
339 | ||
340 | t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
341 | t &= ~BIT(31); | |
342 | rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
343 | ||
344 | t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); | |
345 | t &= 0x80ffffff; | |
346 | rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); | |
347 | ||
348 | t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); | |
349 | t |= 0xa << 24; | |
350 | rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); | |
351 | ||
352 | t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
353 | t |= BIT(31); | |
354 | rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
355 | ||
356 | msleep(50); | |
357 | ||
358 | rstctrl &= ~RT3883_RSTCTRL_PCIE; | |
359 | rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); | |
360 | } | |
361 | ||
362 | syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE); | |
363 | ||
364 | clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN); | |
365 | ||
366 | if (mode & RT3883_PCI_MODE_PCI) { | |
367 | clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN; | |
368 | rstctrl &= ~RT3883_RSTCTRL_PCI; | |
369 | } | |
370 | ||
371 | if (mode & RT3883_PCI_MODE_PCIE) { | |
372 | clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN; | |
373 | rstctrl &= ~RT3883_RSTCTRL_PCIE; | |
374 | } | |
375 | ||
376 | rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); | |
377 | rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); | |
378 | rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1); | |
379 | ||
380 | msleep(500); | |
381 | ||
382 | /* | |
383 | * setup the device number of the P2P bridge | |
384 | * and de-assert the reset line | |
385 | */ | |
386 | t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S); | |
387 | rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG); | |
388 | ||
389 | /* flush write */ | |
390 | rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG); | |
391 | msleep(500); | |
392 | ||
393 | if (mode & RT3883_PCI_MODE_PCIE) { | |
394 | msleep(500); | |
395 | ||
396 | t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1)); | |
397 | ||
398 | rpc->pcie_ready = t & BIT(0); | |
399 | ||
400 | if (!rpc->pcie_ready) { | |
401 | /* reset the PCIe block */ | |
402 | t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); | |
403 | t |= RT3883_RSTCTRL_PCIE; | |
404 | rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); | |
405 | t &= ~RT3883_RSTCTRL_PCIE; | |
406 | rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); | |
407 | ||
408 | /* turn off PCIe clock */ | |
409 | t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); | |
410 | t &= ~RT3883_CLKCFG1_PCIE_CLK_EN; | |
411 | rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1); | |
412 | ||
413 | t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
414 | t &= ~0xf000c080; | |
415 | rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
416 | } | |
417 | } | |
418 | ||
419 | /* enable PCI arbiter */ | |
420 | rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL); | |
421 | } | |
422 | ||
423 | static int rt3883_pci_probe(struct platform_device *pdev) | |
424 | { | |
425 | struct rt3883_pci_controller *rpc; | |
426 | struct device *dev = &pdev->dev; | |
427 | struct device_node *np = dev->of_node; | |
428 | struct resource *res; | |
429 | struct device_node *child; | |
430 | u32 val; | |
431 | int err; | |
432 | int mode; | |
433 | ||
434 | rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); | |
435 | if (!rpc) | |
436 | return -ENOMEM; | |
437 | ||
438 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
439 | if (!res) | |
440 | return -EINVAL; | |
441 | ||
442 | rpc->base = devm_ioremap_resource(dev, res); | |
443 | if (IS_ERR(rpc->base)) | |
444 | return PTR_ERR(rpc->base); | |
445 | ||
446 | /* find the interrupt controller child node */ | |
447 | for_each_child_of_node(np, child) { | |
448 | if (of_get_property(child, "interrupt-controller", NULL) && | |
449 | of_node_get(child)) { | |
450 | rpc->intc_of_node = child; | |
451 | break; | |
452 | } | |
453 | } | |
454 | ||
455 | if (!rpc->intc_of_node) { | |
456 | dev_err(dev, "%s has no %s child node", | |
457 | of_node_full_name(rpc->intc_of_node), | |
458 | "interrupt controller"); | |
459 | return -EINVAL; | |
460 | } | |
461 | ||
462 | /* find the PCI host bridge child node */ | |
463 | for_each_child_of_node(np, child) { | |
464 | if (child->type && | |
465 | of_node_cmp(child->type, "pci") == 0 && | |
466 | of_node_get(child)) { | |
467 | rpc->pci_controller.of_node = child; | |
468 | break; | |
469 | } | |
470 | } | |
471 | ||
472 | if (!rpc->pci_controller.of_node) { | |
473 | dev_err(dev, "%s has no %s child node", | |
474 | of_node_full_name(rpc->intc_of_node), | |
475 | "PCI host bridge"); | |
476 | err = -EINVAL; | |
477 | goto err_put_intc_node; | |
478 | } | |
479 | ||
480 | mode = RT3883_PCI_MODE_NONE; | |
481 | for_each_available_child_of_node(rpc->pci_controller.of_node, child) { | |
482 | int devfn; | |
483 | ||
484 | if (!child->type || | |
485 | of_node_cmp(child->type, "pci") != 0) | |
486 | continue; | |
487 | ||
488 | devfn = of_pci_get_devfn(child); | |
489 | if (devfn < 0) | |
490 | continue; | |
491 | ||
492 | switch (PCI_SLOT(devfn)) { | |
493 | case 1: | |
494 | mode |= RT3883_PCI_MODE_PCIE; | |
495 | break; | |
496 | ||
497 | case 17: | |
498 | case 18: | |
499 | mode |= RT3883_PCI_MODE_PCI; | |
500 | break; | |
501 | } | |
502 | } | |
503 | ||
504 | if (mode == RT3883_PCI_MODE_NONE) { | |
505 | dev_err(dev, "unable to determine PCI mode\n"); | |
506 | err = -EINVAL; | |
507 | goto err_put_hb_node; | |
508 | } | |
509 | ||
510 | dev_info(dev, "mode:%s%s\n", | |
511 | (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "", | |
512 | (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : ""); | |
513 | ||
514 | rt3883_pci_preinit(rpc, mode); | |
515 | ||
516 | rpc->pci_controller.pci_ops = &rt3883_pci_ops; | |
517 | rpc->pci_controller.io_resource = &rpc->io_res; | |
518 | rpc->pci_controller.mem_resource = &rpc->mem_res; | |
519 | ||
520 | /* Load PCI I/O and memory resources from DT */ | |
521 | pci_load_of_ranges(&rpc->pci_controller, | |
522 | rpc->pci_controller.of_node); | |
523 | ||
524 | rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE); | |
525 | rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE); | |
526 | ||
527 | ioport_resource.start = rpc->io_res.start; | |
528 | ioport_resource.end = rpc->io_res.end; | |
529 | ||
530 | /* PCI */ | |
531 | rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0)); | |
532 | rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0)); | |
533 | rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0)); | |
534 | rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0)); | |
535 | rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0)); | |
536 | ||
537 | /* PCIe */ | |
538 | rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1)); | |
539 | rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1)); | |
540 | rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1)); | |
541 | rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1)); | |
542 | rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1)); | |
543 | ||
544 | err = rt3883_pci_irq_init(dev, rpc); | |
545 | if (err) | |
546 | goto err_put_hb_node; | |
547 | ||
548 | /* PCIe */ | |
549 | val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND); | |
550 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; | |
551 | rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val); | |
552 | ||
553 | /* PCI */ | |
554 | val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND); | |
555 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; | |
556 | rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val); | |
557 | ||
558 | if (mode == RT3883_PCI_MODE_PCIE) { | |
559 | rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0)); | |
560 | rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1)); | |
561 | ||
562 | rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, | |
563 | PCI_BASE_ADDRESS_0, | |
564 | RT3883_MEMORY_BASE); | |
565 | /* flush write */ | |
566 | rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, | |
567 | PCI_BASE_ADDRESS_0); | |
568 | } else { | |
569 | rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, | |
570 | PCI_IO_BASE, 0x00000101); | |
571 | } | |
572 | ||
573 | register_pci_controller(&rpc->pci_controller); | |
574 | ||
575 | return 0; | |
576 | ||
577 | err_put_hb_node: | |
578 | of_node_put(rpc->pci_controller.of_node); | |
579 | err_put_intc_node: | |
580 | of_node_put(rpc->intc_of_node); | |
581 | return err; | |
582 | } | |
583 | ||
584 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | |
585 | { | |
530210c7 | 586 | struct of_phandle_args dev_irq; |
12d14e0e GJ |
587 | int err; |
588 | int irq; | |
589 | ||
0c02c800 | 590 | err = of_irq_parse_pci(dev, &dev_irq); |
12d14e0e GJ |
591 | if (err) { |
592 | pr_err("pci %s: unable to get irq map, err=%d\n", | |
593 | pci_name((struct pci_dev *) dev), err); | |
594 | return 0; | |
595 | } | |
596 | ||
e6d30ab1 | 597 | irq = irq_create_of_mapping(&dev_irq); |
12d14e0e GJ |
598 | |
599 | if (irq == 0) | |
600 | pr_crit("pci %s: no irq found for pin %u\n", | |
601 | pci_name((struct pci_dev *) dev), pin); | |
602 | else | |
603 | pr_info("pci %s: using irq %d for pin %u\n", | |
604 | pci_name((struct pci_dev *) dev), irq, pin); | |
605 | ||
606 | return irq; | |
607 | } | |
608 | ||
609 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
610 | { | |
611 | return 0; | |
612 | } | |
613 | ||
614 | static const struct of_device_id rt3883_pci_ids[] = { | |
615 | { .compatible = "ralink,rt3883-pci" }, | |
616 | {}, | |
617 | }; | |
618 | MODULE_DEVICE_TABLE(of, rt3883_pci_ids); | |
619 | ||
620 | static struct platform_driver rt3883_pci_driver = { | |
621 | .probe = rt3883_pci_probe, | |
622 | .driver = { | |
623 | .name = "rt3883-pci", | |
624 | .owner = THIS_MODULE, | |
625 | .of_match_table = of_match_ptr(rt3883_pci_ids), | |
626 | }, | |
627 | }; | |
628 | ||
629 | static int __init rt3883_pci_init(void) | |
630 | { | |
631 | return platform_driver_register(&rt3883_pci_driver); | |
632 | } | |
633 | ||
634 | postcore_initcall(rt3883_pci_init); |