[mirror_ubuntu-bionic-kernel.git] / arch / mips / pci / pci.c

/*
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2011 Wind River Systems,
 *   written by Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/of_address.h>

#include <asm/cpu-info.h>

/*
 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
 * assignments.
 */

/*
 * The PCI controller list.
 */

static struct pci_controller *hose_head, **hose_tail = &hose_head;

unsigned long PCIBIOS_MIN_IO;
unsigned long PCIBIOS_MIN_MEM;

static int pci_initialized;

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
		       resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_controller *hose = dev->sysdata;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
			start = PCIBIOS_MIN_IO + hose->io_resource->start;

		/*
		 * Put everything into 0x00-0xff region modulo 0x400
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	} else if (res->flags & IORESOURCE_MEM) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	}

	return start;
}

static void pcibios_scanbus(struct pci_controller *hose)
{
	static int next_busno;
	static int need_domain_info;
	LIST_HEAD(resources);
	struct pci_bus *bus;

	if (!hose->iommu)
		PCI_DMA_BUS_IS_PHYS = 1;

	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
		next_busno = (*hose->get_busno)();

	pci_add_resource_offset(&resources,
				hose->mem_resource, hose->mem_offset);
	pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
	bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
				&resources);
	if (!bus)
		pci_free_resource_list(&resources);

	hose->bus = bus;

	need_domain_info = need_domain_info || hose->index;
	hose->need_domain_info = need_domain_info;
	if (bus) {
		next_busno = bus->busn_res.end + 1;
		/* Don't allow 8-bit bus number overflow inside the hose -
		   reserve some space for bridges. */
		if (next_busno > 224) {
			next_busno = 0;
			need_domain_info = 1;
		}

		if (!pci_has_flag(PCI_PROBE_ONLY)) {
			pci_bus_size_bridges(bus);
			pci_bus_assign_resources(bus);
		}
	}
}

#ifdef CONFIG_OF
void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
{
	struct of_pci_range range;
	struct of_pci_range_parser parser;

	pr_info("PCI host bridge %s ranges:\n", node->full_name);
	hose->of_node = node;

	if (of_pci_range_parser_init(&parser, node))
		return;

	for_each_of_pci_range(&parser, &range) {
		struct resource *res = NULL;

		switch (range.flags & IORESOURCE_TYPE_BITS) {
		case IORESOURCE_IO:
			pr_info("  IO 0x%016llx..0x%016llx\n",
				range.cpu_addr,
				range.cpu_addr + range.size - 1);
			hose->io_map_base =
				(unsigned long)ioremap(range.cpu_addr,
						       range.size);
			res = hose->io_resource;
			break;
		case IORESOURCE_MEM:
			pr_info(" MEM 0x%016llx..0x%016llx\n",
				range.cpu_addr,
				range.cpu_addr + range.size - 1);
			res = hose->mem_resource;
			break;
		}
		if (res != NULL)
			of_pci_range_to_resource(&range, node, res);
	}
}

struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
{
	struct pci_controller *hose = bus->sysdata;

	return of_node_get(hose->of_node);
}
#endif

static DEFINE_MUTEX(pci_scan_mutex);

void register_pci_controller(struct pci_controller *hose)
{
	struct resource *parent;

	parent = hose->mem_resource->parent;
	if (!parent)
		parent = &iomem_resource;

	if (request_resource(parent, hose->mem_resource) < 0)
		goto out;

	parent = hose->io_resource->parent;
	if (!parent)
		parent = &ioport_resource;

	if (request_resource(parent, hose->io_resource) < 0) {
		release_resource(hose->mem_resource);
		goto out;
	}

	*hose_tail = hose;
	hose_tail = &hose->next;

	/*
	 * Do not panic here but later - this might happen before console init.
	 */
	if (!hose->io_map_base) {
		printk(KERN_WARNING
		       "registering PCI controller with io_map_base unset\n");
	}

	/*
	 * Scan the bus if it is register after the PCI subsystem
	 * initialization.
	 */
	if (pci_initialized) {
		mutex_lock(&pci_scan_mutex);
		pcibios_scanbus(hose);
		mutex_unlock(&pci_scan_mutex);
	}

	return;

out:
	printk(KERN_WARNING
	       "Skipping PCI bus scan due to resource conflict\n");
}

static void __init pcibios_set_cache_line_size(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;
	unsigned int lsize;

	/*
	 * Set PCI cacheline size to that of the highest level in the
	 * cache hierarchy.
	 */
	lsize = c->dcache.linesz;
	lsize = c->scache.linesz ? : lsize;
	lsize = c->tcache.linesz ? : lsize;

	BUG_ON(!lsize);

	pci_dfl_cache_line_size = lsize >> 2;

	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
}

static int __init pcibios_init(void)
{
	struct pci_controller *hose;

	pcibios_set_cache_line_size();

	/* Scan all of the recorded PCI controllers.  */
	for (hose = hose_head; hose; hose = hose->next)
		pcibios_scanbus(hose);

	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);

	pci_initialized = 1;

	return 0;
}

subsys_initcall(pcibios_init);

static int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
		/* Only set up the requested stuff */
		if (!(mask & (1<<idx)))
			continue;

		r = &dev->resource[idx];
		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((idx == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;
		if (!r->start && r->end) {
			printk(KERN_ERR "PCI: Device %s not available "
			       "because of resource collisions\n",
			       pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (cmd != old_cmd) {
		printk("PCI: Enabling device %s (%04x -> %04x)\n",
		       pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

unsigned int pcibios_assign_all_busses(void)
{
	return 1;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;

	if ((err = pcibios_enable_resources(dev, mask)) < 0)
		return err;

	return pcibios_plat_dev_init(dev);
}

void pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_dev *dev = bus->self;

	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
		pci_read_bridge_bases(bus);
	}
}

EXPORT_SYMBOL(PCIBIOS_MIN_IO);
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	unsigned long prot;

	/*
	 * I/O space can be accessed via normal processor loads and stores on
	 * this platform but for now we elect not to do this and portable
	 * drivers should not do this anyway.
	 */
	if (mmap_state == pci_mmap_io)
		return -EINVAL;

	/*
	 * Ignore write-combine; for now only return uncached mappings.
	 */
	prot = pgprot_val(vma->vm_page_prot);
	prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
	vma->vm_page_prot = __pgprot(prot);

	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
		vma->vm_end - vma->vm_start, vma->vm_page_prot);
}

char * (*pcibios_plat_setup)(char *str) __initdata;

char *__init pcibios_setup(char *str)
{
	if (pcibios_plat_setup)
		return pcibios_plat_setup(str);
	return str;
}
Commit	Line	Data
1da177e4	1	/*
70342287 RB	2	* This program is free software; you can redistribute it and/or modify it
70342287 RB	3	* under the terms of the GNU General Public License as published by the
1da177e4 LT	4	* Free Software Foundation; either version 2 of the License, or (at your
	5	* option) any later version.
	6	*
c539ef7d RB	7	* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
	8	* Copyright (C) 2011 Wind River Systems,
	9	* written by Ralf Baechle (ralf@linux-mips.org)
1da177e4	10	*/
c539ef7d	11	#include <linux/bug.h>
1da177e4 LT	12	#include <linux/kernel.h>
	13	#include <linux/mm.h>
	14	#include <linux/bootmem.h>
cae39d13	15	#include <linux/export.h>
1da177e4 LT	16	#include <linux/init.h>
	17	#include <linux/types.h>
	18	#include <linux/pci.h>
a48cf37a	19	#include <linux/of_address.h>
1da177e4	20
c539ef7d RB	21	#include <asm/cpu-info.h>
c539ef7d RB	22
1da177e4	23	/*
29090606 BH	24	* If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
29090606 BH	25	* assignments.
1da177e4	26	*/
1da177e4	27
1da177e4 LT	28	/*
	29	* The PCI controller list.
	30	*/
	31
d58eaab5	32	static struct pci_controller hose_head, *hose_tail = &hose_head;
1da177e4	33
982f6ffe RB	34	unsigned long PCIBIOS_MIN_IO;
982f6ffe RB	35	unsigned long PCIBIOS_MIN_MEM;
1da177e4	36
540799e3 AJ	37	static int pci_initialized;
540799e3 AJ	38
1da177e4 LT	39	/*
	40	* We need to avoid collisions with `mirrored' VGA ports
	41	* and other strange ISA hardware, so we always want the
	42	* addresses to be allocated in the 0x000-0x0ff region
	43	* modulo 0x400.
	44	*
	45	* Why? Because some silly external IO cards only decode
	46	* the low 10 bits of the IO address. The 0x00-0xff region
	47	* is reserved for motherboard devices that decode all 16
	48	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	49	* but we want to try to avoid allocating at 0x2900-0x2bff
	50	* which might have be mirrored at 0x0100-0x03ff..
	51	*/
b26b2d49	52	resource_size_t
3b7a17fc	53	pcibios_align_resource(void data, const struct resource res,
e31dd6e4	54	resource_size_t size, resource_size_t align)
1da177e4 LT	55	{
	56	struct pci_dev *dev = data;
	57	struct pci_controller *hose = dev->sysdata;
e31dd6e4	58	resource_size_t start = res->start;
1da177e4 LT	59
	60	if (res->flags & IORESOURCE_IO) {
	61	/* Make sure we start at our min on all hoses */
	62	if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
	63	start = PCIBIOS_MIN_IO + hose->io_resource->start;
	64
	65	/*
	66	* Put everything into 0x00-0xff region modulo 0x400
	67	*/
	68	if (start & 0x300)
	69	start = (start + 0x3ff) & ~0x3ff;
	70	} else if (res->flags & IORESOURCE_MEM) {
	71	/* Make sure we start at our min on all hoses */
	72	if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
	73	start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	74	}
	75
b26b2d49	76	return start;
1da177e4 LT	77	}
1da177e4 LT	78
28eb0e46	79	static void pcibios_scanbus(struct pci_controller *hose)
540799e3 AJ	80	{
	81	static int next_busno;
	82	static int need_domain_info;
7c090e5b	83	LIST_HEAD(resources);
540799e3 AJ	84	struct pci_bus *bus;
	85
	86	if (!hose->iommu)
	87	PCI_DMA_BUS_IS_PHYS = 1;
	88
29090606	89	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
540799e3 AJ	90	next_busno = (*hose->get_busno)();
540799e3 AJ	91
96a6b9ad BH	92	pci_add_resource_offset(&resources,
	93	hose->mem_resource, hose->mem_offset);
	94	pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
7c090e5b BH	95	bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
	96	&resources);
	97	if (!bus)
	98	pci_free_resource_list(&resources);
	99
540799e3 AJ	100	hose->bus = bus;
	101
	102	need_domain_info = need_domain_info \|\| hose->index;
	103	hose->need_domain_info = need_domain_info;
	104	if (bus) {
b918c62e	105	next_busno = bus->busn_res.end + 1;
540799e3 AJ	106	/* Don't allow 8-bit bus number overflow inside the hose -
	107	reserve some space for bridges. */
	108	if (next_busno > 224) {
	109	next_busno = 0;
	110	need_domain_info = 1;
	111	}
	112
29090606	113	if (!pci_has_flag(PCI_PROBE_ONLY)) {
540799e3 AJ	114	pci_bus_size_bridges(bus);
540799e3 AJ	115	pci_bus_assign_resources(bus);
540799e3 AJ	116	}
	117	}
	118	}
	119
a48cf37a	120	#ifdef CONFIG_OF
28eb0e46	121	void pci_load_of_ranges(struct pci_controller hose, struct device_node node)
a48cf37a	122	{
cffe00c0 AM	123	struct of_pci_range range;
cffe00c0 AM	124	struct of_pci_range_parser parser;
a48cf37a JC	125
a48cf37a JC	126	pr_info("PCI host bridge %s ranges:\n", node->full_name);
a48cf37a JC	127	hose->of_node = node;
a48cf37a JC	128
cffe00c0 AM	129	if (of_pci_range_parser_init(&parser, node))
	130	return;
	131
	132	for_each_of_pci_range(&parser, &range) {
a48cf37a	133	struct resource *res = NULL;
cffe00c0 AM	134
	135	switch (range.flags & IORESOURCE_TYPE_BITS) {
	136	case IORESOURCE_IO:
a48cf37a	137	pr_info(" IO 0x%016llx..0x%016llx\n",
cffe00c0 AM	138	range.cpu_addr,
cffe00c0 AM	139	range.cpu_addr + range.size - 1);
a48cf37a	140	hose->io_map_base =
cffe00c0 AM	141	(unsigned long)ioremap(range.cpu_addr,
cffe00c0 AM	142	range.size);
a48cf37a	143	res = hose->io_resource;
a48cf37a	144	break;
cffe00c0	145	case IORESOURCE_MEM:
a48cf37a	146	pr_info(" MEM 0x%016llx..0x%016llx\n",
cffe00c0 AM	147	range.cpu_addr,
cffe00c0 AM	148	range.cpu_addr + range.size - 1);
a48cf37a	149	res = hose->mem_resource;
a48cf37a JC	150	break;
a48cf37a JC	151	}
cffe00c0 AM	152	if (res != NULL)
cffe00c0 AM	153	of_pci_range_to_resource(&range, node, res);
a48cf37a JC	154	}
a48cf37a JC	155	}
9a97cd43 GJ	156
	157	struct device_node pcibios_get_phb_of_node(struct pci_bus bus)
	158	{
	159	struct pci_controller *hose = bus->sysdata;
	160
	161	return of_node_get(hose->of_node);
	162	}
a48cf37a JC	163	#endif
a48cf37a JC	164
540799e3 AJ	165	static DEFINE_MUTEX(pci_scan_mutex);
540799e3 AJ	166
28eb0e46	167	void register_pci_controller(struct pci_controller *hose)
1da177e4	168	{
22283178 GJ	169	struct resource *parent;
	170
	171	parent = hose->mem_resource->parent;
	172	if (!parent)
	173	parent = &iomem_resource;
	174
	175	if (request_resource(parent, hose->mem_resource) < 0)
639702bd	176	goto out;
22283178 GJ	177
	178	parent = hose->io_resource->parent;
	179	if (!parent)
	180	parent = &ioport_resource;
	181
	182	if (request_resource(parent, hose->io_resource) < 0) {
639702bd TB	183	release_resource(hose->mem_resource);
	184	goto out;
	185	}
	186
1da177e4 LT	187	*hose_tail = hose;
1da177e4 LT	188	hose_tail = &hose->next;
140c1729 RB	189
140c1729 RB	190	/*
25985edc	191	* Do not panic here but later - this might happen before console init.
140c1729 RB	192	*/
	193	if (!hose->io_map_base) {
	194	printk(KERN_WARNING
	195	"registering PCI controller with io_map_base unset\n");
	196	}
540799e3 AJ	197
	198	/*
	199	* Scan the bus if it is register after the PCI subsystem
	200	* initialization.
	201	*/
	202	if (pci_initialized) {
	203	mutex_lock(&pci_scan_mutex);
	204	pcibios_scanbus(hose);
	205	mutex_unlock(&pci_scan_mutex);
	206	}
	207
639702bd TB	208	return;
	209
	210	out:
	211	printk(KERN_WARNING
	212	"Skipping PCI bus scan due to resource conflict\n");
1da177e4 LT	213	}
1da177e4 LT	214
c539ef7d RB	215	static void __init pcibios_set_cache_line_size(void)
	216	{
	217	struct cpuinfo_mips *c = &current_cpu_data;
	218	unsigned int lsize;
	219
	220	/*
	221	* Set PCI cacheline size to that of the highest level in the
	222	* cache hierarchy.
	223	*/
	224	lsize = c->dcache.linesz;
	225	lsize = c->scache.linesz ? : lsize;
	226	lsize = c->tcache.linesz ? : lsize;
	227
	228	BUG_ON(!lsize);
	229
	230	pci_dfl_cache_line_size = lsize >> 2;
	231
	232	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
	233	}
	234
1da177e4 LT	235	static int __init pcibios_init(void)
	236	{
	237	struct pci_controller *hose;
1da177e4	238
c539ef7d RB	239	pcibios_set_cache_line_size();
c539ef7d RB	240
1da177e4	241	/* Scan all of the recorded PCI controllers. */
540799e3 AJ	242	for (hose = hose_head; hose; hose = hose->next)
540799e3 AJ	243	pcibios_scanbus(hose);
1da177e4	244
67eed580	245	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
1da177e4	246
540799e3 AJ	247	pci_initialized = 1;
540799e3 AJ	248
1da177e4 LT	249	return 0;
	250	}
	251
	252	subsys_initcall(pcibios_init);
	253
	254	static int pcibios_enable_resources(struct pci_dev *dev, int mask)
	255	{
	256	u16 cmd, old_cmd;
	257	int idx;
	258	struct resource *r;
	259
	260	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	261	old_cmd = cmd;
e5de3b46	262	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
1da177e4 LT	263	/* Only set up the requested stuff */
	264	if (!(mask & (1<<idx)))
	265	continue;
	266
	267	r = &dev->resource[idx];
986c9485 RB	268	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	269	continue;
	270	if ((idx == PCI_ROM_RESOURCE) &&
	271	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	272	continue;
1da177e4	273	if (!r->start && r->end) {
40d7c1aa RB	274	printk(KERN_ERR "PCI: Device %s not available "
	275	"because of resource collisions\n",
	276	pci_name(dev));
1da177e4 LT	277	return -EINVAL;
	278	}
	279	if (r->flags & IORESOURCE_IO)
	280	cmd \|= PCI_COMMAND_IO;
	281	if (r->flags & IORESOURCE_MEM)
	282	cmd \|= PCI_COMMAND_MEMORY;
	283	}
1da177e4	284	if (cmd != old_cmd) {
40d7c1aa RB	285	printk("PCI: Enabling device %s (%04x -> %04x)\n",
40d7c1aa RB	286	pci_name(dev), old_cmd, cmd);
1da177e4 LT	287	pci_write_config_word(dev, PCI_COMMAND, cmd);
	288	}
	289	return 0;
	290	}
	291
1da177e4 LT	292	unsigned int pcibios_assign_all_busses(void)
1da177e4 LT	293	{
14be538c	294	return 1;
1da177e4 LT	295	}
	296
	297	int pcibios_enable_device(struct pci_dev *dev, int mask)
	298	{
	299	int err;
	300
	301	if ((err = pcibios_enable_resources(dev, mask)) < 0)
	302	return err;
	303
	304	return pcibios_plat_dev_init(dev);
	305	}
	306
28eb0e46	307	void pcibios_fixup_bus(struct pci_bus *bus)
1da177e4	308	{
1da177e4 LT	309	struct pci_dev *dev = bus->self;
1da177e4 LT	310
29090606	311	if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
7c090e5b	312	(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1da177e4	313	pci_read_bridge_bases(bus);
1da177e4 LT	314	}
	315	}
	316
1da177e4 LT	317	EXPORT_SYMBOL(PCIBIOS_MIN_IO);
1da177e4 LT	318	EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
1da177e4	319
98873f53 RB	320	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	321	enum pci_mmap_state mmap_state, int write_combine)
	322	{
	323	unsigned long prot;
	324
	325	/*
	326	* I/O space can be accessed via normal processor loads and stores on
	327	* this platform but for now we elect not to do this and portable
	328	* drivers should not do this anyway.
	329	*/
	330	if (mmap_state == pci_mmap_io)
	331	return -EINVAL;
	332
	333	/*
	334	* Ignore write-combine; for now only return uncached mappings.
	335	*/
	336	prot = pgprot_val(vma->vm_page_prot);
	337	prot = (prot & ~_CACHE_MASK) \| _CACHE_UNCACHED;
	338	vma->vm_page_prot = __pgprot(prot);
	339
	340	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	341	vma->vm_end - vma->vm_start, vma->vm_page_prot);
	342	}
	343
938ca516	344	char * (pcibios_plat_setup)(char str) __initdata;
47a5c976	345
938ca516	346	char __init pcibios_setup(char str)
1da177e4	347	{
47a5c976 AN	348	if (pcibios_plat_setup)
47a5c976 AN	349	return pcibios_plat_setup(str);
1da177e4 LT	350	return str;
1da177e4 LT	351	}