[mirror_ubuntu-zesty-kernel.git] / arch / mips / pci / pci.c

/*
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>

/*
 * Indicate whether we respect the PCI setup left by the firmware.
 *
 * Make this long-lived  so that we know when shutting down
 * whether we probed only or not.
 */
int pci_probe_only;

#define PCI_ASSIGN_ALL_BUSSES	1

unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;

/*
 * The PCI controller list.
 */

struct pci_controller *hose_head, **hose_tail = &hose_head;
struct pci_controller *pci_isa_hose;

unsigned long PCIBIOS_MIN_IO	= 0x0000;
unsigned long PCIBIOS_MIN_MEM	= 0;

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
void
pcibios_align_resource(void *data, struct resource *res,
		       resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_controller *hose = dev->sysdata;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
			start = PCIBIOS_MIN_IO + hose->io_resource->start;

		/*
		 * Put everything into 0x00-0xff region modulo 0x400
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	} else if (res->flags & IORESOURCE_MEM) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	}

	res->start = start;
}

void __devinit register_pci_controller(struct pci_controller *hose)
{
	if (request_resource(&iomem_resource, hose->mem_resource) < 0)
		goto out;
	if (request_resource(&ioport_resource, hose->io_resource) < 0) {
		release_resource(hose->mem_resource);
		goto out;
	}

	*hose_tail = hose;
	hose_tail = &hose->next;

	/*
	 * Do not panic here but later - this might hapen before console init.
	 */
	if (!hose->io_map_base) {
		printk(KERN_WARNING
		       "registering PCI controller with io_map_base unset\n");
	}
	return;

out:
	printk(KERN_WARNING
	       "Skipping PCI bus scan due to resource conflict\n");
}

/* Most MIPS systems have straight-forward swizzling needs.  */

static inline u8 bridge_swizzle(u8 pin, u8 slot)
{
	return (((pin - 1) + slot) % 4) + 1;
}

static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
{
	u8 pin = *pinp;

	while (dev->bus->parent) {
		pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
		/* Move up the chain of bridges. */
		dev = dev->bus->self;
        }
	*pinp = pin;

	/* The slot is the slot of the last bridge. */
	return PCI_SLOT(dev->devfn);
}

static int __init pcibios_init(void)
{
	struct pci_controller *hose;
	struct pci_bus *bus;
	int next_busno;
	int need_domain_info = 0;

	/* Scan all of the recorded PCI controllers.  */
	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {

		if (!hose->iommu)
			PCI_DMA_BUS_IS_PHYS = 1;

		if (hose->get_busno && pci_probe_only)
			next_busno = (*hose->get_busno)();

		bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
		hose->bus = bus;
		need_domain_info = need_domain_info || hose->index;
		hose->need_domain_info = need_domain_info;
		if (bus) {
			next_busno = bus->subordinate + 1;
			/* Don't allow 8-bit bus number overflow inside the hose -
			   reserve some space for bridges. */
			if (next_busno > 224) {
				next_busno = 0;
				need_domain_info = 1;
			}
		}
	}

	if (!pci_probe_only)
		pci_assign_unassigned_resources();
	pci_fixup_irqs(common_swizzle, pcibios_map_irq);

	return 0;
}

subsys_initcall(pcibios_init);

static int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
		/* Only set up the requested stuff */
		if (!(mask & (1<<idx)))
			continue;

		r = &dev->resource[idx];
		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((idx == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;
		if (!r->start && r->end) {
			printk(KERN_ERR "PCI: Device %s not available "
			       "because of resource collisions\n",
			       pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (cmd != old_cmd) {
		printk("PCI: Enabling device %s (%04x -> %04x)\n",
		       pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

/*
 *  If we set up a device for bus mastering, we need to check the latency
 *  timer as certain crappy BIOSes forget to set it properly.
 */
unsigned int pcibios_max_latency = 255;

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
	       pci_name(dev), lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}

unsigned int pcibios_assign_all_busses(void)
{
	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;

	if ((err = pcibios_enable_resources(dev, mask)) < 0)
		return err;

	return pcibios_plat_dev_init(dev);
}

static void pcibios_fixup_device_resources(struct pci_dev *dev,
	struct pci_bus *bus)
{
	/* Update device resources.  */
	struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
	unsigned long offset = 0;
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!dev->resource[i].start)
			continue;
		if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
			continue;
		if (dev->resource[i].flags & IORESOURCE_IO)
			offset = hose->io_offset;
		else if (dev->resource[i].flags & IORESOURCE_MEM)
			offset = hose->mem_offset;

		dev->resource[i].start += offset;
		dev->resource[i].end += offset;
	}
}

void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
	/* Propagate hose info into the subordinate devices.  */

	struct pci_controller *hose = bus->sysdata;
	struct list_head *ln;
	struct pci_dev *dev = bus->self;

	if (!dev) {
		bus->resource[0] = hose->io_resource;
		bus->resource[1] = hose->mem_resource;
	} else if (pci_probe_only &&
		   (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
		pci_read_bridge_bases(bus);
		pcibios_fixup_device_resources(dev, bus);
	}

	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
		dev = pci_dev_b(ln);

		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
			pcibios_fixup_device_resources(dev, bus);
	}
}

void __init
pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
			 struct resource *res)
{
	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
	unsigned long offset = 0;

	if (res->flags & IORESOURCE_IO)
		offset = hose->io_offset;
	else if (res->flags & IORESOURCE_MEM)
		offset = hose->mem_offset;

	region->start = res->start - offset;
	region->end = res->end - offset;
}

void __devinit
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
			struct pci_bus_region *region)
{
	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
	unsigned long offset = 0;

	if (res->flags & IORESOURCE_IO)
		offset = hose->io_offset;
	else if (res->flags & IORESOURCE_MEM)
		offset = hose->mem_offset;

	res->start = region->start + offset;
	res->end = region->end + offset;
}

#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_resource_to_bus);
EXPORT_SYMBOL(pcibios_bus_to_resource);
EXPORT_SYMBOL(PCIBIOS_MIN_IO);
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
#endif

char *pcibios_setup(char *str)
{
	return str;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License as published by the
	4	* Free Software Foundation; either version 2 of the License, or (at your
	5	* option) any later version.
	6	*
	7	* Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
	8	*/
1da177e4 LT	9	#include <linux/kernel.h>
	10	#include <linux/mm.h>
	11	#include <linux/bootmem.h>
	12	#include <linux/init.h>
	13	#include <linux/types.h>
	14	#include <linux/pci.h>
	15
	16	/*
	17	* Indicate whether we respect the PCI setup left by the firmware.
	18	*
	19	* Make this long-lived so that we know when shutting down
	20	* whether we probed only or not.
	21	*/
	22	int pci_probe_only;
	23
	24	#define PCI_ASSIGN_ALL_BUSSES 1
	25
	26	unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
	27
	28	/*
	29	* The PCI controller list.
	30	*/
	31
	32	struct pci_controller hose_head, *hose_tail = &hose_head;
	33	struct pci_controller *pci_isa_hose;
	34
	35	unsigned long PCIBIOS_MIN_IO = 0x0000;
	36	unsigned long PCIBIOS_MIN_MEM = 0;
	37
	38	/*
	39	* We need to avoid collisions with `mirrored' VGA ports
	40	* and other strange ISA hardware, so we always want the
	41	* addresses to be allocated in the 0x000-0x0ff region
	42	* modulo 0x400.
	43	*
	44	* Why? Because some silly external IO cards only decode
	45	* the low 10 bits of the IO address. The 0x00-0xff region
	46	* is reserved for motherboard devices that decode all 16
	47	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	48	* but we want to try to avoid allocating at 0x2900-0x2bff
	49	* which might have be mirrored at 0x0100-0x03ff..
	50	*/
	51	void
	52	pcibios_align_resource(void data, struct resource res,
e31dd6e4	53	resource_size_t size, resource_size_t align)
1da177e4 LT	54	{
	55	struct pci_dev *dev = data;
	56	struct pci_controller *hose = dev->sysdata;
e31dd6e4	57	resource_size_t start = res->start;
1da177e4 LT	58
	59	if (res->flags & IORESOURCE_IO) {
	60	/* Make sure we start at our min on all hoses */
	61	if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
	62	start = PCIBIOS_MIN_IO + hose->io_resource->start;
	63
	64	/*
	65	* Put everything into 0x00-0xff region modulo 0x400
	66	*/
	67	if (start & 0x300)
	68	start = (start + 0x3ff) & ~0x3ff;
	69	} else if (res->flags & IORESOURCE_MEM) {
	70	/* Make sure we start at our min on all hoses */
	71	if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
	72	start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	73	}
	74
	75	res->start = start;
	76	}
	77
606bf782	78	void __devinit register_pci_controller(struct pci_controller *hose)
1da177e4	79	{
639702bd TB	80	if (request_resource(&iomem_resource, hose->mem_resource) < 0)
	81	goto out;
	82	if (request_resource(&ioport_resource, hose->io_resource) < 0) {
	83	release_resource(hose->mem_resource);
	84	goto out;
	85	}
	86
1da177e4 LT	87	*hose_tail = hose;
1da177e4 LT	88	hose_tail = &hose->next;
140c1729 RB	89
	90	/*
	91	* Do not panic here but later - this might hapen before console init.
	92	*/
	93	if (!hose->io_map_base) {
	94	printk(KERN_WARNING
	95	"registering PCI controller with io_map_base unset\n");
	96	}
639702bd TB	97	return;
	98
	99	out:
	100	printk(KERN_WARNING
	101	"Skipping PCI bus scan due to resource conflict\n");
1da177e4 LT	102	}
	103
	104	/* Most MIPS systems have straight-forward swizzling needs. */
	105
	106	static inline u8 bridge_swizzle(u8 pin, u8 slot)
	107	{
	108	return (((pin - 1) + slot) % 4) + 1;
	109	}
	110
	111	static u8 __init common_swizzle(struct pci_dev dev, u8 pinp)
	112	{
	113	u8 pin = *pinp;
	114
	115	while (dev->bus->parent) {
	116	pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
	117	/* Move up the chain of bridges. */
	118	dev = dev->bus->self;
	119	}
	120	*pinp = pin;
	121
	122	/* The slot is the slot of the last bridge. */
	123	return PCI_SLOT(dev->devfn);
	124	}
	125
	126	static int __init pcibios_init(void)
	127	{
	128	struct pci_controller *hose;
	129	struct pci_bus *bus;
	130	int next_busno;
	131	int need_domain_info = 0;
	132
	133	/* Scan all of the recorded PCI controllers. */
	134	for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
	135
1da177e4 LT	136	if (!hose->iommu)
	137	PCI_DMA_BUS_IS_PHYS = 1;
	138
8a1417de AI	139	if (hose->get_busno && pci_probe_only)
	140	next_busno = (*hose->get_busno)();
	141
1da177e4 LT	142	bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
1da177e4 LT	143	hose->bus = bus;
d4ef9dd3	144	need_domain_info = need_domain_info \|\| hose->index;
1da177e4	145	hose->need_domain_info = need_domain_info;
8a1417de AI	146	if (bus) {
	147	next_busno = bus->subordinate + 1;
	148	/* Don't allow 8-bit bus number overflow inside the hose -
	149	reserve some space for bridges. */
	150	if (next_busno > 224) {
	151	next_busno = 0;
	152	need_domain_info = 1;
	153	}
1da177e4	154	}
1da177e4 LT	155	}
	156
	157	if (!pci_probe_only)
	158	pci_assign_unassigned_resources();
	159	pci_fixup_irqs(common_swizzle, pcibios_map_irq);
	160
	161	return 0;
	162	}
	163
	164	subsys_initcall(pcibios_init);
	165
	166	static int pcibios_enable_resources(struct pci_dev *dev, int mask)
	167	{
	168	u16 cmd, old_cmd;
	169	int idx;
	170	struct resource *r;
	171
	172	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	173	old_cmd = cmd;
e5de3b46	174	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
1da177e4 LT	175	/* Only set up the requested stuff */
	176	if (!(mask & (1<<idx)))
	177	continue;
	178
	179	r = &dev->resource[idx];
986c9485 RB	180	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	181	continue;
	182	if ((idx == PCI_ROM_RESOURCE) &&
	183	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	184	continue;
1da177e4	185	if (!r->start && r->end) {
40d7c1aa RB	186	printk(KERN_ERR "PCI: Device %s not available "
	187	"because of resource collisions\n",
	188	pci_name(dev));
1da177e4 LT	189	return -EINVAL;
	190	}
	191	if (r->flags & IORESOURCE_IO)
	192	cmd \|= PCI_COMMAND_IO;
	193	if (r->flags & IORESOURCE_MEM)
	194	cmd \|= PCI_COMMAND_MEMORY;
	195	}
1da177e4	196	if (cmd != old_cmd) {
40d7c1aa RB	197	printk("PCI: Enabling device %s (%04x -> %04x)\n",
40d7c1aa RB	198	pci_name(dev), old_cmd, cmd);
1da177e4 LT	199	pci_write_config_word(dev, PCI_COMMAND, cmd);
	200	}
	201	return 0;
	202	}
	203
	204	/*
	205	* If we set up a device for bus mastering, we need to check the latency
	206	* timer as certain crappy BIOSes forget to set it properly.
	207	*/
	208	unsigned int pcibios_max_latency = 255;
	209
	210	void pcibios_set_master(struct pci_dev *dev)
	211	{
	212	u8 lat;
	213	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	214	if (lat < 16)
	215	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	216	else if (lat > pcibios_max_latency)
	217	lat = pcibios_max_latency;
	218	else
	219	return;
	220	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
	221	pci_name(dev), lat);
	222	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
	223	}
	224
	225	unsigned int pcibios_assign_all_busses(void)
	226	{
	227	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
	228	}
	229
	230	int pcibios_enable_device(struct pci_dev *dev, int mask)
	231	{
	232	int err;
	233
	234	if ((err = pcibios_enable_resources(dev, mask)) < 0)
	235	return err;
	236
	237	return pcibios_plat_dev_init(dev);
	238	}
	239
c4aa2563	240	static void pcibios_fixup_device_resources(struct pci_dev *dev,
1da177e4 LT	241	struct pci_bus *bus)
	242	{
	243	/* Update device resources. */
	244	struct pci_controller hose = (struct pci_controller )bus->sysdata;
	245	unsigned long offset = 0;
	246	int i;
	247
	248	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	249	if (!dev->resource[i].start)
	250	continue;
d20e47e1 RB	251	if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
d20e47e1 RB	252	continue;
1da177e4 LT	253	if (dev->resource[i].flags & IORESOURCE_IO)
	254	offset = hose->io_offset;
	255	else if (dev->resource[i].flags & IORESOURCE_MEM)
	256	offset = hose->mem_offset;
	257
	258	dev->resource[i].start += offset;
	259	dev->resource[i].end += offset;
	260	}
	261	}
	262
234fcd14	263	void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1da177e4 LT	264	{
	265	/* Propagate hose info into the subordinate devices. */
	266
	267	struct pci_controller *hose = bus->sysdata;
	268	struct list_head *ln;
	269	struct pci_dev *dev = bus->self;
	270
	271	if (!dev) {
	272	bus->resource[0] = hose->io_resource;
	273	bus->resource[1] = hose->mem_resource;
	274	} else if (pci_probe_only &&
	275	(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
	276	pci_read_bridge_bases(bus);
	277	pcibios_fixup_device_resources(dev, bus);
42a3b4f2	278	}
1da177e4 LT	279
1da177e4 LT	280	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
8ed07a1c	281	dev = pci_dev_b(ln);
1da177e4 LT	282
	283	if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
	284	pcibios_fixup_device_resources(dev, bus);
	285	}
	286	}
	287
	288	void __init
	289	pcibios_update_irq(struct pci_dev *dev, int irq)
	290	{
	291	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	292	}
	293
c4aa2563	294	void pcibios_resource_to_bus(struct pci_dev dev, struct pci_bus_region region,
1da177e4 LT	295	struct resource *res)
	296	{
	297	struct pci_controller hose = (struct pci_controller )dev->sysdata;
	298	unsigned long offset = 0;
	299
	300	if (res->flags & IORESOURCE_IO)
	301	offset = hose->io_offset;
	302	else if (res->flags & IORESOURCE_MEM)
	303	offset = hose->mem_offset;
	304
	305	region->start = res->start - offset;
	306	region->end = res->end - offset;
	307	}
	308
e63ea56f YY	309	void __devinit
	310	pcibios_bus_to_resource(struct pci_dev dev, struct resource res,
	311	struct pci_bus_region *region)
	312	{
	313	struct pci_controller hose = (struct pci_controller )dev->sysdata;
	314	unsigned long offset = 0;
	315
	316	if (res->flags & IORESOURCE_IO)
	317	offset = hose->io_offset;
	318	else if (res->flags & IORESOURCE_MEM)
	319	offset = hose->mem_offset;
	320
	321	res->start = region->start + offset;
	322	res->end = region->end + offset;
	323	}
	324
1da177e4 LT	325	#ifdef CONFIG_HOTPLUG
1da177e4 LT	326	EXPORT_SYMBOL(pcibios_resource_to_bus);
e63ea56f	327	EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 LT	328	EXPORT_SYMBOL(PCIBIOS_MIN_IO);
	329	EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
	330	#endif
	331
	332	char pcibios_setup(char str)
	333	{
	334	return str;
	335	}