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[mirror_ubuntu-eoan-kernel.git] / arch / mips / pci / pci.c
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2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 2/*
1da177e4 3 *
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4 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
5 * Copyright (C) 2011 Wind River Systems,
6 * written by Ralf Baechle (ralf@linux-mips.org)
1da177e4 7 */
c539ef7d 8#include <linux/bug.h>
1da177e4
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9#include <linux/kernel.h>
10#include <linux/mm.h>
57c8a661 11#include <linux/memblock.h>
cae39d13 12#include <linux/export.h>
1da177e4
LT
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/pci.h>
a48cf37a 16#include <linux/of_address.h>
1da177e4 17
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18#include <asm/cpu-info.h>
19
982f6ffe 20unsigned long PCIBIOS_MIN_IO;
f8091a88 21EXPORT_SYMBOL(PCIBIOS_MIN_IO);
639702bd 22
f8091a88
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23unsigned long PCIBIOS_MIN_MEM;
24EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
1da177e4 25
f474ba9d 26static int __init pcibios_set_cache_line_size(void)
c539ef7d 27{
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28 unsigned int lsize;
29
30 /*
31 * Set PCI cacheline size to that of the highest level in the
32 * cache hierarchy.
33 */
73530266
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34 lsize = cpu_dcache_line_size();
35 lsize = cpu_scache_line_size() ? : lsize;
36 lsize = cpu_tcache_line_size() ? : lsize;
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37
38 BUG_ON(!lsize);
39
40 pci_dfl_cache_line_size = lsize >> 2;
41
42 pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
f474ba9d 43 return 0;
c539ef7d 44}
f474ba9d 45arch_initcall(pcibios_set_cache_line_size);
c539ef7d 46
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47void pci_resource_to_user(const struct pci_dev *dev, int bar,
48 const struct resource *rsrc, resource_size_t *start,
49 resource_size_t *end)
50{
51 phys_addr_t size = resource_size(rsrc);
52
53 *start = fixup_bigphys_addr(rsrc->start, size);
38c0a74f 54 *end = rsrc->start + size - 1;
8221a013 55}