[mirror_ubuntu-eoan-kernel.git] / arch / mips / pmc-sierra / msp71xx / msp_irq.c

/*
 * IRQ vector handles
 *
 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <linux/time.h>

#include <asm/irq_cpu.h>

#include <msp_int.h>

/* SLP bases systems */
extern void msp_slp_irq_init(void);
extern void msp_slp_irq_dispatch(void);

/* CIC based systems */
extern void msp_cic_irq_init(void);
extern void msp_cic_irq_dispatch(void);

/* VSMP support init */
extern void msp_vsmp_int_init(void);

/* vectored interrupt implementation */

/* SW0/1 interrupts are used for SMP/SMTC */
static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); }
static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); }
static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); }
static inline void usb_int_dispatch(void)  { do_IRQ(MSP_INT_USB);  }
static inline void sec_int_dispatch(void)  { do_IRQ(MSP_INT_SEC);  }

/*
 * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
 * hierarchical system.	 The first level are the direct MIPS interrupts
 * and are assigned the interrupt range 0-7.  The second level is the SLM
 * interrupt controller and is assigned the range 8-39.	 The third level
 * comprises the Peripherial block, the PCI block, the PCI MSI block and
 * the SLP.  The PCI interrupts and the SLP errors are handled by the
 * relevant subsystems so the core interrupt code needs only concern
 * itself with the Peripheral block.  These are assigned interrupts in
 * the range 40-71.
 */

asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
	u32 pending;

	pending = read_c0_status() & read_c0_cause();

	/*
	 * jump to the correct interrupt routine
	 * These are arranged in priority order and the timer
	 * comes first!
	 */

#ifdef CONFIG_IRQ_MSP_CIC	/* break out the CIC stuff for now */
	if (pending & C_IRQ4)	/* do the peripherals first, that's the timer */
		msp_cic_irq_dispatch();

	else if (pending & C_IRQ0)
		do_IRQ(MSP_INT_MAC0);

	else if (pending & C_IRQ1)
		do_IRQ(MSP_INT_MAC1);

	else if (pending & C_IRQ2)
		do_IRQ(MSP_INT_USB);

	else if (pending & C_IRQ3)
		do_IRQ(MSP_INT_SAR);

	else if (pending & C_IRQ5)
		do_IRQ(MSP_INT_SEC);

#else
	if (pending & C_IRQ5)
		do_IRQ(MSP_INT_TIMER);

	else if (pending & C_IRQ0)
		do_IRQ(MSP_INT_MAC0);

	else if (pending & C_IRQ1)
		do_IRQ(MSP_INT_MAC1);

	else if (pending & C_IRQ3)
		do_IRQ(MSP_INT_VE);

	else if (pending & C_IRQ4)
		msp_slp_irq_dispatch();
#endif

	else if (pending & C_SW0)	/* do software after hardware */
		do_IRQ(MSP_INT_SW0);

	else if (pending & C_SW1)
		do_IRQ(MSP_INT_SW1);
}

static struct irqaction cic_cascade_msp = {
	.handler = no_action,
	.name	 = "MSP CIC cascade",
	.flags	 = IRQF_NO_THREAD,
};

static struct irqaction per_cascade_msp = {
	.handler = no_action,
	.name	 = "MSP PER cascade",
	.flags	 = IRQF_NO_THREAD,
};

void __init arch_init_irq(void)
{
	/* assume we'll be using vectored interrupt mode except in UP mode*/
#ifdef CONFIG_MIPS_MT
	BUG_ON(!cpu_has_vint);
#endif
	/* initialize the 1st-level CPU based interrupt controller */
	mips_cpu_irq_init();

#ifdef CONFIG_IRQ_MSP_CIC
	msp_cic_irq_init();
#ifdef CONFIG_MIPS_MT
	set_vi_handler(MSP_INT_CIC, msp_cic_irq_dispatch);
	set_vi_handler(MSP_INT_MAC0, mac0_int_dispatch);
	set_vi_handler(MSP_INT_MAC1, mac1_int_dispatch);
	set_vi_handler(MSP_INT_SAR, mac2_int_dispatch);
	set_vi_handler(MSP_INT_USB, usb_int_dispatch);
	set_vi_handler(MSP_INT_SEC, sec_int_dispatch);
#ifdef CONFIG_MIPS_MT_SMP
	msp_vsmp_int_init();
#elif defined CONFIG_MIPS_MT_SMTC
	/*Set hwmask for all platform devices */
	irq_hwmask[MSP_INT_MAC0] = C_IRQ0;
	irq_hwmask[MSP_INT_MAC1] = C_IRQ1;
	irq_hwmask[MSP_INT_USB] = C_IRQ2;
	irq_hwmask[MSP_INT_SAR] = C_IRQ3;
	irq_hwmask[MSP_INT_SEC] = C_IRQ5;

#endif	/* CONFIG_MIPS_MT_SMP */
#endif	/* CONFIG_MIPS_MT */
	/* setup the cascaded interrupts */
	setup_irq(MSP_INT_CIC, &cic_cascade_msp);
	setup_irq(MSP_INT_PER, &per_cascade_msp);

#else
	/* setup the 2nd-level SLP register based interrupt controller */
	/* VSMP /SMTC support support is not enabled for SLP */
	msp_slp_irq_init();

	/* setup the cascaded SLP/PER interrupts */
	setup_irq(MSP_INT_SLP, &cic_cascade_msp);
	setup_irq(MSP_INT_PER, &per_cascade_msp);
#endif
}
Commit	Line	Data
35832e26 MSJ	1	/*
	2	* IRQ vector handles
	3	*
	4	* Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/irq.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/ptrace.h>
	16	#include <linux/time.h>
	17
	18	#include <asm/irq_cpu.h>
	19
	20	#include <msp_int.h>
	21
35832e26 MSJ	22	/* SLP bases systems */
	23	extern void msp_slp_irq_init(void);
	24	extern void msp_slp_irq_dispatch(void);
	25
	26	/* CIC based systems */
	27	extern void msp_cic_irq_init(void);
	28	extern void msp_cic_irq_dispatch(void);
	29
92592c9c A	30	/* VSMP support init */
	31	extern void msp_vsmp_int_init(void);
	32
	33	/* vectored interrupt implementation */
	34
	35	/* SW0/1 interrupts are used for SMP/SMTC */
	36	static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); }
	37	static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); }
	38	static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); }
	39	static inline void usb_int_dispatch(void) { do_IRQ(MSP_INT_USB); }
	40	static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC); }
	41
35832e26 MSJ	42	/*
35832e26 MSJ	43	* The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
70342287	44	* hierarchical system. The first level are the direct MIPS interrupts
35832e26	45	* and are assigned the interrupt range 0-7. The second level is the SLM
70342287	46	* interrupt controller and is assigned the range 8-39. The third level
35832e26 MSJ	47	* comprises the Peripherial block, the PCI block, the PCI MSI block and
	48	* the SLP. The PCI interrupts and the SLP errors are handled by the
	49	* relevant subsystems so the core interrupt code needs only concern
	50	* itself with the Peripheral block. These are assigned interrupts in
	51	* the range 40-71.
	52	*/
	53
	54	asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
	55	{
	56	u32 pending;
	57
	58	pending = read_c0_status() & read_c0_cause();
	59
	60	/*
	61	* jump to the correct interrupt routine
	62	* These are arranged in priority order and the timer
	63	* comes first!
	64	*/
	65
	66	#ifdef CONFIG_IRQ_MSP_CIC /* break out the CIC stuff for now */
	67	if (pending & C_IRQ4) /* do the peripherals first, that's the timer */
	68	msp_cic_irq_dispatch();
	69
	70	else if (pending & C_IRQ0)
	71	do_IRQ(MSP_INT_MAC0);
	72
	73	else if (pending & C_IRQ1)
	74	do_IRQ(MSP_INT_MAC1);
	75
	76	else if (pending & C_IRQ2)
	77	do_IRQ(MSP_INT_USB);
	78
	79	else if (pending & C_IRQ3)
	80	do_IRQ(MSP_INT_SAR);
	81
	82	else if (pending & C_IRQ5)
	83	do_IRQ(MSP_INT_SEC);
	84
	85	#else
	86	if (pending & C_IRQ5)
	87	do_IRQ(MSP_INT_TIMER);
	88
	89	else if (pending & C_IRQ0)
	90	do_IRQ(MSP_INT_MAC0);
	91
	92	else if (pending & C_IRQ1)
	93	do_IRQ(MSP_INT_MAC1);
	94
	95	else if (pending & C_IRQ3)
	96	do_IRQ(MSP_INT_VE);
	97
	98	else if (pending & C_IRQ4)
	99	msp_slp_irq_dispatch();
	100	#endif
	101
	102	else if (pending & C_SW0) /* do software after hardware */
	103	do_IRQ(MSP_INT_SW0);
	104
	105	else if (pending & C_SW1)
	106	do_IRQ(MSP_INT_SW1);
	107	}
	108
92592c9c	109	static struct irqaction cic_cascade_msp = {
35832e26	110	.handler = no_action,
a705dc7c	111	.name = "MSP CIC cascade",
5a4a4ad8	112	.flags = IRQF_NO_THREAD,
35832e26 MSJ	113	};
35832e26 MSJ	114
92592c9c A	115	static struct irqaction per_cascade_msp = {
92592c9c A	116	.handler = no_action,
a705dc7c	117	.name = "MSP PER cascade",
5a4a4ad8	118	.flags = IRQF_NO_THREAD,
92592c9c	119	};
35832e26 MSJ	120
	121	void __init arch_init_irq(void)
	122	{
92592c9c A	123	/* assume we'll be using vectored interrupt mode except in UP mode*/
	124	#ifdef CONFIG_MIPS_MT
	125	BUG_ON(!cpu_has_vint);
	126	#endif
35832e26 MSJ	127	/* initialize the 1st-level CPU based interrupt controller */
	128	mips_cpu_irq_init();
	129
	130	#ifdef CONFIG_IRQ_MSP_CIC
	131	msp_cic_irq_init();
92592c9c A	132	#ifdef CONFIG_MIPS_MT
	133	set_vi_handler(MSP_INT_CIC, msp_cic_irq_dispatch);
	134	set_vi_handler(MSP_INT_MAC0, mac0_int_dispatch);
	135	set_vi_handler(MSP_INT_MAC1, mac1_int_dispatch);
	136	set_vi_handler(MSP_INT_SAR, mac2_int_dispatch);
	137	set_vi_handler(MSP_INT_USB, usb_int_dispatch);
	138	set_vi_handler(MSP_INT_SEC, sec_int_dispatch);
	139	#ifdef CONFIG_MIPS_MT_SMP
	140	msp_vsmp_int_init();
	141	#elif defined CONFIG_MIPS_MT_SMTC
	142	/Set hwmask for all platform devices /
	143	irq_hwmask[MSP_INT_MAC0] = C_IRQ0;
	144	irq_hwmask[MSP_INT_MAC1] = C_IRQ1;
	145	irq_hwmask[MSP_INT_USB] = C_IRQ2;
	146	irq_hwmask[MSP_INT_SAR] = C_IRQ3;
	147	irq_hwmask[MSP_INT_SEC] = C_IRQ5;
	148
	149	#endif /* CONFIG_MIPS_MT_SMP */
	150	#endif /* CONFIG_MIPS_MT */
35832e26	151	/* setup the cascaded interrupts */
92592c9c A	152	setup_irq(MSP_INT_CIC, &cic_cascade_msp);
	153	setup_irq(MSP_INT_PER, &per_cascade_msp);
	154
35832e26 MSJ	155	#else
35832e26 MSJ	156	/* setup the 2nd-level SLP register based interrupt controller */
92592c9c	157	/* VSMP /SMTC support support is not enabled for SLP */
35832e26 MSJ	158	msp_slp_irq_init();
	159
	160	/* setup the cascaded SLP/PER interrupts */
92592c9c A	161	setup_irq(MSP_INT_SLP, &cic_cascade_msp);
92592c9c A	162	setup_irq(MSP_INT_PER, &per_cascade_msp);
35832e26 MSJ	163	#endif
35832e26 MSJ	164	}