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Commit | Line | Data |
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35832e26 MSJ |
1 | /* |
2 | * Setting up the clock on MSP SOCs. No RTC typically. | |
3 | * | |
4 | * Carsten Langgaard, carstenl@mips.com | |
5 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. | |
6 | * | |
7 | * ######################################################################## | |
8 | * | |
9 | * This program is free software; you can distribute it and/or modify it | |
10 | * under the terms of the GNU General Public License (Version 2) as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
21 | * | |
22 | * ######################################################################## | |
23 | */ | |
24 | ||
25 | #include <linux/init.h> | |
26 | #include <linux/kernel_stat.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/spinlock.h> | |
35832e26 MSJ |
29 | #include <linux/ptrace.h> |
30 | ||
3b042d08 | 31 | #include <asm/cevt-r4k.h> |
35832e26 MSJ |
32 | #include <asm/mipsregs.h> |
33 | #include <asm/time.h> | |
34 | ||
35 | #include <msp_prom.h> | |
36 | #include <msp_int.h> | |
37 | #include <msp_regs.h> | |
38 | ||
3b042d08 A |
39 | #define get_current_vpe() \ |
40 | ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE) | |
41 | ||
42 | static struct irqaction timer_vpe1; | |
43 | static int tim_installed; | |
44 | ||
4b550488 | 45 | void __init plat_time_init(void) |
35832e26 | 46 | { |
70342287 | 47 | char *endp, *s; |
35832e26 MSJ |
48 | unsigned long cpu_rate = 0; |
49 | ||
50 | if (cpu_rate == 0) { | |
51 | s = prom_getenv("clkfreqhz"); | |
52 | cpu_rate = simple_strtoul(s, &endp, 10); | |
53 | if (endp != NULL && *endp != 0) { | |
54 | printk(KERN_ERR | |
55 | "Clock rate in Hz parse error: %s\n", s); | |
56 | cpu_rate = 0; | |
57 | } | |
58 | } | |
59 | ||
60 | if (cpu_rate == 0) { | |
61 | s = prom_getenv("clkfreq"); | |
62 | cpu_rate = 1000 * simple_strtoul(s, &endp, 10); | |
63 | if (endp != NULL && *endp != 0) { | |
64 | printk(KERN_ERR | |
65 | "Clock rate in MHz parse error: %s\n", s); | |
66 | cpu_rate = 0; | |
67 | } | |
68 | } | |
69 | ||
70 | if (cpu_rate == 0) { | |
71 | #if defined(CONFIG_PMC_MSP7120_EVAL) \ | |
72 | || defined(CONFIG_PMC_MSP7120_GW) | |
73 | cpu_rate = 400000000; | |
74 | #elif defined(CONFIG_PMC_MSP7120_FPGA) | |
75 | cpu_rate = 25000000; | |
76 | #else | |
77 | cpu_rate = 150000000; | |
78 | #endif | |
79 | printk(KERN_ERR | |
80 | "Failed to determine CPU clock rate, " | |
81 | "assuming %ld hz ...\n", cpu_rate); | |
82 | } | |
83 | ||
84 | printk(KERN_WARNING "Clock rate set to %ld\n", cpu_rate); | |
85 | ||
86 | /* timer frequency is 1/2 clock rate */ | |
87 | mips_hpt_frequency = cpu_rate/2; | |
88 | } | |
89 | ||
078a55fc | 90 | unsigned int get_c0_compare_int(void) |
35832e26 | 91 | { |
3b042d08 A |
92 | /* MIPS_MT modes may want timer for second VPE */ |
93 | if ((get_current_vpe()) && !tim_installed) { | |
94 | memcpy(&timer_vpe1, &c0_compare_irqaction, sizeof(timer_vpe1)); | |
95 | setup_irq(MSP_INT_VPE1_TIMER, &timer_vpe1); | |
96 | tim_installed++; | |
97 | } | |
98 | ||
99 | return get_current_vpe() ? MSP_INT_VPE1_TIMER : MSP_INT_VPE0_TIMER; | |
35832e26 | 100 | } |