projects / mirror_ubuntu-jammy-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 74ba9207 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| edb6310a DL |
2 | /* |
| 3 | * board.c: STB225 board support. | |
| 4 | * | |
| 5 | * Copyright 2008 NXP Semiconductors | |
| 6 | * Chris Steel <chris.steel@nxp.com> | |
| 7 | * Daniel Laird <daniel.j.laird@nxp.com> | |
| 8 | * | |
| 9 | * Based on software written by: | |
| 70342287 | 10 | * Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code. |
| edb6310a DL |
11 | */ |
| 12 | #include <linux/init.h> | |
| 13 | #include <asm/bootinfo.h> | |
| 14 | #include <linux/mm.h> | |
| 15 | #include <pnx833x.h> | |
| 16 | #include <gpio.h> | |
| 17 | ||
| 18 | /* endianess twiddlers */ | |
| 19 | #define PNX8335_DEBUG0 0x4400 | |
| 20 | #define PNX8335_DEBUG1 0x4404 | |
| 21 | #define PNX8335_DEBUG2 0x4408 | |
| 22 | #define PNX8335_DEBUG3 0x440c | |
| 23 | #define PNX8335_DEBUG4 0x4410 | |
| 24 | #define PNX8335_DEBUG5 0x4414 | |
| 25 | #define PNX8335_DEBUG6 0x4418 | |
| 26 | #define PNX8335_DEBUG7 0x441c | |
| 27 | ||
| 28 | int prom_argc; | |
| 982f6ffe | 29 | char **prom_argv, **prom_envp; |
| edb6310a DL |
30 | |
| 31 | extern void prom_init_cmdline(void); | |
| 32 | extern char *prom_getenv(char *envname); | |
| 33 | ||
| 34 | const char *get_system_type(void) | |
| 35 | { | |
| 36 | return "NXP STB22x"; | |
| 37 | } | |
| 38 | ||
| 39 | static inline unsigned long env_or_default(char *env, unsigned long dfl) | |
| 40 | { | |
| 41 | char *str = prom_getenv(env); | |
| 42 | return str ? simple_strtol(str, 0, 0) : dfl; | |
| 43 | } | |
| 44 | ||
| 45 | void __init prom_init(void) | |
| 46 | { | |
| 47 | unsigned long memsize; | |
| 48 | ||
| 49 | prom_argc = fw_arg0; | |
| 50 | prom_argv = (char **)fw_arg1; | |
| 51 | prom_envp = (char **)fw_arg2; | |
| 52 | ||
| 53 | prom_init_cmdline(); | |
| 54 | ||
| 55 | memsize = env_or_default("memsize", 0x02000000); | |
| 56 | add_memory_region(0, memsize, BOOT_MEM_RAM); | |
| 57 | } | |
| 58 | ||
| 59 | void __init pnx833x_board_setup(void) | |
| 60 | { | |
| 61 | pnx833x_gpio_select_function_alt(4); | |
| 62 | pnx833x_gpio_select_output(4); | |
| 63 | pnx833x_gpio_select_function_alt(5); | |
| 64 | pnx833x_gpio_select_input(5); | |
| 65 | pnx833x_gpio_select_function_alt(6); | |
| 66 | pnx833x_gpio_select_input(6); | |
| 67 | pnx833x_gpio_select_function_alt(7); | |
| 68 | pnx833x_gpio_select_output(7); | |
| 69 | ||
| 70 | pnx833x_gpio_select_function_alt(25); | |
| 71 | pnx833x_gpio_select_function_alt(26); | |
| 72 | ||
| 73 | pnx833x_gpio_select_function_alt(27); | |
| 74 | pnx833x_gpio_select_function_alt(28); | |
| 75 | pnx833x_gpio_select_function_alt(29); | |
| 76 | pnx833x_gpio_select_function_alt(30); | |
| 77 | pnx833x_gpio_select_function_alt(31); | |
| 78 | pnx833x_gpio_select_function_alt(32); | |
| 79 | pnx833x_gpio_select_function_alt(33); | |
| 80 | ||
| c1d7f41c | 81 | #if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM) |
| edb6310a DL |
82 | /* Setup MIU for NAND access on CS0... |
| 83 | * | |
| 84 | * (it seems that we must also configure CS1 for reliable operation, | |
| 85 | * otherwise the first read ID command will fail if it's read as 4 bytes | |
| 86 | * but pass if it's read as 1 word.) | |
| 87 | */ | |
| 88 | ||
| 89 | /* Setup MIU CS0 & CS1 timing */ | |
| 90 | PNX833X_MIU_SEL0 = 0; | |
| 91 | PNX833X_MIU_SEL1 = 0; | |
| 92 | PNX833X_MIU_SEL0_TIMING = 0x50003081; | |
| 93 | PNX833X_MIU_SEL1_TIMING = 0x50003081; | |
| 94 | ||
| 95 | /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */ | |
| 96 | pnx833x_gpio_select_function_alt(0); | |
| 97 | ||
| 98 | /* Setup GPIO 04 to input NAND read/busy signal */ | |
| 99 | pnx833x_gpio_select_function_io(4); | |
| 100 | pnx833x_gpio_select_input(4); | |
| 101 | ||
| 102 | /* Setup GPIO 05 to disable NAND write protect */ | |
| 103 | pnx833x_gpio_select_function_io(5); | |
| 104 | pnx833x_gpio_select_output(5); | |
| 105 | pnx833x_gpio_write(1, 5); | |
| 106 | ||
| c1d7f41c | 107 | #elif IS_ENABLED(CONFIG_MTD_CFI) |
| edb6310a DL |
108 | |
| 109 | /* Set up MIU for 16-bit NOR access on CS0 and CS1... */ | |
| 110 | ||
| 111 | /* Setup MIU CS0 & CS1 timing */ | |
| 112 | PNX833X_MIU_SEL0 = 1; | |
| 113 | PNX833X_MIU_SEL1 = 1; | |
| 114 | PNX833X_MIU_SEL0_TIMING = 0x6A08D082; | |
| 115 | PNX833X_MIU_SEL1_TIMING = 0x6A08D082; | |
| 116 | ||
| 117 | /* Setup GPIO 00 for use as MIU CS1 (CS0 is not multiplexed, so does not need this) */ | |
| 118 | pnx833x_gpio_select_function_alt(0); | |
| 119 | #endif | |
| 120 | } |