[mirror_ubuntu-artful-kernel.git] / arch / mips / ralink / mt7620.c

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 *
 * Parts of this file are based on Ralink's 2.6.21 BSP
 *
 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>

#include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7620.h>

#include "common.h"

/* does the board have sdram or ddram */
static int dram_type;

static struct ralink_pinmux_grp mode_mux[] = {
	{
		.name = "i2c",
		.mask = MT7620_GPIO_MODE_I2C,
		.gpio_first = 1,
		.gpio_last = 2,
	}, {
		.name = "spi",
		.mask = MT7620_GPIO_MODE_SPI,
		.gpio_first = 3,
		.gpio_last = 6,
	}, {
		.name = "uartlite",
		.mask = MT7620_GPIO_MODE_UART1,
		.gpio_first = 15,
		.gpio_last = 16,
	}, {
		.name = "wdt",
		.mask = MT7620_GPIO_MODE_WDT,
		.gpio_first = 17,
		.gpio_last = 17,
	}, {
		.name = "mdio",
		.mask = MT7620_GPIO_MODE_MDIO,
		.gpio_first = 22,
		.gpio_last = 23,
	}, {
		.name = "rgmii1",
		.mask = MT7620_GPIO_MODE_RGMII1,
		.gpio_first = 24,
		.gpio_last = 35,
	}, {
		.name = "spi refclk",
		.mask = MT7620_GPIO_MODE_SPI_REF_CLK,
		.gpio_first = 37,
		.gpio_last = 39,
	}, {
		.name = "jtag",
		.mask = MT7620_GPIO_MODE_JTAG,
		.gpio_first = 40,
		.gpio_last = 44,
	}, {
		/* shared lines with jtag */
		.name = "ephy",
		.mask = MT7620_GPIO_MODE_EPHY,
		.gpio_first = 40,
		.gpio_last = 44,
	}, {
		.name = "nand",
		.mask = MT7620_GPIO_MODE_JTAG,
		.gpio_first = 45,
		.gpio_last = 59,
	}, {
		.name = "rgmii2",
		.mask = MT7620_GPIO_MODE_RGMII2,
		.gpio_first = 60,
		.gpio_last = 71,
	}, {
		.name = "wled",
		.mask = MT7620_GPIO_MODE_WLED,
		.gpio_first = 72,
		.gpio_last = 72,
	}, {0}
};

static struct ralink_pinmux_grp uart_mux[] = {
	{
		.name = "uartf",
		.mask = MT7620_GPIO_MODE_UARTF,
		.gpio_first = 7,
		.gpio_last = 14,
	}, {
		.name = "pcm uartf",
		.mask = MT7620_GPIO_MODE_PCM_UARTF,
		.gpio_first = 7,
		.gpio_last = 14,
	}, {
		.name = "pcm i2s",
		.mask = MT7620_GPIO_MODE_PCM_I2S,
		.gpio_first = 7,
		.gpio_last = 14,
	}, {
		.name = "i2s uartf",
		.mask = MT7620_GPIO_MODE_I2S_UARTF,
		.gpio_first = 7,
		.gpio_last = 14,
	}, {
		.name = "pcm gpio",
		.mask = MT7620_GPIO_MODE_PCM_GPIO,
		.gpio_first = 11,
		.gpio_last = 14,
	}, {
		.name = "gpio uartf",
		.mask = MT7620_GPIO_MODE_GPIO_UARTF,
		.gpio_first = 7,
		.gpio_last = 10,
	}, {
		.name = "gpio i2s",
		.mask = MT7620_GPIO_MODE_GPIO_I2S,
		.gpio_first = 7,
		.gpio_last = 10,
	}, {
		.name = "gpio",
		.mask = MT7620_GPIO_MODE_GPIO,
	}, {0}
};

struct ralink_pinmux rt_gpio_pinmux = {
	.mode = mode_mux,
	.uart = uart_mux,
	.uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
	.uart_mask = MT7620_GPIO_MODE_UART0_MASK,
};

static __init u32
mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
{
	u64 t;

	t = ref_rate;
	t *= mul;
	do_div(t, div);

	return t;
}

#define MHZ(x)		((x) * 1000 * 1000)

static __init unsigned long
mt7620_get_xtal_rate(void)
{
	u32 reg;

	reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
	if (reg & SYSCFG0_XTAL_FREQ_SEL)
		return MHZ(40);

	return MHZ(20);
}

static __init unsigned long
mt7620_get_periph_rate(unsigned long xtal_rate)
{
	u32 reg;

	reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
	if (reg & CLKCFG0_PERI_CLK_SEL)
		return xtal_rate;

	return MHZ(40);
}

static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };

static __init unsigned long
mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
{
	u32 reg;
	u32 mul;
	u32 div;

	reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
	if (reg & CPLL_CFG0_BYPASS_REF_CLK)
		return xtal_rate;

	if ((reg & CPLL_CFG0_SW_CFG) == 0)
		return MHZ(600);

	mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
	      CPLL_CFG0_PLL_MULT_RATIO_MASK;
	mul += 24;
	if (reg & CPLL_CFG0_LC_CURFCK)
		mul *= 2;

	div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
	      CPLL_CFG0_PLL_DIV_RATIO_MASK;

	WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));

	return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
}

static __init unsigned long
mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
{
	u32 reg;

	reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
	if (reg & CPLL_CFG1_CPU_AUX1)
		return xtal_rate;

	if (reg & CPLL_CFG1_CPU_AUX0)
		return MHZ(480);

	return cpu_pll_rate;
}

static __init unsigned long
mt7620_get_cpu_rate(unsigned long pll_rate)
{
	u32 reg;
	u32 mul;
	u32 div;

	reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);

	mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
	div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
	      CPU_SYS_CLKCFG_CPU_FDIV_MASK;

	return mt7620_calc_rate(pll_rate, mul, div);
}

static const u32 mt7620_ocp_dividers[16] __initconst = {
	[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
	[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
	[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
	[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
	[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
};

static __init unsigned long
mt7620_get_dram_rate(unsigned long pll_rate)
{
	if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
		return pll_rate / 4;

	return pll_rate / 3;
}

static __init unsigned long
mt7620_get_sys_rate(unsigned long cpu_rate)
{
	u32 reg;
	u32 ocp_ratio;
	u32 div;

	reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);

	ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
		    CPU_SYS_CLKCFG_OCP_RATIO_MASK;

	if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
		return cpu_rate;

	div = mt7620_ocp_dividers[ocp_ratio];
	if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
		return cpu_rate;

	return cpu_rate / div;
}

void __init ralink_clk_init(void)
{
	unsigned long xtal_rate;
	unsigned long cpu_pll_rate;
	unsigned long pll_rate;
	unsigned long cpu_rate;
	unsigned long sys_rate;
	unsigned long dram_rate;
	unsigned long periph_rate;

	xtal_rate = mt7620_get_xtal_rate();

	cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
	pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);

	cpu_rate = mt7620_get_cpu_rate(pll_rate);
	dram_rate = mt7620_get_dram_rate(pll_rate);
	sys_rate = mt7620_get_sys_rate(cpu_rate);
	periph_rate = mt7620_get_periph_rate(xtal_rate);

#define RFMT(label)	label ":%lu.%03luMHz "
#define RINT(x)		((x) / 1000000)
#define RFRAC(x)	(((x) / 1000) % 1000)

	pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
		 RINT(xtal_rate), RFRAC(xtal_rate),
		 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
		 RINT(pll_rate), RFRAC(pll_rate));

	pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
		 RINT(cpu_rate), RFRAC(cpu_rate),
		 RINT(dram_rate), RFRAC(dram_rate),
		 RINT(sys_rate), RFRAC(sys_rate),
		 RINT(periph_rate), RFRAC(periph_rate));

#undef RFRAC
#undef RINT
#undef RFMT

	ralink_clk_add("cpu", cpu_rate);
	ralink_clk_add("10000100.timer", periph_rate);
	ralink_clk_add("10000120.watchdog", periph_rate);
	ralink_clk_add("10000500.uart", periph_rate);
	ralink_clk_add("10000c00.uartlite", periph_rate);
}

void __init ralink_of_remap(void)
{
	rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
	rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");

	if (!rt_sysc_membase || !rt_memc_membase)
		panic("Failed to remap core resources");
}

void prom_soc_init(struct ralink_soc_info *soc_info)
{
	void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
	unsigned char *name = NULL;
	u32 n0;
	u32 n1;
	u32 rev;
	u32 cfg0;

	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);

	if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
		name = "MT7620N";
		soc_info->compatible = "ralink,mt7620n-soc";
	} else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
		name = "MT7620A";
		soc_info->compatible = "ralink,mt7620a-soc";
	} else {
		panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
	}

	rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);

	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
		"Ralink %s ver:%u eco:%u",
		name,
		(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
		(rev & CHIP_REV_ECO_MASK));

	cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
	dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;

	switch (dram_type) {
	case SYSCFG0_DRAM_TYPE_SDRAM:
		pr_info("Board has SDRAM\n");
		soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
		soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
		break;

	case SYSCFG0_DRAM_TYPE_DDR1:
		pr_info("Board has DDR1\n");
		soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
		soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
		break;

	case SYSCFG0_DRAM_TYPE_DDR2:
		pr_info("Board has DDR2\n");
		soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
		soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
		break;
	default:
		BUG();
	}
	soc_info->mem_base = MT7620_DRAM_BASE;
}
Commit	Line	Data
594bde68 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Parts of this file are based on Ralink's 2.6.21 BSP
	7	*
	8	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
	9	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
	10	* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/module.h>
	16
	17	#include <asm/mipsregs.h>
	18	#include <asm/mach-ralink/ralink_regs.h>
	19	#include <asm/mach-ralink/mt7620.h>
	20
	21	#include "common.h"
	22
	23	/* does the board have sdram or ddram */
	24	static int dram_type;
	25
594bde68 JC	26	static struct ralink_pinmux_grp mode_mux[] = {
	27	{
	28	.name = "i2c",
	29	.mask = MT7620_GPIO_MODE_I2C,
	30	.gpio_first = 1,
	31	.gpio_last = 2,
	32	}, {
	33	.name = "spi",
	34	.mask = MT7620_GPIO_MODE_SPI,
	35	.gpio_first = 3,
	36	.gpio_last = 6,
	37	}, {
	38	.name = "uartlite",
	39	.mask = MT7620_GPIO_MODE_UART1,
	40	.gpio_first = 15,
	41	.gpio_last = 16,
	42	}, {
	43	.name = "wdt",
	44	.mask = MT7620_GPIO_MODE_WDT,
	45	.gpio_first = 17,
	46	.gpio_last = 17,
	47	}, {
	48	.name = "mdio",
	49	.mask = MT7620_GPIO_MODE_MDIO,
	50	.gpio_first = 22,
	51	.gpio_last = 23,
	52	}, {
	53	.name = "rgmii1",
	54	.mask = MT7620_GPIO_MODE_RGMII1,
	55	.gpio_first = 24,
	56	.gpio_last = 35,
	57	}, {
	58	.name = "spi refclk",
	59	.mask = MT7620_GPIO_MODE_SPI_REF_CLK,
	60	.gpio_first = 37,
	61	.gpio_last = 39,
	62	}, {
	63	.name = "jtag",
	64	.mask = MT7620_GPIO_MODE_JTAG,
	65	.gpio_first = 40,
	66	.gpio_last = 44,
	67	}, {
	68	/* shared lines with jtag */
	69	.name = "ephy",
	70	.mask = MT7620_GPIO_MODE_EPHY,
	71	.gpio_first = 40,
	72	.gpio_last = 44,
	73	}, {
	74	.name = "nand",
	75	.mask = MT7620_GPIO_MODE_JTAG,
	76	.gpio_first = 45,
	77	.gpio_last = 59,
	78	}, {
	79	.name = "rgmii2",
	80	.mask = MT7620_GPIO_MODE_RGMII2,
	81	.gpio_first = 60,
	82	.gpio_last = 71,
	83	}, {
	84	.name = "wled",
	85	.mask = MT7620_GPIO_MODE_WLED,
	86	.gpio_first = 72,
	87	.gpio_last = 72,
	88	}, {0}
	89	};
90
91	static struct ralink_pinmux_grp uart_mux[] = {
92	{
93	.name = "uartf",
94	.mask = MT7620_GPIO_MODE_UARTF,
95	.gpio_first = 7,
96	.gpio_last = 14,
97	}, {
98	.name = "pcm uartf",
99	.mask = MT7620_GPIO_MODE_PCM_UARTF,
100	.gpio_first = 7,
101	.gpio_last = 14,
102	}, {
103	.name = "pcm i2s",
104	.mask = MT7620_GPIO_MODE_PCM_I2S,
105	.gpio_first = 7,
106	.gpio_last = 14,
107	}, {
108	.name = "i2s uartf",
109	.mask = MT7620_GPIO_MODE_I2S_UARTF,
110	.gpio_first = 7,
111	.gpio_last = 14,
112	}, {
113	.name = "pcm gpio",
114	.mask = MT7620_GPIO_MODE_PCM_GPIO,
115	.gpio_first = 11,
116	.gpio_last = 14,
117	}, {
118	.name = "gpio uartf",
119	.mask = MT7620_GPIO_MODE_GPIO_UARTF,
120	.gpio_first = 7,
121	.gpio_last = 10,
122	}, {
123	.name = "gpio i2s",
124	.mask = MT7620_GPIO_MODE_GPIO_I2S,
125	.gpio_first = 7,
126	.gpio_last = 10,
127	}, {
128	.name = "gpio",
129	.mask = MT7620_GPIO_MODE_GPIO,
130	}, {0}
131	};
132
133	struct ralink_pinmux rt_gpio_pinmux = {
134	.mode = mode_mux,
135	.uart = uart_mux,
136	.uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
137	.uart_mask = MT7620_GPIO_MODE_UART0_MASK,
138	};
139
ded1e9d7 GJ	140	static __init u32
	141	mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
	142	{
	143	u64 t;
	144
	145	t = ref_rate;
	146	t *= mul;
	147	do_div(t, div);
	148
	149	return t;
	150	}
	151
	152	#define MHZ(x) ((x) * 1000 * 1000)
	153
	154	static __init unsigned long
	155	mt7620_get_xtal_rate(void)
594bde68	156	{
ded1e9d7 GJ	157	u32 reg;
	158
	159	reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
	160	if (reg & SYSCFG0_XTAL_FREQ_SEL)
	161	return MHZ(40);
	162
	163	return MHZ(20);
	164	}
	165
	166	static __init unsigned long
	167	mt7620_get_periph_rate(unsigned long xtal_rate)
	168	{
	169	u32 reg;
	170
	171	reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
	172	if (reg & CLKCFG0_PERI_CLK_SEL)
	173	return xtal_rate;
	174
	175	return MHZ(40);
	176	}
594bde68	177
ded1e9d7 GJ	178	static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
	179
	180	static __init unsigned long
	181	mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
	182	{
	183	u32 reg;
	184	u32 mul;
	185	u32 div;
	186
	187	reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
	188	if (reg & CPLL_CFG0_BYPASS_REF_CLK)
	189	return xtal_rate;
	190
	191	if ((reg & CPLL_CFG0_SW_CFG) == 0)
	192	return MHZ(600);
	193
	194	mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
	195	CPLL_CFG0_PLL_MULT_RATIO_MASK;
	196	mul += 24;
	197	if (reg & CPLL_CFG0_LC_CURFCK)
	198	mul *= 2;
	199
	200	div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
	201	CPLL_CFG0_PLL_DIV_RATIO_MASK;
	202
	203	WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
	204
	205	return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
	206	}
	207
	208	static __init unsigned long
	209	mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
	210	{
	211	u32 reg;
	212
	213	reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
	214	if (reg & CPLL_CFG1_CPU_AUX1)
	215	return xtal_rate;
	216
	217	if (reg & CPLL_CFG1_CPU_AUX0)
	218	return MHZ(480);
	219
	220	return cpu_pll_rate;
	221	}
	222
	223	static __init unsigned long
	224	mt7620_get_cpu_rate(unsigned long pll_rate)
	225	{
	226	u32 reg;
	227	u32 mul;
	228	u32 div;
	229
	230	reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
	231
	232	mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
	233	div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
	234	CPU_SYS_CLKCFG_CPU_FDIV_MASK;
	235
	236	return mt7620_calc_rate(pll_rate, mul, div);
	237	}
	238
	239	static const u32 mt7620_ocp_dividers[16] __initconst = {
	240	[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
	241	[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
242	[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
243	[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
244	[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
245	};
246
247	static __init unsigned long
248	mt7620_get_dram_rate(unsigned long pll_rate)
249	{
594bde68	250	if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
ded1e9d7 GJ	251	return pll_rate / 4;
	252
	253	return pll_rate / 3;
	254	}
	255
	256	static __init unsigned long
	257	mt7620_get_sys_rate(unsigned long cpu_rate)
	258	{
	259	u32 reg;
	260	u32 ocp_ratio;
	261	u32 div;
	262
	263	reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
	264
	265	ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
	266	CPU_SYS_CLKCFG_OCP_RATIO_MASK;
	267
	268	if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
	269	return cpu_rate;
	270
	271	div = mt7620_ocp_dividers[ocp_ratio];
	272	if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
	273	return cpu_rate;
	274
	275	return cpu_rate / div;
	276	}
	277
	278	void __init ralink_clk_init(void)
	279	{
	280	unsigned long xtal_rate;
	281	unsigned long cpu_pll_rate;
	282	unsigned long pll_rate;
	283	unsigned long cpu_rate;
	284	unsigned long sys_rate;
	285	unsigned long dram_rate;
	286	unsigned long periph_rate;
	287
	288	xtal_rate = mt7620_get_xtal_rate();
	289
	290	cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
	291	pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
	292
	293	cpu_rate = mt7620_get_cpu_rate(pll_rate);
	294	dram_rate = mt7620_get_dram_rate(pll_rate);
	295	sys_rate = mt7620_get_sys_rate(cpu_rate);
	296	periph_rate = mt7620_get_periph_rate(xtal_rate);
	297
	298	#define RFMT(label) label ":%lu.%03luMHz "
	299	#define RINT(x) ((x) / 1000000)
	300	#define RFRAC(x) (((x) / 1000) % 1000)
	301
	302	pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
	303	RINT(xtal_rate), RFRAC(xtal_rate),
	304	RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
	305	RINT(pll_rate), RFRAC(pll_rate));
	306
	307	pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
	308	RINT(cpu_rate), RFRAC(cpu_rate),
	309	RINT(dram_rate), RFRAC(dram_rate),
	310	RINT(sys_rate), RFRAC(sys_rate),
	311	RINT(periph_rate), RFRAC(periph_rate));
	312
	313	#undef RFRAC
	314	#undef RINT
315	#undef RFMT
594bde68 JC	316
594bde68 JC	317	ralink_clk_add("cpu", cpu_rate);
ded1e9d7	318	ralink_clk_add("10000100.timer", periph_rate);
68c9b7ed	319	ralink_clk_add("10000120.watchdog", periph_rate);
ded1e9d7 GJ	320	ralink_clk_add("10000500.uart", periph_rate);
ded1e9d7 GJ	321	ralink_clk_add("10000c00.uartlite", periph_rate);
594bde68 JC	322	}
	323
	324	void __init ralink_of_remap(void)
	325	{
	326	rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
	327	rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
	328
	329	if (!rt_sysc_membase \|\| !rt_memc_membase)
	330	panic("Failed to remap core resources");
	331	}
	332
	333	void prom_soc_init(struct ralink_soc_info *soc_info)
	334	{
	335	void __iomem sysc = (void __iomem ) KSEG1ADDR(MT7620_SYSC_BASE);
	336	unsigned char *name = NULL;
	337	u32 n0;
	338	u32 n1;
	339	u32 rev;
	340	u32 cfg0;
	341
	342	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
	343	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
	344
	345	if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
	346	name = "MT7620N";
	347	soc_info->compatible = "ralink,mt7620n-soc";
	348	} else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
	349	name = "MT7620A";
	350	soc_info->compatible = "ralink,mt7620a-soc";
	351	} else {
	352	panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
	353	}
	354
	355	rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
	356
	357	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
	358	"Ralink %s ver:%u eco:%u",
	359	name,
	360	(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
	361	(rev & CHIP_REV_ECO_MASK));
	362
	363	cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
	364	dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
51e39607 JC	365
	366	switch (dram_type) {
	367	case SYSCFG0_DRAM_TYPE_SDRAM:
538e0daa	368	pr_info("Board has SDRAM\n");
51e39607 JC	369	soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
	370	soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
	371	break;
	372
	373	case SYSCFG0_DRAM_TYPE_DDR1:
538e0daa	374	pr_info("Board has DDR1\n");
51e39607 JC	375	soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
	376	soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
	377	break;
	378
	379	case SYSCFG0_DRAM_TYPE_DDR2:
538e0daa	380	pr_info("Board has DDR2\n");
51e39607 JC	381	soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
	382	soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
	383	break;
	384	default:
	385	BUG();
	386	}
	387	soc_info->mem_base = MT7620_DRAM_BASE;
594bde68	388	}