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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1df7addb | 2 | /* |
1df7addb JC |
3 | * |
4 | * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com> | |
97b92108 | 5 | * Copyright (C) 2015 John Crispin <john@phrozen.org> |
1df7addb JC |
6 | */ |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/init.h> | |
1df7addb JC |
10 | |
11 | #include <asm/mipsregs.h> | |
12 | #include <asm/smp-ops.h> | |
e83f7e02 | 13 | #include <asm/mips-cps.h> |
1df7addb JC |
14 | #include <asm/mach-ralink/ralink_regs.h> |
15 | #include <asm/mach-ralink/mt7621.h> | |
16 | ||
17 | #include <pinmux.h> | |
18 | ||
19 | #include "common.h" | |
20 | ||
21 | #define SYSC_REG_SYSCFG 0x10 | |
22 | #define SYSC_REG_CPLL_CLKCFG0 0x2c | |
23 | #define SYSC_REG_CUR_CLK_STS 0x44 | |
24 | #define CPU_CLK_SEL (BIT(30) | BIT(31)) | |
25 | ||
26 | #define MT7621_GPIO_MODE_UART1 1 | |
27 | #define MT7621_GPIO_MODE_I2C 2 | |
28 | #define MT7621_GPIO_MODE_UART3_MASK 0x3 | |
29 | #define MT7621_GPIO_MODE_UART3_SHIFT 3 | |
30 | #define MT7621_GPIO_MODE_UART3_GPIO 1 | |
31 | #define MT7621_GPIO_MODE_UART2_MASK 0x3 | |
32 | #define MT7621_GPIO_MODE_UART2_SHIFT 5 | |
33 | #define MT7621_GPIO_MODE_UART2_GPIO 1 | |
34 | #define MT7621_GPIO_MODE_JTAG 7 | |
35 | #define MT7621_GPIO_MODE_WDT_MASK 0x3 | |
36 | #define MT7621_GPIO_MODE_WDT_SHIFT 8 | |
37 | #define MT7621_GPIO_MODE_WDT_GPIO 1 | |
38 | #define MT7621_GPIO_MODE_PCIE_RST 0 | |
39 | #define MT7621_GPIO_MODE_PCIE_REF 2 | |
40 | #define MT7621_GPIO_MODE_PCIE_MASK 0x3 | |
41 | #define MT7621_GPIO_MODE_PCIE_SHIFT 10 | |
42 | #define MT7621_GPIO_MODE_PCIE_GPIO 1 | |
43 | #define MT7621_GPIO_MODE_MDIO_MASK 0x3 | |
44 | #define MT7621_GPIO_MODE_MDIO_SHIFT 12 | |
45 | #define MT7621_GPIO_MODE_MDIO_GPIO 1 | |
46 | #define MT7621_GPIO_MODE_RGMII1 14 | |
47 | #define MT7621_GPIO_MODE_RGMII2 15 | |
48 | #define MT7621_GPIO_MODE_SPI_MASK 0x3 | |
49 | #define MT7621_GPIO_MODE_SPI_SHIFT 16 | |
50 | #define MT7621_GPIO_MODE_SPI_GPIO 1 | |
51 | #define MT7621_GPIO_MODE_SDHCI_MASK 0x3 | |
52 | #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 | |
53 | #define MT7621_GPIO_MODE_SDHCI_GPIO 1 | |
54 | ||
55 | static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; | |
56 | static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; | |
57 | static struct rt2880_pmx_func uart3_grp[] = { | |
58 | FUNC("uart3", 0, 5, 4), | |
59 | FUNC("i2s", 2, 5, 4), | |
60 | FUNC("spdif3", 3, 5, 4), | |
61 | }; | |
62 | static struct rt2880_pmx_func uart2_grp[] = { | |
63 | FUNC("uart2", 0, 9, 4), | |
64 | FUNC("pcm", 2, 9, 4), | |
65 | FUNC("spdif2", 3, 9, 4), | |
66 | }; | |
67 | static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; | |
68 | static struct rt2880_pmx_func wdt_grp[] = { | |
69 | FUNC("wdt rst", 0, 18, 1), | |
70 | FUNC("wdt refclk", 2, 18, 1), | |
71 | }; | |
72 | static struct rt2880_pmx_func pcie_rst_grp[] = { | |
73 | FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), | |
74 | FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) | |
75 | }; | |
76 | static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; | |
77 | static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; | |
78 | static struct rt2880_pmx_func spi_grp[] = { | |
79 | FUNC("spi", 0, 34, 7), | |
80 | FUNC("nand1", 2, 34, 7), | |
81 | }; | |
82 | static struct rt2880_pmx_func sdhci_grp[] = { | |
83 | FUNC("sdhci", 0, 41, 8), | |
84 | FUNC("nand2", 2, 41, 8), | |
85 | }; | |
86 | static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; | |
87 | ||
88 | static struct rt2880_pmx_group mt7621_pinmux_data[] = { | |
89 | GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), | |
90 | GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), | |
91 | GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, | |
92 | MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT), | |
93 | GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK, | |
94 | MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT), | |
95 | GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG), | |
96 | GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK, | |
97 | MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT), | |
98 | GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK, | |
99 | MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT), | |
100 | GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK, | |
101 | MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT), | |
102 | GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2), | |
103 | GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK, | |
104 | MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT), | |
105 | GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK, | |
106 | MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT), | |
107 | GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1), | |
108 | { 0 } | |
109 | }; | |
110 | ||
111 | phys_addr_t mips_cpc_default_phys_base(void) | |
112 | { | |
113 | panic("Cannot detect cpc address"); | |
114 | } | |
115 | ||
116 | void __init ralink_clk_init(void) | |
117 | { | |
118 | int cpu_fdiv = 0; | |
119 | int cpu_ffrac = 0; | |
120 | int fbdiv = 0; | |
121 | u32 clk_sts, syscfg; | |
122 | u8 clk_sel = 0, xtal_mode; | |
123 | u32 cpu_clk; | |
124 | ||
125 | if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0) | |
126 | clk_sel = 1; | |
127 | ||
128 | switch (clk_sel) { | |
129 | case 0: | |
130 | clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); | |
131 | cpu_fdiv = ((clk_sts >> 8) & 0x1F); | |
132 | cpu_ffrac = (clk_sts & 0x1F); | |
133 | cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000; | |
134 | break; | |
135 | ||
136 | case 1: | |
137 | fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1; | |
138 | syscfg = rt_sysc_r32(SYSC_REG_SYSCFG); | |
139 | xtal_mode = (syscfg >> 6) & 0x7; | |
140 | if (xtal_mode >= 6) { | |
141 | /* 25Mhz Xtal */ | |
142 | cpu_clk = 25 * fbdiv * 1000 * 1000; | |
143 | } else if (xtal_mode >= 3) { | |
144 | /* 40Mhz Xtal */ | |
145 | cpu_clk = 40 * fbdiv * 1000 * 1000; | |
146 | } else { | |
147 | /* 20Mhz Xtal */ | |
148 | cpu_clk = 20 * fbdiv * 1000 * 1000; | |
149 | } | |
150 | break; | |
151 | } | |
152 | } | |
153 | ||
154 | void __init ralink_of_remap(void) | |
155 | { | |
156 | rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); | |
157 | rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc"); | |
158 | ||
159 | if (!rt_sysc_membase || !rt_memc_membase) | |
160 | panic("Failed to remap core resources"); | |
161 | } | |
162 | ||
163 | void prom_soc_init(struct ralink_soc_info *soc_info) | |
164 | { | |
165 | void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); | |
166 | unsigned char *name = NULL; | |
167 | u32 n0; | |
168 | u32 n1; | |
169 | u32 rev; | |
170 | ||
a63d706e N |
171 | /* Early detection of CMP support */ |
172 | mips_cm_probe(); | |
173 | mips_cpc_probe(); | |
174 | ||
175 | if (mips_cps_numiocu(0)) { | |
176 | /* | |
177 | * mips_cm_probe() wipes out bootloader | |
178 | * config for CM regions and we have to configure them | |
179 | * again. This SoC cannot talk to pamlbus devices | |
180 | * witout proper iocu region set up. | |
181 | * | |
182 | * FIXME: it would be better to do this with values | |
183 | * from DT, but we need this very early because | |
184 | * without this we cannot talk to pretty much anything | |
185 | * including serial. | |
186 | */ | |
187 | write_gcr_reg0_base(MT7621_PALMBUS_BASE); | |
188 | write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | | |
189 | CM_GCR_REGn_MASK_CMTGT_IOCU0); | |
190 | __sync(); | |
191 | } | |
192 | ||
1df7addb JC |
193 | n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); |
194 | n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); | |
195 | ||
196 | if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) { | |
197 | name = "MT7621"; | |
198 | soc_info->compatible = "mtk,mt7621-soc"; | |
199 | } else { | |
200 | panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1); | |
201 | } | |
4f79ddec | 202 | ralink_soc = MT762X_SOC_MT7621AT; |
1df7addb JC |
203 | rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); |
204 | ||
205 | snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, | |
206 | "MediaTek %s ver:%u eco:%u", | |
207 | name, | |
208 | (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, | |
209 | (rev & CHIP_REV_ECO_MASK)); | |
210 | ||
211 | soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN; | |
212 | soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX; | |
213 | soc_info->mem_base = MT7621_DRAM_BASE; | |
214 | ||
215 | rt2880_pinmux_data = mt7621_pinmux_data; | |
216 | ||
1df7addb JC |
217 | |
218 | if (!register_cps_smp_ops()) | |
219 | return; | |
220 | if (!register_cmp_smp_ops()) | |
221 | return; | |
222 | if (!register_vsmp_smp_ops()) | |
223 | return; | |
224 | } |