projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| c06e836a JC |
1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify it | |
| 3 | * under the terms of the GNU General Public License version 2 as published | |
| 4 | * by the Free Software Foundation. | |
| 5 | * | |
| 6 | * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> | |
| 7 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> | |
| 97b92108 | 8 | * Copyright (C) 2013 John Crispin <john@phrozen.org> |
| c06e836a JC |
9 | */ |
| 10 | ||
| 11 | #include <linux/pm.h> | |
| 12 | #include <linux/io.h> | |
| 2a153f1c | 13 | #include <linux/of.h> |
| 1a935205 | 14 | #include <linux/delay.h> |
| 2a153f1c | 15 | #include <linux/reset-controller.h> |
| c06e836a JC |
16 | |
| 17 | #include <asm/reboot.h> | |
| 18 | ||
| 19 | #include <asm/mach-ralink/ralink_regs.h> | |
| 20 | ||
| 21 | /* Reset Control */ | |
| 1a935205 JC |
22 | #define SYSC_REG_RESET_CTRL 0x034 |
| 23 | ||
| 24 | #define RSTCTL_RESET_PCI BIT(26) | |
| 25 | #define RSTCTL_RESET_SYSTEM BIT(0) | |
| c06e836a | 26 | |
| 2a153f1c JC |
27 | static int ralink_assert_device(struct reset_controller_dev *rcdev, |
| 28 | unsigned long id) | |
| 29 | { | |
| 30 | u32 val; | |
| 31 | ||
| 32 | if (id < 8) | |
| 33 | return -1; | |
| 34 | ||
| 35 | val = rt_sysc_r32(SYSC_REG_RESET_CTRL); | |
| 36 | val |= BIT(id); | |
| 37 | rt_sysc_w32(val, SYSC_REG_RESET_CTRL); | |
| 38 | ||
| 39 | return 0; | |
| 40 | } | |
| 41 | ||
| 42 | static int ralink_deassert_device(struct reset_controller_dev *rcdev, | |
| 43 | unsigned long id) | |
| 44 | { | |
| 45 | u32 val; | |
| 46 | ||
| 47 | if (id < 8) | |
| 48 | return -1; | |
| 49 | ||
| 50 | val = rt_sysc_r32(SYSC_REG_RESET_CTRL); | |
| 51 | val &= ~BIT(id); | |
| 52 | rt_sysc_w32(val, SYSC_REG_RESET_CTRL); | |
| 53 | ||
| 54 | return 0; | |
| 55 | } | |
| 56 | ||
| 57 | static int ralink_reset_device(struct reset_controller_dev *rcdev, | |
| 58 | unsigned long id) | |
| 59 | { | |
| 60 | ralink_assert_device(rcdev, id); | |
| 61 | return ralink_deassert_device(rcdev, id); | |
| 62 | } | |
| 63 | ||
| b11d0227 | 64 | static const struct reset_control_ops reset_ops = { |
| 2a153f1c JC |
65 | .reset = ralink_reset_device, |
| 66 | .assert = ralink_assert_device, | |
| 67 | .deassert = ralink_deassert_device, | |
| 68 | }; | |
| 69 | ||
| 70 | static struct reset_controller_dev reset_dev = { | |
| 71 | .ops = &reset_ops, | |
| 72 | .owner = THIS_MODULE, | |
| 73 | .nr_resets = 32, | |
| 74 | .of_reset_n_cells = 1, | |
| 75 | }; | |
| 76 | ||
| 77 | void ralink_rst_init(void) | |
| 78 | { | |
| 79 | reset_dev.of_node = of_find_compatible_node(NULL, NULL, | |
| 80 | "ralink,rt2880-reset"); | |
| 81 | if (!reset_dev.of_node) | |
| 82 | pr_err("Failed to find reset controller node"); | |
| 83 | else | |
| 84 | reset_controller_register(&reset_dev); | |
| 85 | } | |
| 86 | ||
| c06e836a JC |
87 | static void ralink_restart(char *command) |
| 88 | { | |
| 1a935205 JC |
89 | if (IS_ENABLED(CONFIG_PCI)) { |
| 90 | rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL); | |
| 91 | mdelay(50); | |
| 92 | } | |
| 93 | ||
| c06e836a JC |
94 | local_irq_disable(); |
| 95 | rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL); | |
| 96 | unreachable(); | |
| 97 | } | |
| 98 | ||
| 99 | static void ralink_halt(void) | |
| 100 | { | |
| 101 | local_irq_disable(); | |
| 102 | unreachable(); | |
| 103 | } | |
| 104 | ||
| 105 | static int __init mips_reboot_setup(void) | |
| 106 | { | |
| 107 | _machine_restart = ralink_restart; | |
| 108 | _machine_halt = ralink_halt; | |
| c06e836a JC |
109 | |
| 110 | return 0; | |
| 111 | } | |
| 112 | ||
| 113 | arch_initcall(mips_reboot_setup); |