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2809b317 JC |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify it | |
3 | * under the terms of the GNU General Public License version 2 as published | |
4 | * by the Free Software Foundation. | |
5 | * | |
6 | * Parts of this file are based on Ralink's 2.6.21 BSP | |
7 | * | |
8 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> | |
9 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> | |
10 | * Copyright (C) 2013 John Crispin <blogic@openwrt.org> | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | ||
17 | #include <asm/mipsregs.h> | |
18 | #include <asm/mach-ralink/ralink_regs.h> | |
19 | #include <asm/mach-ralink/rt305x.h> | |
20 | ||
21 | #include "common.h" | |
22 | ||
23 | enum rt305x_soc_type rt305x_soc; | |
24 | ||
0ba43370 | 25 | static struct ralink_pinmux_grp mode_mux[] = { |
2809b317 JC |
26 | { |
27 | .name = "i2c", | |
28 | .mask = RT305X_GPIO_MODE_I2C, | |
29 | .gpio_first = RT305X_GPIO_I2C_SD, | |
30 | .gpio_last = RT305X_GPIO_I2C_SCLK, | |
31 | }, { | |
32 | .name = "spi", | |
33 | .mask = RT305X_GPIO_MODE_SPI, | |
34 | .gpio_first = RT305X_GPIO_SPI_EN, | |
35 | .gpio_last = RT305X_GPIO_SPI_CLK, | |
36 | }, { | |
37 | .name = "uartlite", | |
38 | .mask = RT305X_GPIO_MODE_UART1, | |
39 | .gpio_first = RT305X_GPIO_UART1_TXD, | |
40 | .gpio_last = RT305X_GPIO_UART1_RXD, | |
41 | }, { | |
42 | .name = "jtag", | |
43 | .mask = RT305X_GPIO_MODE_JTAG, | |
44 | .gpio_first = RT305X_GPIO_JTAG_TDO, | |
45 | .gpio_last = RT305X_GPIO_JTAG_TDI, | |
46 | }, { | |
47 | .name = "mdio", | |
48 | .mask = RT305X_GPIO_MODE_MDIO, | |
49 | .gpio_first = RT305X_GPIO_MDIO_MDC, | |
50 | .gpio_last = RT305X_GPIO_MDIO_MDIO, | |
51 | }, { | |
52 | .name = "sdram", | |
53 | .mask = RT305X_GPIO_MODE_SDRAM, | |
54 | .gpio_first = RT305X_GPIO_SDRAM_MD16, | |
55 | .gpio_last = RT305X_GPIO_SDRAM_MD31, | |
56 | }, { | |
57 | .name = "rgmii", | |
58 | .mask = RT305X_GPIO_MODE_RGMII, | |
59 | .gpio_first = RT305X_GPIO_GE0_TXD0, | |
60 | .gpio_last = RT305X_GPIO_GE0_RXCLK, | |
61 | }, {0} | |
62 | }; | |
63 | ||
0ba43370 | 64 | static struct ralink_pinmux_grp uart_mux[] = { |
2809b317 JC |
65 | { |
66 | .name = "uartf", | |
67 | .mask = RT305X_GPIO_MODE_UARTF, | |
68 | .gpio_first = RT305X_GPIO_7, | |
69 | .gpio_last = RT305X_GPIO_14, | |
70 | }, { | |
71 | .name = "pcm uartf", | |
72 | .mask = RT305X_GPIO_MODE_PCM_UARTF, | |
73 | .gpio_first = RT305X_GPIO_7, | |
74 | .gpio_last = RT305X_GPIO_14, | |
75 | }, { | |
76 | .name = "pcm i2s", | |
77 | .mask = RT305X_GPIO_MODE_PCM_I2S, | |
78 | .gpio_first = RT305X_GPIO_7, | |
79 | .gpio_last = RT305X_GPIO_14, | |
80 | }, { | |
81 | .name = "i2s uartf", | |
82 | .mask = RT305X_GPIO_MODE_I2S_UARTF, | |
83 | .gpio_first = RT305X_GPIO_7, | |
84 | .gpio_last = RT305X_GPIO_14, | |
85 | }, { | |
86 | .name = "pcm gpio", | |
87 | .mask = RT305X_GPIO_MODE_PCM_GPIO, | |
88 | .gpio_first = RT305X_GPIO_10, | |
89 | .gpio_last = RT305X_GPIO_14, | |
90 | }, { | |
91 | .name = "gpio uartf", | |
92 | .mask = RT305X_GPIO_MODE_GPIO_UARTF, | |
93 | .gpio_first = RT305X_GPIO_7, | |
eb63875c | 94 | .gpio_last = RT305X_GPIO_10, |
2809b317 JC |
95 | }, { |
96 | .name = "gpio i2s", | |
97 | .mask = RT305X_GPIO_MODE_GPIO_I2S, | |
98 | .gpio_first = RT305X_GPIO_7, | |
eb63875c | 99 | .gpio_last = RT305X_GPIO_10, |
2809b317 JC |
100 | }, { |
101 | .name = "gpio", | |
102 | .mask = RT305X_GPIO_MODE_GPIO, | |
103 | }, {0} | |
104 | }; | |
105 | ||
0ba43370 | 106 | static void rt305x_wdt_reset(void) |
2809b317 JC |
107 | { |
108 | u32 t; | |
109 | ||
110 | /* enable WDT reset output on pin SRAM_CS_N */ | |
111 | t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); | |
112 | t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT << | |
113 | RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT; | |
114 | rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG); | |
115 | } | |
116 | ||
4114b6a6 | 117 | struct ralink_pinmux rt_gpio_pinmux = { |
2809b317 JC |
118 | .mode = mode_mux, |
119 | .uart = uart_mux, | |
120 | .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT, | |
eb63875c | 121 | .uart_mask = RT305X_GPIO_MODE_UART0_MASK, |
2809b317 JC |
122 | .wdt_reset = rt305x_wdt_reset, |
123 | }; | |
124 | ||
dafecee8 JC |
125 | static unsigned long rt5350_get_mem_size(void) |
126 | { | |
127 | void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); | |
128 | unsigned long ret; | |
129 | u32 t; | |
130 | ||
131 | t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); | |
132 | t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) & | |
133 | RT5350_SYSCFG0_DRAM_SIZE_MASK; | |
134 | ||
135 | switch (t) { | |
136 | case RT5350_SYSCFG0_DRAM_SIZE_2M: | |
137 | ret = 2; | |
138 | break; | |
139 | case RT5350_SYSCFG0_DRAM_SIZE_8M: | |
140 | ret = 8; | |
141 | break; | |
142 | case RT5350_SYSCFG0_DRAM_SIZE_16M: | |
143 | ret = 16; | |
144 | break; | |
145 | case RT5350_SYSCFG0_DRAM_SIZE_32M: | |
146 | ret = 32; | |
147 | break; | |
148 | case RT5350_SYSCFG0_DRAM_SIZE_64M: | |
149 | ret = 64; | |
150 | break; | |
151 | default: | |
152 | panic("rt5350: invalid DRAM size: %u", t); | |
153 | break; | |
154 | } | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
2809b317 JC |
159 | void __init ralink_clk_init(void) |
160 | { | |
161 | unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; | |
6ac8579b JC |
162 | unsigned long wmac_rate = 40000000; |
163 | ||
2809b317 JC |
164 | u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); |
165 | ||
166 | if (soc_is_rt305x() || soc_is_rt3350()) { | |
167 | t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & | |
168 | RT305X_SYSCFG_CPUCLK_MASK; | |
169 | switch (t) { | |
170 | case RT305X_SYSCFG_CPUCLK_LOW: | |
171 | cpu_rate = 320000000; | |
172 | break; | |
173 | case RT305X_SYSCFG_CPUCLK_HIGH: | |
174 | cpu_rate = 384000000; | |
175 | break; | |
176 | } | |
177 | sys_rate = uart_rate = wdt_rate = cpu_rate / 3; | |
178 | } else if (soc_is_rt3352()) { | |
179 | t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & | |
180 | RT3352_SYSCFG0_CPUCLK_MASK; | |
181 | switch (t) { | |
182 | case RT3352_SYSCFG0_CPUCLK_LOW: | |
183 | cpu_rate = 384000000; | |
184 | break; | |
185 | case RT3352_SYSCFG0_CPUCLK_HIGH: | |
186 | cpu_rate = 400000000; | |
187 | break; | |
188 | } | |
189 | sys_rate = wdt_rate = cpu_rate / 3; | |
190 | uart_rate = 40000000; | |
191 | } else if (soc_is_rt5350()) { | |
192 | t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & | |
193 | RT5350_SYSCFG0_CPUCLK_MASK; | |
194 | switch (t) { | |
195 | case RT5350_SYSCFG0_CPUCLK_360: | |
196 | cpu_rate = 360000000; | |
197 | sys_rate = cpu_rate / 3; | |
198 | break; | |
199 | case RT5350_SYSCFG0_CPUCLK_320: | |
200 | cpu_rate = 320000000; | |
201 | sys_rate = cpu_rate / 4; | |
202 | break; | |
203 | case RT5350_SYSCFG0_CPUCLK_300: | |
204 | cpu_rate = 300000000; | |
205 | sys_rate = cpu_rate / 3; | |
206 | break; | |
207 | default: | |
208 | BUG(); | |
209 | } | |
210 | uart_rate = 40000000; | |
211 | wdt_rate = sys_rate; | |
212 | } else { | |
213 | BUG(); | |
214 | } | |
215 | ||
6ac8579b JC |
216 | if (soc_is_rt3352() || soc_is_rt5350()) { |
217 | u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); | |
218 | ||
219 | if (!(val & RT3352_CLKCFG0_XTAL_SEL)) | |
220 | wmac_rate = 20000000; | |
221 | } | |
222 | ||
2809b317 JC |
223 | ralink_clk_add("cpu", cpu_rate); |
224 | ralink_clk_add("10000b00.spi", sys_rate); | |
225 | ralink_clk_add("10000100.timer", wdt_rate); | |
6ac8579b | 226 | ralink_clk_add("10000120.watchdog", wdt_rate); |
2809b317 JC |
227 | ralink_clk_add("10000500.uart", uart_rate); |
228 | ralink_clk_add("10000c00.uartlite", uart_rate); | |
6ac8579b JC |
229 | ralink_clk_add("10100000.ethernet", sys_rate); |
230 | ralink_clk_add("10180000.wmac", wmac_rate); | |
2809b317 JC |
231 | } |
232 | ||
233 | void __init ralink_of_remap(void) | |
234 | { | |
235 | rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); | |
236 | rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc"); | |
237 | ||
238 | if (!rt_sysc_membase || !rt_memc_membase) | |
239 | panic("Failed to remap core resources"); | |
240 | } | |
241 | ||
242 | void prom_soc_init(struct ralink_soc_info *soc_info) | |
243 | { | |
244 | void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); | |
245 | unsigned char *name; | |
246 | u32 n0; | |
247 | u32 n1; | |
248 | u32 id; | |
249 | ||
250 | n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); | |
251 | n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); | |
252 | ||
253 | if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { | |
254 | unsigned long icache_sets; | |
255 | ||
256 | icache_sets = (read_c0_config1() >> 22) & 7; | |
257 | if (icache_sets == 1) { | |
258 | rt305x_soc = RT305X_SOC_RT3050; | |
259 | name = "RT3050"; | |
260 | soc_info->compatible = "ralink,rt3050-soc"; | |
261 | } else { | |
262 | rt305x_soc = RT305X_SOC_RT3052; | |
263 | name = "RT3052"; | |
264 | soc_info->compatible = "ralink,rt3052-soc"; | |
265 | } | |
266 | } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { | |
267 | rt305x_soc = RT305X_SOC_RT3350; | |
268 | name = "RT3350"; | |
269 | soc_info->compatible = "ralink,rt3350-soc"; | |
270 | } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { | |
271 | rt305x_soc = RT305X_SOC_RT3352; | |
272 | name = "RT3352"; | |
273 | soc_info->compatible = "ralink,rt3352-soc"; | |
274 | } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { | |
275 | rt305x_soc = RT305X_SOC_RT5350; | |
276 | name = "RT5350"; | |
277 | soc_info->compatible = "ralink,rt5350-soc"; | |
278 | } else { | |
279 | panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); | |
280 | } | |
281 | ||
282 | id = __raw_readl(sysc + SYSC_REG_CHIP_ID); | |
283 | ||
284 | snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, | |
285 | "Ralink %s id:%u rev:%u", | |
286 | name, | |
287 | (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, | |
288 | (id & CHIP_ID_REV_MASK)); | |
dafecee8 JC |
289 | |
290 | soc_info->mem_base = RT305X_SDRAM_BASE; | |
291 | if (soc_is_rt5350()) { | |
292 | soc_info->mem_size = rt5350_get_mem_size(); | |
293 | } else if (soc_is_rt305x() || soc_is_rt3350()) { | |
294 | soc_info->mem_size_min = RT305X_MEM_SIZE_MIN; | |
295 | soc_info->mem_size_max = RT305X_MEM_SIZE_MAX; | |
296 | } else if (soc_is_rt3352()) { | |
297 | soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; | |
298 | soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; | |
299 | } | |
2809b317 | 300 | } |