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73b4390f RB |
1 | /* |
2 | * RouterBoard 500 Platform devices | |
3 | * | |
4 | * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> | |
5 | * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | #include <linux/kernel.h> | |
f9ded569 | 18 | #include <linux/export.h> |
73b4390f RB |
19 | #include <linux/init.h> |
20 | #include <linux/ctype.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/platform_device.h> | |
d4092d76 | 23 | #include <linux/mtd/rawnand.h> |
73b4390f RB |
24 | #include <linux/mtd/mtd.h> |
25 | #include <linux/mtd/partitions.h> | |
832f5dac | 26 | #include <linux/gpio.h> |
73b4390f RB |
27 | #include <linux/gpio_keys.h> |
28 | #include <linux/input.h> | |
1452fc7d | 29 | #include <linux/serial_8250.h> |
73b4390f RB |
30 | |
31 | #include <asm/bootinfo.h> | |
32 | ||
33 | #include <asm/mach-rc32434/rc32434.h> | |
34 | #include <asm/mach-rc32434/dma.h> | |
35 | #include <asm/mach-rc32434/dma_v.h> | |
36 | #include <asm/mach-rc32434/eth.h> | |
37 | #include <asm/mach-rc32434/rb.h> | |
38 | #include <asm/mach-rc32434/integ.h> | |
39 | #include <asm/mach-rc32434/gpio.h> | |
3cd4e067 | 40 | #include <asm/mach-rc32434/irq.h> |
73b4390f RB |
41 | |
42 | #define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET) | |
43 | #define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET) | |
44 | ||
1452fc7d PS |
45 | extern unsigned int idt_cpu_freq; |
46 | ||
36f2db4b PS |
47 | static struct mpmc_device dev3; |
48 | ||
49 | void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) | |
50 | { | |
51 | unsigned long flags; | |
52 | ||
53 | spin_lock_irqsave(&dev3.lock, flags); | |
54 | ||
55 | dev3.state = (dev3.state | or_mask) & ~nand_mask; | |
56 | writeb(dev3.state, dev3.base); | |
57 | ||
58 | spin_unlock_irqrestore(&dev3.lock, flags); | |
59 | } | |
60 | EXPORT_SYMBOL(set_latch_u5); | |
61 | ||
62 | unsigned char get_latch_u5(void) | |
63 | { | |
64 | return dev3.state; | |
65 | } | |
66 | EXPORT_SYMBOL(get_latch_u5); | |
67 | ||
73b4390f RB |
68 | static struct resource korina_dev0_res[] = { |
69 | { | |
70 | .name = "korina_regs", | |
71 | .start = ETH0_BASE_ADDR, | |
72 | .end = ETH0_BASE_ADDR + sizeof(struct eth_regs), | |
73 | .flags = IORESOURCE_MEM, | |
74 | }, { | |
75 | .name = "korina_rx", | |
76 | .start = ETH0_DMA_RX_IRQ, | |
77 | .end = ETH0_DMA_RX_IRQ, | |
78 | .flags = IORESOURCE_IRQ | |
79 | }, { | |
80 | .name = "korina_tx", | |
81 | .start = ETH0_DMA_TX_IRQ, | |
82 | .end = ETH0_DMA_TX_IRQ, | |
83 | .flags = IORESOURCE_IRQ | |
84 | }, { | |
85 | .name = "korina_ovr", | |
86 | .start = ETH0_RX_OVR_IRQ, | |
87 | .end = ETH0_RX_OVR_IRQ, | |
88 | .flags = IORESOURCE_IRQ | |
89 | }, { | |
90 | .name = "korina_und", | |
91 | .start = ETH0_TX_UND_IRQ, | |
92 | .end = ETH0_TX_UND_IRQ, | |
93 | .flags = IORESOURCE_IRQ | |
94 | }, { | |
95 | .name = "korina_dma_rx", | |
96 | .start = ETH0_RX_DMA_ADDR, | |
97 | .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1, | |
98 | .flags = IORESOURCE_MEM, | |
99 | }, { | |
100 | .name = "korina_dma_tx", | |
101 | .start = ETH0_TX_DMA_ADDR, | |
102 | .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1, | |
103 | .flags = IORESOURCE_MEM, | |
104 | } | |
105 | }; | |
106 | ||
107 | static struct korina_device korina_dev0_data = { | |
108 | .name = "korina0", | |
109 | .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee} | |
110 | }; | |
111 | ||
112 | static struct platform_device korina_dev0 = { | |
b6e2f58a | 113 | .id = -1, |
73b4390f | 114 | .name = "korina", |
73b4390f RB |
115 | .resource = korina_dev0_res, |
116 | .num_resources = ARRAY_SIZE(korina_dev0_res), | |
117 | }; | |
118 | ||
73b4390f RB |
119 | static struct resource cf_slot0_res[] = { |
120 | { | |
121 | .name = "cf_membase", | |
122 | .flags = IORESOURCE_MEM | |
123 | }, { | |
124 | .name = "cf_irq", | |
125 | .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */ | |
126 | .end = (8 + 4 * 32 + CF_GPIO_NUM), | |
127 | .flags = IORESOURCE_IRQ | |
128 | } | |
129 | }; | |
130 | ||
131 | static struct cf_device cf_slot0_data = { | |
3cd4e067 | 132 | .gpio_pin = CF_GPIO_NUM |
73b4390f RB |
133 | }; |
134 | ||
135 | static struct platform_device cf_slot0 = { | |
b6e2f58a | 136 | .id = -1, |
73b4390f RB |
137 | .name = "pata-rb532-cf", |
138 | .dev.platform_data = &cf_slot0_data, | |
139 | .resource = cf_slot0_res, | |
140 | .num_resources = ARRAY_SIZE(cf_slot0_res), | |
141 | }; | |
142 | ||
143 | /* Resources and device for NAND */ | |
144 | static int rb532_dev_ready(struct mtd_info *mtd) | |
145 | { | |
1b432840 | 146 | return gpio_get_value(GPIO_RDY); |
73b4390f RB |
147 | } |
148 | ||
149 | static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
150 | { | |
b1afda0e | 151 | struct nand_chip *chip = mtd_to_nand(mtd); |
73b4390f RB |
152 | unsigned char orbits, nandbits; |
153 | ||
154 | if (ctrl & NAND_CTRL_CHANGE) { | |
155 | orbits = (ctrl & NAND_CLE) << 1; | |
156 | orbits |= (ctrl & NAND_ALE) >> 1; | |
157 | ||
158 | nandbits = (~ctrl & NAND_CLE) << 1; | |
159 | nandbits |= (~ctrl & NAND_ALE) >> 1; | |
160 | ||
161 | set_latch_u5(orbits, nandbits); | |
162 | } | |
163 | if (cmd != NAND_CMD_NONE) | |
164 | writeb(cmd, chip->IO_ADDR_W); | |
165 | } | |
166 | ||
167 | static struct resource nand_slot0_res[] = { | |
168 | [0] = { | |
169 | .name = "nand_membase", | |
170 | .flags = IORESOURCE_MEM | |
171 | } | |
172 | }; | |
173 | ||
174 | static struct platform_nand_data rb532_nand_data = { | |
175 | .ctrl.dev_ready = rb532_dev_ready, | |
176 | .ctrl.cmd_ctrl = rb532_cmd_ctrl, | |
177 | }; | |
178 | ||
179 | static struct platform_device nand_slot0 = { | |
180 | .name = "gen_nand", | |
181 | .id = -1, | |
182 | .resource = nand_slot0_res, | |
183 | .num_resources = ARRAY_SIZE(nand_slot0_res), | |
184 | .dev.platform_data = &rb532_nand_data, | |
185 | }; | |
186 | ||
187 | static struct mtd_partition rb532_partition_info[] = { | |
188 | { | |
189 | .name = "Routerboard NAND boot", | |
190 | .offset = 0, | |
191 | .size = 4 * 1024 * 1024, | |
192 | }, { | |
193 | .name = "rootfs", | |
194 | .offset = MTDPART_OFS_NXTBLK, | |
195 | .size = MTDPART_SIZ_FULL, | |
196 | } | |
197 | }; | |
198 | ||
199 | static struct platform_device rb532_led = { | |
200 | .name = "rb532-led", | |
b6e2f58a | 201 | .id = -1, |
73b4390f RB |
202 | }; |
203 | ||
73b4390f | 204 | static struct platform_device rb532_button = { |
d9bdffd2 | 205 | .name = "rb532-button", |
73b4390f | 206 | .id = -1, |
73b4390f RB |
207 | }; |
208 | ||
209 | static struct resource rb532_wdt_res[] = { | |
210 | { | |
211 | .name = "rb532_wdt_res", | |
212 | .start = INTEG0_BASE_ADDR, | |
213 | .end = INTEG0_BASE_ADDR + sizeof(struct integ), | |
214 | .flags = IORESOURCE_MEM, | |
215 | } | |
216 | }; | |
217 | ||
218 | static struct platform_device rb532_wdt = { | |
70342287 RB |
219 | .name = "rc32434_wdt", |
220 | .id = -1, | |
221 | .resource = rb532_wdt_res, | |
73b4390f RB |
222 | .num_resources = ARRAY_SIZE(rb532_wdt_res), |
223 | }; | |
224 | ||
1452fc7d PS |
225 | static struct plat_serial8250_port rb532_uart_res[] = { |
226 | { | |
f98fd44b | 227 | .type = PORT_16550A, |
1452fc7d PS |
228 | .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE), |
229 | .irq = UART0_IRQ, | |
230 | .regshift = 2, | |
231 | .iotype = UPIO_MEM, | |
232 | .flags = UPF_BOOT_AUTOCONF, | |
233 | }, | |
234 | { | |
235 | .flags = 0, | |
236 | } | |
237 | }; | |
238 | ||
239 | static struct platform_device rb532_uart = { | |
70342287 RB |
240 | .name = "serial8250", |
241 | .id = PLAT8250_DEV_PLATFORM, | |
1452fc7d PS |
242 | .dev.platform_data = &rb532_uart_res, |
243 | }; | |
244 | ||
73b4390f RB |
245 | static struct platform_device *rb532_devs[] = { |
246 | &korina_dev0, | |
247 | &nand_slot0, | |
248 | &cf_slot0, | |
249 | &rb532_led, | |
250 | &rb532_button, | |
1452fc7d | 251 | &rb532_uart, |
73b4390f RB |
252 | &rb532_wdt |
253 | }; | |
254 | ||
73b4390f | 255 | /* NAND definitions */ |
70342287 | 256 | #define NAND_CHIP_DELAY 25 |
73b4390f RB |
257 | |
258 | static void __init rb532_nand_setup(void) | |
259 | { | |
260 | switch (mips_machtype) { | |
261 | case MACH_MIKROTIK_RB532A: | |
262 | set_latch_u5(LO_FOFF | LO_CEX, | |
263 | LO_ULED | LO_ALE | LO_CLE | LO_WPX); | |
264 | break; | |
265 | default: | |
266 | set_latch_u5(LO_WPX | LO_FOFF | LO_CEX, | |
267 | LO_ULED | LO_ALE | LO_CLE); | |
268 | break; | |
269 | } | |
270 | ||
271 | /* Setup NAND specific settings */ | |
272 | rb532_nand_data.chip.nr_chips = 1; | |
273 | rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info); | |
274 | rb532_nand_data.chip.partitions = rb532_partition_info; | |
275 | rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY; | |
73b4390f RB |
276 | } |
277 | ||
278 | ||
279 | static int __init plat_setup_devices(void) | |
280 | { | |
281 | /* Look for the CF card reader */ | |
1ddfe82d | 282 | if (!readl(IDT434_REG_BASE + DEV1MASK)) |
bc4c4e83 | 283 | rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */ |
73b4390f RB |
284 | else { |
285 | cf_slot0_res[0].start = | |
1ddfe82d | 286 | readl(IDT434_REG_BASE + DEV1BASE); |
73b4390f RB |
287 | cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000; |
288 | } | |
289 | ||
290 | /* Read the NAND resources from the device controller */ | |
1ddfe82d | 291 | nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE); |
73b4390f RB |
292 | nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; |
293 | ||
1c4db8e8 PS |
294 | /* Read and map device controller 3 */ |
295 | dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1); | |
36f2db4b PS |
296 | |
297 | if (!dev3.base) { | |
298 | printk(KERN_ERR "rb532: cannot remap device controller 3\n"); | |
299 | return -ENXIO; | |
300 | } | |
301 | ||
73b4390f RB |
302 | /* Initialise the NAND device */ |
303 | rb532_nand_setup(); | |
304 | ||
1452fc7d PS |
305 | /* set the uart clock to the current cpu frequency */ |
306 | rb532_uart_res[0].uartclk = idt_cpu_freq; | |
307 | ||
4e7c81af FF |
308 | dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data); |
309 | ||
73b4390f RB |
310 | return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs)); |
311 | } | |
312 | ||
313 | static int __init setup_kmac(char *s) | |
314 | { | |
315 | printk(KERN_INFO "korina mac = %s\n", s); | |
9e21c7e4 DW |
316 | if (!mac_pton(s, korina_dev0_data.mac)) { |
317 | printk(KERN_ERR "Invalid mac\n"); | |
318 | return -EINVAL; | |
319 | } | |
73b4390f RB |
320 | return 0; |
321 | } | |
322 | ||
323 | __setup("kmac=", setup_kmac); | |
324 | ||
325 | arch_initcall(plat_setup_devices); |