[mirror_ubuntu-eoan-kernel.git] / arch / mips / sgi-ip22 / ip22-mc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * ip22-mc.c: Routines for manipulating SGI Memory Controller.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
 * Copyright (C) 2003 Ladislav Michl  (ladis@linux-mips.org)
 * Copyright (C) 2004 Peter Fuerst    (pf@net.alphadv.de) - IP28
 */

#include <linux/init.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>

#include <asm/io.h>
#include <asm/bootinfo.h>
#include <asm/sgialib.h>
#include <asm/sgi/mc.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>

struct sgimc_regs *sgimc;

EXPORT_SYMBOL(sgimc);

static inline unsigned long get_bank_addr(unsigned int memconfig)
{
	return (memconfig & SGIMC_MCONFIG_BASEADDR) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22);
}

static inline unsigned long get_bank_size(unsigned int memconfig)
{
	return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
}

static inline unsigned int get_bank_config(int bank)
{
	unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
	return bank % 2 ? res & 0xffff : res >> 16;
}

struct mem {
	unsigned long addr;
	unsigned long size;
};

/*
 * Detect installed memory, do some sanity checks and notify kernel about it
 */
static void __init probe_memory(void)
{
	int i, j, found, cnt = 0;
	struct mem bank[4];
	struct mem space[2] = {{SGIMC_SEG0_BADDR, 0}, {SGIMC_SEG1_BADDR, 0}};

	printk(KERN_INFO "MC: Probing memory configuration:\n");
	for (i = 0; i < ARRAY_SIZE(bank); i++) {
		unsigned int tmp = get_bank_config(i);
		if (!(tmp & SGIMC_MCONFIG_BVALID))
			continue;

		bank[cnt].size = get_bank_size(tmp);
		bank[cnt].addr = get_bank_addr(tmp);
		printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
			i, bank[cnt].size / 1024 / 1024, bank[cnt].addr);
		cnt++;
	}

	/* And you thought bubble sort is dead algorithm... */
	do {
		unsigned long addr, size;

		found = 0;
		for (i = 1; i < cnt; i++)
			if (bank[i-1].addr > bank[i].addr) {
				addr = bank[i].addr;
				size = bank[i].size;
				bank[i].addr = bank[i-1].addr;
				bank[i].size = bank[i-1].size;
				bank[i-1].addr = addr;
				bank[i-1].size = size;
				found = 1;
			}
	} while (found);

	/* Figure out how are memory banks mapped into spaces */
	for (i = 0; i < cnt; i++) {
		found = 0;
		for (j = 0; j < ARRAY_SIZE(space) && !found; j++)
			if (space[j].addr + space[j].size == bank[i].addr) {
				space[j].size += bank[i].size;
				found = 1;
			}
		/* There is either hole or overlapping memory */
		if (!found)
			printk(KERN_CRIT "MC: Memory configuration mismatch "
					 "(%08lx), expect Bus Error soon\n",
					 bank[i].addr);
	}

	for (i = 0; i < ARRAY_SIZE(space); i++)
		if (space[i].size)
			add_memory_region(space[i].addr, space[i].size,
					  BOOT_MEM_RAM);
}

void __init sgimc_init(void)
{
	u32 tmp;

	/* ioremap can't fail */
	sgimc = (struct sgimc_regs *)
		ioremap(SGIMC_BASE, sizeof(struct sgimc_regs));

	printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
	       (int) sgimc->systemid & SGIMC_SYSID_MASKREV);

	/* Place the MC into a known state.  This must be done before
	 * interrupts are first enabled etc.
	 */

	/* Step 0: Make sure we turn off the watchdog in case it's
	 *	   still running (which might be the case after a
	 *	   soft reboot).
	 */
	tmp = sgimc->cpuctrl0;
	tmp &= ~SGIMC_CCTRL0_WDOG;
	sgimc->cpuctrl0 = tmp;

	/* Step 1: The CPU/GIO error status registers will not latch
	 *	   up a new error status until the register has been
	 *	   cleared by the cpu.	These status registers are
	 *	   cleared by writing any value to them.
	 */
	sgimc->cstat = sgimc->gstat = 0;

	/* Step 2: Enable all parity checking in cpu control register
	 *	   zero.
	 */
	/* don't touch parity settings for IP28 */
	tmp = sgimc->cpuctrl0;
#ifndef CONFIG_SGI_IP28
	tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM;
#endif
	tmp |= SGIMC_CCTRL0_R4KNOCHKPARR;
	sgimc->cpuctrl0 = tmp;

	/* Step 3: Setup the MC write buffer depth, this is controlled
	 *	   in cpu control register 1 in the lower 4 bits.
	 */
	tmp = sgimc->cpuctrl1;
	tmp &= ~0xf;
	tmp |= 0xd;
	sgimc->cpuctrl1 = tmp;

	/* Step 4: Initialize the RPSS divider register to run as fast
	 *	   as it can correctly operate.	 The register is laid
	 *	   out as follows:
	 *
	 *	   ----------------------------------------
	 *	   |  RESERVED	|   INCREMENT	| DIVIDER |
	 *	   ----------------------------------------
	 *	    31	      16 15	       8 7	 0
	 *
	 *	   DIVIDER determines how often a 'tick' happens,
	 *	   INCREMENT determines by how the RPSS increment
	 *	   registers value increases at each 'tick'. Thus,
	 *	   for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
	 */
	sgimc->divider = 0x101;

	/* Step 5: Initialize GIO64 arbitrator configuration register.
	 *
	 * NOTE: HPC init code in sgihpc_init() must run before us because
	 *	 we need to know Guiness vs. FullHouse and the board
	 *	 revision on this machine. You have been warned.
	 */

	/* First the basic invariants across all GIO64 implementations. */
	tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */
	tmp |= SGIMC_GIOPAR_HPC64;	/* All 1st HPC's interface at 64bits */
	tmp |= SGIMC_GIOPAR_ONEBUS;	/* Only one physical GIO bus exists */

	if (ip22_is_fullhouse()) {
		/* Fullhouse specific settings. */
		if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
			tmp |= SGIMC_GIOPAR_HPC264;	/* 2nd HPC at 64bits */
			tmp |= SGIMC_GIOPAR_PLINEEXP0;	/* exp0 pipelines */
			tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
			tmp |= SGIMC_GIOPAR_RTIMEEXP0;	/* exp0 is realtime */
		} else {
			tmp |= SGIMC_GIOPAR_HPC264;	/* 2nd HPC 64bits */
			tmp |= SGIMC_GIOPAR_PLINEEXP0;	/* exp[01] pipelined */
			tmp |= SGIMC_GIOPAR_PLINEEXP1;
			tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
		}
	} else {
		/* Guiness specific settings. */
		tmp |= SGIMC_GIOPAR_EISA64;	/* MC talks to EISA at 64bits */
		tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
	}
	sgimc->giopar = tmp;	/* poof */

	probe_memory();
}

void __init prom_meminit(void) {}
void __init prom_free_prom_memory(void)
{
#ifdef CONFIG_SGI_IP28
	u32 mconfig1;
	unsigned long flags;
	spinlock_t lock;

	/*
	 * because ARCS accesses memory uncached we wait until ARCS
	 * isn't needed any longer, before we switch from slow to
	 * normal mode
	 */
	spin_lock_irqsave(&lock, flags);
	mconfig1 = sgimc->mconfig1;
	/* map ECC register */
	sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060;
	iob();
	/* switch to normal mode */
	*(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;
	iob();
	/* reduce WR_COL */
	sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4;
	iob();
	/* restore old config */
	sgimc->mconfig1 = mconfig1;
	iob();
	spin_unlock_irqrestore(&lock, flags);
#endif
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* ip22-mc.c: Routines for manipulating SGI Memory Controller.
	4	*
79add627	5	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
1da177e4 LT	6	* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
1da177e4 LT	7	* Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
e2defae5	8	* Copyright (C) 2004 Peter Fuerst (pf@net.alphadv.de) - IP28
1da177e4 LT	9	*/
	10
	11	#include <linux/init.h>
26dd3e4f	12	#include <linux/export.h>
1da177e4	13	#include <linux/kernel.h>
26dd3e4f	14	#include <linux/spinlock.h>
1da177e4 LT	15
	16	#include <asm/io.h>
	17	#include <asm/bootinfo.h>
	18	#include <asm/sgialib.h>
	19	#include <asm/sgi/mc.h>
	20	#include <asm/sgi/hpc3.h>
	21	#include <asm/sgi/ip22.h>
	22
	23	struct sgimc_regs *sgimc;
	24
	25	EXPORT_SYMBOL(sgimc);
	26
	27	static inline unsigned long get_bank_addr(unsigned int memconfig)
	28	{
635c9907	29	return (memconfig & SGIMC_MCONFIG_BASEADDR) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22);
1da177e4 LT	30	}
	31
	32	static inline unsigned long get_bank_size(unsigned int memconfig)
	33	{
635c9907	34	return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
1da177e4 LT	35	}
	36
	37	static inline unsigned int get_bank_config(int bank)
	38	{
	39	unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
	40	return bank % 2 ? res & 0xffff : res >> 16;
	41	}
	42
	43	struct mem {
	44	unsigned long addr;
	45	unsigned long size;
	46	};
	47
	48	/*
	49	* Detect installed memory, do some sanity checks and notify kernel about it
	50	*/
5bd080f7	51	static void __init probe_memory(void)
1da177e4 LT	52	{
	53	int i, j, found, cnt = 0;
	54	struct mem bank[4];
	55	struct mem space[2] = {{SGIMC_SEG0_BADDR, 0}, {SGIMC_SEG1_BADDR, 0}};
	56
	57	printk(KERN_INFO "MC: Probing memory configuration:\n");
	58	for (i = 0; i < ARRAY_SIZE(bank); i++) {
	59	unsigned int tmp = get_bank_config(i);
	60	if (!(tmp & SGIMC_MCONFIG_BVALID))
	61	continue;
	62
	63	bank[cnt].size = get_bank_size(tmp);
	64	bank[cnt].addr = get_bank_addr(tmp);
	65	printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
	66	i, bank[cnt].size / 1024 / 1024, bank[cnt].addr);
	67	cnt++;
	68	}
	69
	70	/* And you thought bubble sort is dead algorithm... */
	71	do {
	72	unsigned long addr, size;
	73
	74	found = 0;
	75	for (i = 1; i < cnt; i++)
	76	if (bank[i-1].addr > bank[i].addr) {
	77	addr = bank[i].addr;
	78	size = bank[i].size;
	79	bank[i].addr = bank[i-1].addr;
	80	bank[i].size = bank[i-1].size;
	81	bank[i-1].addr = addr;
	82	bank[i-1].size = size;
	83	found = 1;
	84	}
	85	} while (found);
	86
	87	/* Figure out how are memory banks mapped into spaces */
	88	for (i = 0; i < cnt; i++) {
	89	found = 0;
	90	for (j = 0; j < ARRAY_SIZE(space) && !found; j++)
	91	if (space[j].addr + space[j].size == bank[i].addr) {
	92	space[j].size += bank[i].size;
	93	found = 1;
	94	}
	95	/* There is either hole or overlapping memory */
	96	if (!found)
	97	printk(KERN_CRIT "MC: Memory configuration mismatch "
	98	"(%08lx), expect Bus Error soon\n",
	99	bank[i].addr);
	100	}
	101
	102	for (i = 0; i < ARRAY_SIZE(space); i++)
	103	if (space[i].size)
	104	add_memory_region(space[i].addr, space[i].size,
	105	BOOT_MEM_RAM);
	106	}
	107
	108	void __init sgimc_init(void)
	109	{
	110	u32 tmp;
	111
	112	/* ioremap can't fail */
	113	sgimc = (struct sgimc_regs *)
	114	ioremap(SGIMC_BASE, sizeof(struct sgimc_regs));
	115
116	printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
117	(int) sgimc->systemid & SGIMC_SYSID_MASKREV);
118
119	/* Place the MC into a known state. This must be done before
120	* interrupts are first enabled etc.
121	*/
122
123	/* Step 0: Make sure we turn off the watchdog in case it's
70342287 RB	124	* still running (which might be the case after a
70342287 RB	125	* soft reboot).
1da177e4 LT	126	*/
	127	tmp = sgimc->cpuctrl0;
	128	tmp &= ~SGIMC_CCTRL0_WDOG;
	129	sgimc->cpuctrl0 = tmp;
	130
	131	/* Step 1: The CPU/GIO error status registers will not latch
70342287 RB	132	* up a new error status until the register has been
	133	* cleared by the cpu. These status registers are
	134	* cleared by writing any value to them.
1da177e4 LT	135	*/
	136	sgimc->cstat = sgimc->gstat = 0;
	137
	138	/* Step 2: Enable all parity checking in cpu control register
70342287	139	* zero.
1da177e4	140	*/
e2defae5	141	/* don't touch parity settings for IP28 */
1da177e4	142	tmp = sgimc->cpuctrl0;
e84de0c6 TB	143	#ifndef CONFIG_SGI_IP28
e84de0c6 TB	144	tmp \|= SGIMC_CCTRL0_EPERRGIO \| SGIMC_CCTRL0_EPERRMEM;
e2defae5	145	#endif
e84de0c6	146	tmp \|= SGIMC_CCTRL0_R4KNOCHKPARR;
1da177e4 LT	147	sgimc->cpuctrl0 = tmp;
	148
	149	/* Step 3: Setup the MC write buffer depth, this is controlled
70342287	150	* in cpu control register 1 in the lower 4 bits.
1da177e4 LT	151	*/
	152	tmp = sgimc->cpuctrl1;
	153	tmp &= ~0xf;
	154	tmp \|= 0xd;
	155	sgimc->cpuctrl1 = tmp;
	156
	157	/* Step 4: Initialize the RPSS divider register to run as fast
70342287 RB	158	* as it can correctly operate. The register is laid
70342287 RB	159	* out as follows:
1da177e4	160	*
70342287 RB	161	* ----------------------------------------
	162	* \| RESERVED \| INCREMENT \| DIVIDER \|
	163	* ----------------------------------------
	164	* 31 16 15 8 7 0
1da177e4	165	*
70342287 RB	166	* DIVIDER determines how often a 'tick' happens,
	167	* INCREMENT determines by how the RPSS increment
	168	* registers value increases at each 'tick'. Thus,
	169	* for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
1da177e4 LT	170	*/
	171	sgimc->divider = 0x101;
	172
	173	/* Step 5: Initialize GIO64 arbitrator configuration register.
	174	*
	175	* NOTE: HPC init code in sgihpc_init() must run before us because
70342287 RB	176	* we need to know Guiness vs. FullHouse and the board
70342287 RB	177	* revision on this machine. You have been warned.
1da177e4 LT	178	*/
	179
	180	/* First the basic invariants across all GIO64 implementations. */
e84de0c6 TB	181	tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */
e84de0c6 TB	182	tmp \|= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */
1da177e4 LT	183	tmp \|= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */
	184
	185	if (ip22_is_fullhouse()) {
	186	/* Fullhouse specific settings. */
	187	if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
	188	tmp \|= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */
	189	tmp \|= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */
70342287	190	tmp \|= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
1da177e4 LT	191	tmp \|= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */
	192	} else {
	193	tmp \|= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */
	194	tmp \|= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */
	195	tmp \|= SGIMC_GIOPAR_PLINEEXP1;
70342287	196	tmp \|= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
1da177e4 LT	197	}
	198	} else {
	199	/* Guiness specific settings. */
	200	tmp \|= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */
70342287	201	tmp \|= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
1da177e4 LT	202	}
	203	sgimc->giopar = tmp; /* poof */
	204
	205	probe_memory();
	206	}
	207
	208	void __init prom_meminit(void) {}
c44e8d5e	209	void __init prom_free_prom_memory(void)
1da177e4	210	{
7a2852e4 TB	211	#ifdef CONFIG_SGI_IP28
	212	u32 mconfig1;
	213	unsigned long flags;
	214	spinlock_t lock;
	215
	216	/*
	217	* because ARCS accesses memory uncached we wait until ARCS
	218	* isn't needed any longer, before we switch from slow to
	219	* normal mode
	220	*/
	221	spin_lock_irqsave(&lock, flags);
	222	mconfig1 = sgimc->mconfig1;
	223	/* map ECC register */
	224	sgimc->mconfig1 = (mconfig1 & 0xffff0000) \| 0x2060;
	225	iob();
	226	/* switch to normal mode */
	227	(unsigned long )PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;
	228	iob();
	229	/* reduce WR_COL */
	230	sgimc->cmacc = (sgimc->cmacc & ~0xf) \| 4;
	231	iob();
	232	/* restore old config */
	233	sgimc->mconfig1 = mconfig1;
	234	iob();
	235	spin_unlock_irqrestore(&lock, flags);
	236	#endif
1da177e4	237	}