[mirror_ubuntu-focal-kernel.git] / arch / mips / sgi-ip27 / ip27-nmi.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/kernel.h>
#include <linux/mmzone.h>
#include <linux/nodemask.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/atomic.h>
#include <asm/sn/types.h>
#include <asm/sn/addrs.h>
#include <asm/sn/nmi.h>
#include <asm/sn/arch.h>
#include <asm/sn/sn0/hub.h>

#if 0
#define NODE_NUM_CPUS(n)	CNODE_NUM_CPUS(n)
#else
#define NODE_NUM_CPUS(n)	CPUS_PER_NODE
#endif

#define CNODEID_NONE (cnodeid_t)-1

typedef unsigned long machreg_t;

static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;

/*
 * Let's see what else we need to do here. Set up sp, gp?
 */
void nmi_dump(void)
{
	void cont_nmi_dump(void);

	cont_nmi_dump();
}

void install_cpu_nmi_handler(int slice)
{
	nmi_t *nmi_addr;

	nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice);
	if (nmi_addr->call_addr)
		return;
	nmi_addr->magic = NMI_MAGIC;
	nmi_addr->call_addr = (void *)nmi_dump;
	nmi_addr->call_addr_c =
		(void *)(~((unsigned long)(nmi_addr->call_addr)));
	nmi_addr->call_parm = 0;
}

/*
 * Copy the cpu registers which have been saved in the IP27prom format
 * into the eframe format for the node under consideration.
 */

void nmi_cpu_eframe_save(nasid_t nasid, int slice)
{
	struct reg_struct *nr;
	int		i;

	/* Get the pointer to the current cpu's register set. */
	nr = (struct reg_struct *)
		(TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) +
		slice * IP27_NMI_KREGS_CPU_SIZE);

	pr_emerg("NMI nasid %d: slice %d\n", nasid, slice);

	/*
	 * Saved main processor registers
	 */
	for (i = 0; i < 32; ) {
		if ((i % 4) == 0)
			pr_emerg("$%2d   :", i);
		pr_cont(" %016lx", nr->gpr[i]);

		i++;
		if ((i % 4) == 0)
			pr_cont("\n");
	}

	pr_emerg("Hi    : (value lost)\n");
	pr_emerg("Lo    : (value lost)\n");

	/*
	 * Saved cp0 registers
	 */
	pr_emerg("epc   : %016lx %pS\n", nr->epc, (void *)nr->epc);
	pr_emerg("%s\n", print_tainted());
	pr_emerg("ErrEPC: %016lx %pS\n", nr->error_epc, (void *)nr->error_epc);
	pr_emerg("ra    : %016lx %pS\n", nr->gpr[31], (void *)nr->gpr[31]);
	pr_emerg("Status: %08lx	      ", nr->sr);

	if (nr->sr & ST0_KX)
		pr_cont("KX ");
	if (nr->sr & ST0_SX)
		pr_cont("SX ");
	if (nr->sr & ST0_UX)
		pr_cont("UX ");

	switch (nr->sr & ST0_KSU) {
	case KSU_USER:
		pr_cont("USER ");
		break;
	case KSU_SUPERVISOR:
		pr_cont("SUPERVISOR ");
		break;
	case KSU_KERNEL:
		pr_cont("KERNEL ");
		break;
	default:
		pr_cont("BAD_MODE ");
		break;
	}

	if (nr->sr & ST0_ERL)
		pr_cont("ERL ");
	if (nr->sr & ST0_EXL)
		pr_cont("EXL ");
	if (nr->sr & ST0_IE)
		pr_cont("IE ");
	pr_cont("\n");

	pr_emerg("Cause : %08lx\n", nr->cause);
	pr_emerg("PrId  : %08x\n", read_c0_prid());
	pr_emerg("BadVA : %016lx\n", nr->badva);
	pr_emerg("CErr  : %016lx\n", nr->cache_err);
	pr_emerg("NMI_SR: %016lx\n", nr->nmi_sr);

	pr_emerg("\n");
}

void nmi_dump_hub_irq(nasid_t nasid, int slice)
{
	u64 mask0, mask1, pend0, pend1;

	if (slice == 0) {				/* Slice A */
		mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A);
		mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A);
	} else {					/* Slice B */
		mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B);
		mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B);
	}

	pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
	pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);

	pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1);
	pr_emerg("PI_INT_PEND0: %16llx PI_INT_PEND1: %16llx\n", pend0, pend1);
	pr_emerg("\n\n");
}

/*
 * Copy the cpu registers which have been saved in the IP27prom format
 * into the eframe format for the node under consideration.
 */
void nmi_node_eframe_save(cnodeid_t  cnode)
{
	nasid_t nasid;
	int slice;

	/* Make sure that we have a valid node */
	if (cnode == CNODEID_NONE)
		return;

	nasid = COMPACT_TO_NASID_NODEID(cnode);
	if (nasid == INVALID_NASID)
		return;

	/* Save the registers into eframe for each cpu */
	for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) {
		nmi_cpu_eframe_save(nasid, slice);
		nmi_dump_hub_irq(nasid, slice);
	}
}

/*
 * Save the nmi cpu registers for all cpus in the system.
 */
void
nmi_eframes_save(void)
{
	cnodeid_t	cnode;

	for_each_online_node(cnode)
		nmi_node_eframe_save(cnode);
}

void
cont_nmi_dump(void)
{
#ifndef REAL_NMI_SIGNAL
	static atomic_t nmied_cpus = ATOMIC_INIT(0);

	atomic_inc(&nmied_cpus);
#endif
	/*
	 * Only allow 1 cpu to proceed
	 */
	arch_spin_lock(&nmi_lock);

#ifdef REAL_NMI_SIGNAL
	/*
	 * Wait up to 15 seconds for the other cpus to respond to the NMI.
	 * If a cpu has not responded after 10 sec, send it 1 additional NMI.
	 * This is for 2 reasons:
	 *	- sometimes a MMSC fail to NMI all cpus.
	 *	- on 512p SN0 system, the MMSC will only send NMIs to
	 *	  half the cpus. Unfortunately, we don't know which cpus may be
	 *	  NMIed - it depends on how the site chooses to configure.
	 *
	 * Note: it has been measure that it takes the MMSC up to 2.3 secs to
	 * send NMIs to all cpus on a 256p system.
	 */
	for (i=0; i < 1500; i++) {
		for_each_online_node(node)
			if (NODEPDA(node)->dump_count == 0)
				break;
		if (node == MAX_NUMNODES)
			break;
		if (i == 1000) {
			for_each_online_node(node)
				if (NODEPDA(node)->dump_count == 0) {
					cpu = cpumask_first(cpumask_of_node(node));
					for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) {
						CPUMASK_SETB(nmied_cpus, cpu);
						/*
						 * cputonasid, cputoslice
						 * needs kernel cpuid
						 */
						SEND_NMI((cputonasid(cpu)), (cputoslice(cpu)));
					}
				}

		}
		udelay(10000);
	}
#else
	while (atomic_read(&nmied_cpus) != num_online_cpus());
#endif

	/*
	 * Save the nmi cpu registers for all cpu in the eframe format.
	 */
	nmi_eframes_save();
	LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	#include <linux/kernel.h>
	3	#include <linux/mmzone.h>
	4	#include <linux/nodemask.h>
	5	#include <linux/spinlock.h>
	6	#include <linux/smp.h>
60063497	7	#include <linux/atomic.h>
1da177e4 LT	8	#include <asm/sn/types.h>
	9	#include <asm/sn/addrs.h>
	10	#include <asm/sn/nmi.h>
	11	#include <asm/sn/arch.h>
	12	#include <asm/sn/sn0/hub.h>
	13
	14	#if 0
	15	#define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n)
	16	#else
	17	#define NODE_NUM_CPUS(n) CPUS_PER_NODE
	18	#endif
	19
	20	#define CNODEID_NONE (cnodeid_t)-1
1da177e4 LT	21
	22	typedef unsigned long machreg_t;
	23
598c5aba	24	static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;
1da177e4 LT	25
1da177e4 LT	26	/*
4939788e	27	* Let's see what else we need to do here. Set up sp, gp?
1da177e4 LT	28	*/
	29	void nmi_dump(void)
	30	{
	31	void cont_nmi_dump(void);
	32
	33	cont_nmi_dump();
	34	}
	35
	36	void install_cpu_nmi_handler(int slice)
	37	{
	38	nmi_t *nmi_addr;
	39
	40	nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice);
	41	if (nmi_addr->call_addr)
	42	return;
	43	nmi_addr->magic = NMI_MAGIC;
	44	nmi_addr->call_addr = (void *)nmi_dump;
	45	nmi_addr->call_addr_c =
	46	(void *)(~((unsigned long)(nmi_addr->call_addr)));
	47	nmi_addr->call_parm = 0;
	48	}
	49
	50	/*
	51	* Copy the cpu registers which have been saved in the IP27prom format
	52	* into the eframe format for the node under consideration.
	53	*/
	54
	55	void nmi_cpu_eframe_save(nasid_t nasid, int slice)
	56	{
	57	struct reg_struct *nr;
70342287	58	int i;
1da177e4 LT	59
	60	/* Get the pointer to the current cpu's register set. */
	61	nr = (struct reg_struct *)
	62	(TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) +
	63	slice * IP27_NMI_KREGS_CPU_SIZE);
	64
ab68280e	65	pr_emerg("NMI nasid %d: slice %d\n", nasid, slice);
1da177e4 LT	66
	67	/*
	68	* Saved main processor registers
	69	*/
	70	for (i = 0; i < 32; ) {
	71	if ((i % 4) == 0)
ab68280e TB	72	pr_emerg("$%2d :", i);
ab68280e TB	73	pr_cont(" %016lx", nr->gpr[i]);
1da177e4 LT	74
	75	i++;
	76	if ((i % 4) == 0)
ab68280e	77	pr_cont("\n");
1da177e4 LT	78	}
1da177e4 LT	79
ab68280e TB	80	pr_emerg("Hi : (value lost)\n");
ab68280e TB	81	pr_emerg("Lo : (value lost)\n");
1da177e4 LT	82
	83	/*
	84	* Saved cp0 registers
	85	*/
ab68280e TB	86	pr_emerg("epc : %016lx %pS\n", nr->epc, (void *)nr->epc);
	87	pr_emerg("%s\n", print_tainted());
	88	pr_emerg("ErrEPC: %016lx %pS\n", nr->error_epc, (void *)nr->error_epc);
	89	pr_emerg("ra : %016lx %pS\n", nr->gpr[31], (void *)nr->gpr[31]);
	90	pr_emerg("Status: %08lx ", nr->sr);
1da177e4 LT	91
1da177e4 LT	92	if (nr->sr & ST0_KX)
ab68280e	93	pr_cont("KX ");
1da177e4	94	if (nr->sr & ST0_SX)
ab68280e	95	pr_cont("SX ");
1da177e4	96	if (nr->sr & ST0_UX)
ab68280e	97	pr_cont("UX ");
1da177e4 LT	98
	99	switch (nr->sr & ST0_KSU) {
	100	case KSU_USER:
ab68280e	101	pr_cont("USER ");
1da177e4 LT	102	break;
1da177e4 LT	103	case KSU_SUPERVISOR:
ab68280e	104	pr_cont("SUPERVISOR ");
1da177e4 LT	105	break;
1da177e4 LT	106	case KSU_KERNEL:
ab68280e	107	pr_cont("KERNEL ");
1da177e4 LT	108	break;
1da177e4 LT	109	default:
ab68280e	110	pr_cont("BAD_MODE ");
1da177e4 LT	111	break;
	112	}
	113
	114	if (nr->sr & ST0_ERL)
ab68280e	115	pr_cont("ERL ");
1da177e4	116	if (nr->sr & ST0_EXL)
ab68280e	117	pr_cont("EXL ");
1da177e4	118	if (nr->sr & ST0_IE)
ab68280e TB	119	pr_cont("IE ");
ab68280e TB	120	pr_cont("\n");
1da177e4	121
ab68280e TB	122	pr_emerg("Cause : %08lx\n", nr->cause);
	123	pr_emerg("PrId : %08x\n", read_c0_prid());
	124	pr_emerg("BadVA : %016lx\n", nr->badva);
	125	pr_emerg("CErr : %016lx\n", nr->cache_err);
	126	pr_emerg("NMI_SR: %016lx\n", nr->nmi_sr);
1da177e4	127
ab68280e	128	pr_emerg("\n");
1da177e4 LT	129	}
	130
	131	void nmi_dump_hub_irq(nasid_t nasid, int slice)
	132	{
db0e7d4e	133	u64 mask0, mask1, pend0, pend1;
1da177e4 LT	134
	135	if (slice == 0) { /* Slice A */
	136	mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A);
	137	mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A);
	138	} else { /* Slice B */
	139	mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B);
	140	mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B);
	141	}
	142
	143	pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
	144	pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);
	145
ab68280e TB	146	pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1);
	147	pr_emerg("PI_INT_PEND0: %16llx PI_INT_PEND1: %16llx\n", pend0, pend1);
	148	pr_emerg("\n\n");
1da177e4 LT	149	}
	150
	151	/*
	152	* Copy the cpu registers which have been saved in the IP27prom format
	153	* into the eframe format for the node under consideration.
	154	*/
	155	void nmi_node_eframe_save(cnodeid_t cnode)
	156	{
	157	nasid_t nasid;
	158	int slice;
	159
	160	/* Make sure that we have a valid node */
	161	if (cnode == CNODEID_NONE)
	162	return;
	163
	164	nasid = COMPACT_TO_NASID_NODEID(cnode);
	165	if (nasid == INVALID_NASID)
	166	return;
	167
	168	/* Save the registers into eframe for each cpu */
	169	for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) {
	170	nmi_cpu_eframe_save(nasid, slice);
	171	nmi_dump_hub_irq(nasid, slice);
	172	}
	173	}
	174
	175	/*
	176	* Save the nmi cpu registers for all cpus in the system.
	177	*/
	178	void
	179	nmi_eframes_save(void)
	180	{
	181	cnodeid_t cnode;
	182
	183	for_each_online_node(cnode)
	184	nmi_node_eframe_save(cnode);
	185	}
	186
	187	void
	188	cont_nmi_dump(void)
	189	{
	190	#ifndef REAL_NMI_SIGNAL
	191	static atomic_t nmied_cpus = ATOMIC_INIT(0);
	192
	193	atomic_inc(&nmied_cpus);
	194	#endif
	195	/*
2ba53e37	196	* Only allow 1 cpu to proceed
1da177e4	197	*/
598c5aba	198	arch_spin_lock(&nmi_lock);
1da177e4 LT	199
	200	#ifdef REAL_NMI_SIGNAL
	201	/*
	202	* Wait up to 15 seconds for the other cpus to respond to the NMI.
	203	* If a cpu has not responded after 10 sec, send it 1 additional NMI.
	204	* This is for 2 reasons:
	205	* - sometimes a MMSC fail to NMI all cpus.
	206	* - on 512p SN0 system, the MMSC will only send NMIs to
	207	* half the cpus. Unfortunately, we don't know which cpus may be
	208	* NMIed - it depends on how the site chooses to configure.
	209	*
	210	* Note: it has been measure that it takes the MMSC up to 2.3 secs to
	211	* send NMIs to all cpus on a 256p system.
	212	*/
	213	for (i=0; i < 1500; i++) {
	214	for_each_online_node(node)
	215	if (NODEPDA(node)->dump_count == 0)
	216	break;
	217	if (node == MAX_NUMNODES)
	218	break;
	219	if (i == 1000) {
	220	for_each_online_node(node)
	221	if (NODEPDA(node)->dump_count == 0) {
0451fb2e	222	cpu = cpumask_first(cpumask_of_node(node));
1da177e4 LT	223	for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) {
	224	CPUMASK_SETB(nmied_cpus, cpu);
	225	/*
	226	* cputonasid, cputoslice
	227	* needs kernel cpuid
	228	*/
	229	SEND_NMI((cputonasid(cpu)), (cputoslice(cpu)));
	230	}
	231	}
	232
	233	}
	234	udelay(10000);
	235	}
	236	#else
	237	while (atomic_read(&nmied_cpus) != num_online_cpus());
	238	#endif
	239
	240	/*
	241	* Save the nmi cpu registers for all cpu in the eframe format.
	242	*/
	243	nmi_eframes_save();
	244	LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET \| NPR_LOCALRESET);
	245	}