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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * This program is free software; you can redistribute it and/or |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
bb9b813b RB |
15 | * |
16 | * Copyright (C) 2001, 2002, 2003 Broadcom Corporation | |
17 | * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org> | |
18 | * Copyright (C) 2007 MIPS Technologies, Inc. | |
19 | * written by Ralf Baechle <ralf@linux-mips.org> | |
1da177e4 LT |
20 | */ |
21 | ||
bb9b813b | 22 | #undef DEBUG |
1da177e4 | 23 | |
bb9b813b | 24 | #include <linux/device.h> |
1da177e4 LT |
25 | #include <linux/module.h> |
26 | #include <linux/kernel.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/vmalloc.h> | |
32 | #include <linux/fs.h> | |
33 | #include <linux/errno.h> | |
bb9b813b | 34 | #include <linux/types.h> |
db89a48c | 35 | #include <linux/wait.h> |
bb9b813b | 36 | |
1da177e4 LT |
37 | #include <asm/io.h> |
38 | #include <asm/sibyte/sb1250.h> | |
39 | #include <asm/sibyte/sb1250_regs.h> | |
40 | #include <asm/sibyte/sb1250_scd.h> | |
41 | #include <asm/sibyte/sb1250_int.h> | |
bb9b813b RB |
42 | #include <asm/system.h> |
43 | #include <asm/uaccess.h> | |
1da177e4 | 44 | |
bb9b813b RB |
45 | #define SBPROF_TB_MAJOR 240 |
46 | ||
47 | typedef u64 tb_sample_t[6*256]; | |
48 | ||
49 | enum open_status { | |
50 | SB_CLOSED, | |
51 | SB_OPENING, | |
52 | SB_OPEN | |
53 | }; | |
54 | ||
55 | struct sbprof_tb { | |
56 | wait_queue_head_t tb_sync; | |
57 | wait_queue_head_t tb_read; | |
58 | struct mutex lock; | |
59 | enum open_status open; | |
60 | tb_sample_t *sbprof_tbbuf; | |
61 | int next_tb_sample; | |
62 | ||
63 | volatile int tb_enable; | |
64 | volatile int tb_armed; | |
65 | ||
66 | }; | |
1da177e4 LT |
67 | |
68 | static struct sbprof_tb sbp; | |
69 | ||
bb9b813b RB |
70 | #define MAX_SAMPLE_BYTES (24*1024*1024) |
71 | #define MAX_TBSAMPLE_BYTES (12*1024*1024) | |
72 | ||
73 | #define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t)) | |
74 | #define TB_SAMPLE_SIZE (sizeof(tb_sample_t)) | |
75 | #define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE) | |
76 | ||
77 | /* ioctls */ | |
78 | #define SBPROF_ZBSTART _IOW('s', 0, int) | |
79 | #define SBPROF_ZBSTOP _IOW('s', 1, int) | |
80 | #define SBPROF_ZBWAITFULL _IOW('s', 2, int) | |
81 | ||
82 | /* | |
83 | * Routines for using 40-bit SCD cycle counter | |
84 | * | |
85 | * Client responsible for either handling interrupts or making sure | |
86 | * the cycles counter never saturates, e.g., by doing | |
87 | * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs. | |
88 | */ | |
89 | ||
90 | /* | |
91 | * Configures SCD counter 0 to count ZCLKs starting from val; | |
92 | * Configures SCD counters1,2,3 to count nothing. | |
93 | * Must not be called while gathering ZBbus profiles. | |
94 | */ | |
95 | ||
96 | #define zclk_timer_init(val) \ | |
97 | __asm__ __volatile__ (".set push;" \ | |
98 | ".set mips64;" \ | |
99 | "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \ | |
100 | "sd %0, 0x10($8);" /* write val to counter0 */ \ | |
101 | "sd %1, 0($8);" /* config counter0 for zclks*/ \ | |
102 | ".set pop" \ | |
103 | : /* no outputs */ \ | |
104 | /* enable, counter0 */ \ | |
105 | : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \ | |
106 | : /* modifies */ "$8" ) | |
107 | ||
108 | ||
109 | /* Reads SCD counter 0 and puts result in value | |
110 | unsigned long long val; */ | |
111 | #define zclk_get(val) \ | |
112 | __asm__ __volatile__ (".set push;" \ | |
113 | ".set mips64;" \ | |
114 | "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \ | |
115 | "ld %0, 0x10($8);" /* write val to counter0 */ \ | |
116 | ".set pop" \ | |
117 | : /* outputs */ "=r"(val) \ | |
118 | : /* inputs */ \ | |
119 | : /* modifies */ "$8" ) | |
120 | ||
121 | #define DEVNAME "bcm1250_tbprof" | |
122 | ||
1da177e4 LT |
123 | #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES) |
124 | ||
bb9b813b | 125 | /* |
1da177e4 LT |
126 | * Support for ZBbus sampling using the trace buffer |
127 | * | |
128 | * We use the SCD performance counter interrupt, caused by a Zclk counter | |
129 | * overflow, to trigger the start of tracing. | |
130 | * | |
131 | * We set the trace buffer to sample everything and freeze on | |
132 | * overflow. | |
133 | * | |
134 | * We map the interrupt for trace_buffer_freeze to handle it on CPU 0. | |
bb9b813b | 135 | */ |
1da177e4 | 136 | |
bb9b813b | 137 | static u64 tb_period; |
1da177e4 LT |
138 | |
139 | static void arm_tb(void) | |
140 | { | |
bb9b813b RB |
141 | u64 scdperfcnt; |
142 | u64 next = (1ULL << 40) - tb_period; | |
143 | u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; | |
144 | ||
145 | /* | |
146 | * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to trigger | |
147 | *start of trace. XXX vary sampling period | |
148 | */ | |
65bda1a9 MR |
149 | __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); |
150 | scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); | |
bb9b813b RB |
151 | |
152 | /* | |
153 | * Unfortunately, in Pass 2 we must clear all counters to knock down a | |
154 | * previous interrupt request. This means that bus profiling requires | |
155 | * ALL of the SCD perf counters. | |
156 | */ | |
65bda1a9 | 157 | __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | |
bb9b813b RB |
158 | /* keep counters 0,2,3 as is */ |
159 | M_SPC_CFG_ENABLE | /* enable counting */ | |
160 | M_SPC_CFG_CLEAR | /* clear all counters */ | |
161 | V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */ | |
65bda1a9 MR |
162 | IOADDR(A_SCD_PERF_CNT_CFG)); |
163 | __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); | |
bb9b813b | 164 | |
1da177e4 | 165 | /* Reset the trace buffer */ |
65bda1a9 | 166 | __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); |
1da177e4 LT |
167 | #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT) |
168 | /* XXXKW may want to expose control to the data-collector */ | |
169 | tb_options |= M_SCD_TRACE_CFG_FORCECNT; | |
170 | #endif | |
65bda1a9 | 171 | __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); |
1da177e4 LT |
172 | sbp.tb_armed = 1; |
173 | } | |
174 | ||
36d98e79 | 175 | static irqreturn_t sbprof_tb_intr(int irq, void *dev_id) |
1da177e4 LT |
176 | { |
177 | int i; | |
bb9b813b RB |
178 | |
179 | pr_debug(DEVNAME ": tb_intr\n"); | |
180 | ||
1da177e4 LT |
181 | if (sbp.next_tb_sample < MAX_TB_SAMPLES) { |
182 | /* XXX should use XKPHYS to make writes bypass L2 */ | |
bb9b813b | 183 | u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; |
1da177e4 | 184 | /* Read out trace */ |
65bda1a9 MR |
185 | __raw_writeq(M_SCD_TRACE_CFG_START_READ, |
186 | IOADDR(A_SCD_TRACE_CFG)); | |
1da177e4 LT |
187 | __asm__ __volatile__ ("sync" : : : "memory"); |
188 | /* Loop runs backwards because bundles are read out in reverse order */ | |
189 | for (i = 256 * 6; i > 0; i -= 6) { | |
bb9b813b RB |
190 | /* Subscripts decrease to put bundle in the order */ |
191 | /* t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */ | |
65bda1a9 | 192 | p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); |
bb9b813b | 193 | /* read t2 hi */ |
65bda1a9 | 194 | p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); |
bb9b813b | 195 | /* read t2 lo */ |
65bda1a9 | 196 | p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); |
bb9b813b | 197 | /* read t1 hi */ |
65bda1a9 | 198 | p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); |
bb9b813b | 199 | /* read t1 lo */ |
65bda1a9 | 200 | p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); |
bb9b813b | 201 | /* read t0 hi */ |
65bda1a9 | 202 | p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); |
bb9b813b | 203 | /* read t0 lo */ |
1da177e4 LT |
204 | } |
205 | if (!sbp.tb_enable) { | |
bb9b813b | 206 | pr_debug(DEVNAME ": tb_intr shutdown\n"); |
65bda1a9 MR |
207 | __raw_writeq(M_SCD_TRACE_CFG_RESET, |
208 | IOADDR(A_SCD_TRACE_CFG)); | |
1da177e4 LT |
209 | sbp.tb_armed = 0; |
210 | wake_up(&sbp.tb_sync); | |
211 | } else { | |
bb9b813b | 212 | arm_tb(); /* knock down current interrupt and get another one later */ |
1da177e4 LT |
213 | } |
214 | } else { | |
215 | /* No more trace buffer samples */ | |
bb9b813b | 216 | pr_debug(DEVNAME ": tb_intr full\n"); |
65bda1a9 | 217 | __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); |
1da177e4 LT |
218 | sbp.tb_armed = 0; |
219 | if (!sbp.tb_enable) { | |
220 | wake_up(&sbp.tb_sync); | |
221 | } | |
222 | wake_up(&sbp.tb_read); | |
223 | } | |
bb9b813b | 224 | |
1da177e4 LT |
225 | return IRQ_HANDLED; |
226 | } | |
227 | ||
36d98e79 | 228 | static irqreturn_t sbprof_pc_intr(int irq, void *dev_id) |
1da177e4 LT |
229 | { |
230 | printk(DEVNAME ": unexpected pc_intr"); | |
231 | return IRQ_NONE; | |
232 | } | |
233 | ||
bb9b813b RB |
234 | /* |
235 | * Requires: Already called zclk_timer_init with a value that won't | |
236 | * saturate 40 bits. No subsequent use of SCD performance counters | |
237 | * or trace buffer. | |
238 | */ | |
239 | ||
240 | static int sbprof_zbprof_start(struct file *filp) | |
1da177e4 | 241 | { |
bb9b813b RB |
242 | u64 scdperfcnt; |
243 | int err; | |
1da177e4 | 244 | |
bb9b813b | 245 | if (xchg(&sbp.tb_enable, 1)) |
1da177e4 LT |
246 | return -EBUSY; |
247 | ||
bb9b813b | 248 | pr_debug(DEVNAME ": starting\n"); |
1da177e4 | 249 | |
1da177e4 LT |
250 | sbp.next_tb_sample = 0; |
251 | filp->f_pos = 0; | |
252 | ||
bb9b813b RB |
253 | err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, |
254 | DEVNAME " trace freeze", &sbp); | |
255 | if (err) | |
1da177e4 | 256 | return -EBUSY; |
bb9b813b | 257 | |
1da177e4 | 258 | /* Make sure there isn't a perf-cnt interrupt waiting */ |
65bda1a9 | 259 | scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); |
1da177e4 | 260 | /* Disable and clear counters, override SRC_1 */ |
65bda1a9 MR |
261 | __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | |
262 | M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1), | |
263 | IOADDR(A_SCD_PERF_CNT_CFG)); | |
1da177e4 | 264 | |
bb9b813b RB |
265 | /* |
266 | * We grab this interrupt to prevent others from trying to use it, even | |
267 | * though we don't want to service the interrupts (they only feed into | |
268 | * the trace-on-interrupt mechanism) | |
269 | */ | |
270 | err = request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, | |
271 | DEVNAME " scd perfcnt", &sbp); | |
272 | if (err) | |
273 | goto out_free_irq; | |
274 | ||
275 | /* | |
276 | * I need the core to mask these, but the interrupt mapper to pass them | |
277 | * through. I am exploiting my knowledge that cp0_status masks out | |
278 | * IP[5]. krw | |
279 | */ | |
65bda1a9 MR |
280 | __raw_writeq(K_INT_MAP_I3, |
281 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + | |
282 | (K_INT_PERF_CNT << 3))); | |
1da177e4 LT |
283 | |
284 | /* Initialize address traps */ | |
65bda1a9 MR |
285 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); |
286 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); | |
287 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); | |
288 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); | |
1da177e4 | 289 | |
65bda1a9 MR |
290 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); |
291 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); | |
292 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); | |
293 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); | |
1da177e4 | 294 | |
65bda1a9 MR |
295 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); |
296 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); | |
297 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); | |
298 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); | |
1da177e4 LT |
299 | |
300 | /* Initialize Trace Event 0-7 */ | |
bb9b813b | 301 | /* when interrupt */ |
65bda1a9 MR |
302 | __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); |
303 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); | |
304 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); | |
305 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); | |
306 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); | |
307 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); | |
308 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); | |
309 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); | |
1da177e4 LT |
310 | |
311 | /* Initialize Trace Sequence 0-7 */ | |
bb9b813b | 312 | /* Start on event 0 (interrupt) */ |
65bda1a9 MR |
313 | __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, |
314 | IOADDR(A_SCD_TRACE_SEQUENCE_0)); | |
bb9b813b | 315 | /* dsamp when d used | asamp when a used */ |
65bda1a9 MR |
316 | __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | |
317 | K_SCD_TRSEQ_TRIGGER_ALL, | |
318 | IOADDR(A_SCD_TRACE_SEQUENCE_1)); | |
319 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); | |
320 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); | |
321 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); | |
322 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); | |
323 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); | |
324 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); | |
1da177e4 LT |
325 | |
326 | /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ | |
65bda1a9 MR |
327 | __raw_writeq(1ULL << K_INT_PERF_CNT, |
328 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); | |
1da177e4 LT |
329 | |
330 | arm_tb(); | |
331 | ||
bb9b813b | 332 | pr_debug(DEVNAME ": done starting\n"); |
1da177e4 LT |
333 | |
334 | return 0; | |
bb9b813b RB |
335 | |
336 | out_free_irq: | |
337 | free_irq(K_INT_TRACE_FREEZE, &sbp); | |
338 | ||
339 | return err; | |
1da177e4 LT |
340 | } |
341 | ||
bb9b813b | 342 | static int sbprof_zbprof_stop(void) |
1da177e4 | 343 | { |
bb9b813b RB |
344 | int err; |
345 | ||
346 | pr_debug(DEVNAME ": stopping\n"); | |
1da177e4 LT |
347 | |
348 | if (sbp.tb_enable) { | |
bb9b813b RB |
349 | /* |
350 | * XXXKW there is a window here where the intr handler may run, | |
351 | * see the disable, and do the wake_up before this sleep | |
352 | * happens. | |
353 | */ | |
354 | pr_debug(DEVNAME ": wait for disarm\n"); | |
355 | err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed); | |
356 | pr_debug(DEVNAME ": disarm complete, stat %d\n", err); | |
357 | ||
358 | if (err) | |
359 | return err; | |
360 | ||
1da177e4 | 361 | sbp.tb_enable = 0; |
1da177e4 LT |
362 | free_irq(K_INT_TRACE_FREEZE, &sbp); |
363 | free_irq(K_INT_PERF_CNT, &sbp); | |
364 | } | |
365 | ||
bb9b813b | 366 | pr_debug(DEVNAME ": done stopping\n"); |
1da177e4 LT |
367 | |
368 | return 0; | |
369 | } | |
370 | ||
371 | static int sbprof_tb_open(struct inode *inode, struct file *filp) | |
372 | { | |
373 | int minor; | |
374 | ||
375 | minor = iminor(inode); | |
bb9b813b | 376 | if (minor != 0) |
1da177e4 | 377 | return -ENODEV; |
bb9b813b RB |
378 | |
379 | if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED) | |
1da177e4 | 380 | return -EBUSY; |
1da177e4 LT |
381 | |
382 | memset(&sbp, 0, sizeof(struct sbprof_tb)); | |
bb9b813b | 383 | |
1da177e4 | 384 | sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES); |
bb9b813b | 385 | if (!sbp.sbprof_tbbuf) |
1da177e4 | 386 | return -ENOMEM; |
bb9b813b | 387 | |
1da177e4 LT |
388 | memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES); |
389 | init_waitqueue_head(&sbp.tb_sync); | |
390 | init_waitqueue_head(&sbp.tb_read); | |
bb9b813b RB |
391 | mutex_init(&sbp.lock); |
392 | ||
393 | sbp.open = SB_OPEN; | |
1da177e4 LT |
394 | |
395 | return 0; | |
396 | } | |
397 | ||
398 | static int sbprof_tb_release(struct inode *inode, struct file *filp) | |
399 | { | |
bb9b813b | 400 | int minor = iminor(inode); |
1da177e4 | 401 | |
bb9b813b | 402 | if (minor != 0 || !sbp.open) |
1da177e4 | 403 | return -ENODEV; |
1da177e4 | 404 | |
bb9b813b RB |
405 | mutex_lock(&sbp.lock); |
406 | ||
407 | if (sbp.tb_armed || sbp.tb_enable) | |
1da177e4 | 408 | sbprof_zbprof_stop(); |
1da177e4 LT |
409 | |
410 | vfree(sbp.sbprof_tbbuf); | |
411 | sbp.open = 0; | |
412 | ||
bb9b813b RB |
413 | mutex_unlock(&sbp.lock); |
414 | ||
1da177e4 LT |
415 | return 0; |
416 | } | |
417 | ||
418 | static ssize_t sbprof_tb_read(struct file *filp, char *buf, | |
419 | size_t size, loff_t *offp) | |
420 | { | |
421 | int cur_sample, sample_off, cur_count, sample_left; | |
1da177e4 | 422 | long cur_off = *offp; |
bb9b813b RB |
423 | char *dest = buf; |
424 | int count = 0; | |
425 | char *src; | |
426 | ||
427 | if (!access_ok(VERIFY_WRITE, buf, size)) | |
428 | return -EFAULT; | |
429 | ||
430 | mutex_lock(&sbp.lock); | |
1da177e4 LT |
431 | |
432 | count = 0; | |
433 | cur_sample = cur_off / TB_SAMPLE_SIZE; | |
434 | sample_off = cur_off % TB_SAMPLE_SIZE; | |
435 | sample_left = TB_SAMPLE_SIZE - sample_off; | |
bb9b813b | 436 | |
1da177e4 | 437 | while (size && (cur_sample < sbp.next_tb_sample)) { |
bb9b813b RB |
438 | int err; |
439 | ||
1da177e4 LT |
440 | cur_count = size < sample_left ? size : sample_left; |
441 | src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off); | |
bb9b813b RB |
442 | err = __copy_to_user(dest, src, cur_count); |
443 | if (err) { | |
444 | *offp = cur_off + cur_count - err; | |
445 | mutex_unlock(&sbp.lock); | |
446 | return err; | |
447 | } | |
448 | ||
449 | pr_debug(DEVNAME ": read from sample %d, %d bytes\n", | |
450 | cur_sample, cur_count); | |
1da177e4 LT |
451 | size -= cur_count; |
452 | sample_left -= cur_count; | |
453 | if (!sample_left) { | |
454 | cur_sample++; | |
455 | sample_off = 0; | |
456 | sample_left = TB_SAMPLE_SIZE; | |
457 | } else { | |
458 | sample_off += cur_count; | |
459 | } | |
460 | cur_off += cur_count; | |
461 | dest += cur_count; | |
462 | count += cur_count; | |
463 | } | |
bb9b813b | 464 | |
1da177e4 | 465 | *offp = cur_off; |
bb9b813b | 466 | mutex_unlock(&sbp.lock); |
1da177e4 LT |
467 | |
468 | return count; | |
469 | } | |
470 | ||
bb9b813b RB |
471 | static long sbprof_tb_ioctl(struct file *filp, unsigned int command, |
472 | unsigned long arg) | |
1da177e4 LT |
473 | { |
474 | int error = 0; | |
475 | ||
476 | switch (command) { | |
477 | case SBPROF_ZBSTART: | |
bb9b813b | 478 | mutex_lock(&sbp.lock); |
1da177e4 | 479 | error = sbprof_zbprof_start(filp); |
bb9b813b | 480 | mutex_unlock(&sbp.lock); |
1da177e4 | 481 | break; |
bb9b813b | 482 | |
1da177e4 | 483 | case SBPROF_ZBSTOP: |
bb9b813b | 484 | mutex_lock(&sbp.lock); |
1da177e4 | 485 | error = sbprof_zbprof_stop(); |
bb9b813b | 486 | mutex_unlock(&sbp.lock); |
1da177e4 | 487 | break; |
bb9b813b | 488 | |
1da177e4 | 489 | case SBPROF_ZBWAITFULL: |
bb9b813b RB |
490 | error = wait_event_interruptible(sbp.tb_read, TB_FULL); |
491 | if (error) | |
492 | break; | |
493 | ||
494 | error = put_user(TB_FULL, (int *) arg); | |
495 | break; | |
496 | ||
1da177e4 LT |
497 | default: |
498 | error = -EINVAL; | |
499 | break; | |
500 | } | |
501 | ||
502 | return error; | |
503 | } | |
504 | ||
5dfe4c96 | 505 | static const struct file_operations sbprof_tb_fops = { |
1da177e4 LT |
506 | .owner = THIS_MODULE, |
507 | .open = sbprof_tb_open, | |
508 | .release = sbprof_tb_release, | |
509 | .read = sbprof_tb_read, | |
b288f135 RB |
510 | .unlocked_ioctl = sbprof_tb_ioctl, |
511 | .compat_ioctl = sbprof_tb_ioctl, | |
1da177e4 LT |
512 | .mmap = NULL, |
513 | }; | |
514 | ||
bb9b813b RB |
515 | static struct class *tb_class; |
516 | static struct device *tb_dev; | |
517 | ||
1da177e4 LT |
518 | static int __init sbprof_tb_init(void) |
519 | { | |
bb9b813b RB |
520 | struct device *dev; |
521 | struct class *tbc; | |
522 | int err; | |
523 | ||
1da177e4 LT |
524 | if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) { |
525 | printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n", | |
526 | SBPROF_TB_MAJOR); | |
527 | return -EIO; | |
528 | } | |
bb9b813b RB |
529 | |
530 | tbc = class_create(THIS_MODULE, "sb_tracebuffer"); | |
531 | if (IS_ERR(tbc)) { | |
532 | err = PTR_ERR(tbc); | |
533 | goto out_chrdev; | |
534 | } | |
535 | ||
536 | tb_class = tbc; | |
537 | ||
538 | dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), "tb"); | |
539 | if (IS_ERR(dev)) { | |
540 | err = PTR_ERR(dev); | |
541 | goto out_class; | |
542 | } | |
543 | tb_dev = dev; | |
544 | ||
1da177e4 LT |
545 | sbp.open = 0; |
546 | tb_period = zbbus_mhz * 10000LL; | |
bb9b813b RB |
547 | pr_info(DEVNAME ": initialized - tb_period = %lld\n", tb_period); |
548 | ||
1da177e4 | 549 | return 0; |
bb9b813b RB |
550 | |
551 | out_class: | |
552 | class_destroy(tb_class); | |
553 | out_chrdev: | |
554 | unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME); | |
555 | ||
556 | return err; | |
1da177e4 LT |
557 | } |
558 | ||
559 | static void __exit sbprof_tb_cleanup(void) | |
560 | { | |
bb9b813b | 561 | device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0)); |
1da177e4 | 562 | unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME); |
bb9b813b | 563 | class_destroy(tb_class); |
1da177e4 LT |
564 | } |
565 | ||
566 | module_init(sbprof_tb_init); | |
567 | module_exit(sbprof_tb_cleanup); | |
bb9b813b RB |
568 | |
569 | MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR); | |
570 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); | |
571 | MODULE_LICENSE("GPL"); |