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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
1da177e4 LT |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/linkage.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/smp.h> | |
24 | #include <linux/mm.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/kernel_stat.h> | |
27 | ||
28 | #include <asm/errno.h> | |
29 | #include <asm/signal.h> | |
30 | #include <asm/system.h> | |
31 | #include <asm/ptrace.h> | |
32 | #include <asm/io.h> | |
33 | ||
34 | #include <asm/sibyte/sb1250_regs.h> | |
35 | #include <asm/sibyte/sb1250_int.h> | |
36 | #include <asm/sibyte/sb1250_uart.h> | |
37 | #include <asm/sibyte/sb1250_scd.h> | |
38 | #include <asm/sibyte/sb1250.h> | |
39 | ||
40 | /* | |
41 | * These are the routines that handle all the low level interrupt stuff. | |
42 | * Actions handled here are: initialization of the interrupt map, requesting of | |
43 | * interrupt lines by handlers, dispatching if interrupts to handlers, probing | |
44 | * for interrupt lines | |
45 | */ | |
46 | ||
47 | ||
48 | #define shutdown_sb1250_irq disable_sb1250_irq | |
49 | static void end_sb1250_irq(unsigned int irq); | |
50 | static void enable_sb1250_irq(unsigned int irq); | |
51 | static void disable_sb1250_irq(unsigned int irq); | |
52 | static unsigned int startup_sb1250_irq(unsigned int irq); | |
53 | static void ack_sb1250_irq(unsigned int irq); | |
54 | #ifdef CONFIG_SMP | |
942d042d | 55 | static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); |
1da177e4 LT |
56 | #endif |
57 | ||
58 | #ifdef CONFIG_SIBYTE_HAS_LDT | |
59 | extern unsigned long ldt_eoi_space; | |
60 | #endif | |
61 | ||
62 | #ifdef CONFIG_KGDB | |
63 | static int kgdb_irq; | |
64 | ||
65 | /* Default to UART1 */ | |
66 | int kgdb_port = 1; | |
67 | #ifdef CONFIG_SIBYTE_SB1250_DUART | |
68 | extern char sb1250_duart_present[]; | |
69 | #endif | |
70 | #endif | |
71 | ||
94dee171 | 72 | static struct irq_chip sb1250_irq_type = { |
8ab00b9a RB |
73 | .typename = "SB1250-IMR", |
74 | .startup = startup_sb1250_irq, | |
75 | .shutdown = shutdown_sb1250_irq, | |
76 | .enable = enable_sb1250_irq, | |
77 | .disable = disable_sb1250_irq, | |
78 | .ack = ack_sb1250_irq, | |
79 | .end = end_sb1250_irq, | |
1da177e4 | 80 | #ifdef CONFIG_SMP |
8ab00b9a | 81 | .set_affinity = sb1250_set_affinity |
1da177e4 LT |
82 | #endif |
83 | }; | |
84 | ||
85 | /* Store the CPU id (not the logical number) */ | |
86 | int sb1250_irq_owner[SB1250_NR_IRQS]; | |
87 | ||
88 | DEFINE_SPINLOCK(sb1250_imr_lock); | |
89 | ||
90 | void sb1250_mask_irq(int cpu, int irq) | |
91 | { | |
92 | unsigned long flags; | |
93 | u64 cur_ints; | |
94 | ||
95 | spin_lock_irqsave(&sb1250_imr_lock, flags); | |
65bda1a9 MR |
96 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
97 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 | 98 | cur_ints |= (((u64) 1) << irq); |
65bda1a9 MR |
99 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
100 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 LT |
101 | spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
102 | } | |
103 | ||
104 | void sb1250_unmask_irq(int cpu, int irq) | |
105 | { | |
106 | unsigned long flags; | |
107 | u64 cur_ints; | |
108 | ||
109 | spin_lock_irqsave(&sb1250_imr_lock, flags); | |
65bda1a9 MR |
110 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
111 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 | 112 | cur_ints &= ~(((u64) 1) << irq); |
65bda1a9 MR |
113 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
114 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 LT |
115 | spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
116 | } | |
117 | ||
118 | #ifdef CONFIG_SMP | |
942d042d | 119 | static void sb1250_set_affinity(unsigned int irq, cpumask_t mask) |
1da177e4 LT |
120 | { |
121 | int i = 0, old_cpu, cpu, int_on; | |
122 | u64 cur_ints; | |
94dee171 | 123 | struct irq_desc *desc = irq_desc + irq; |
1da177e4 LT |
124 | unsigned long flags; |
125 | ||
942d042d | 126 | i = first_cpu(mask); |
1da177e4 | 127 | |
942d042d | 128 | if (cpus_weight(mask) > 1) { |
1da177e4 LT |
129 | printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); |
130 | return; | |
131 | } | |
132 | ||
133 | /* Convert logical CPU to physical CPU */ | |
134 | cpu = cpu_logical_map(i); | |
135 | ||
136 | /* Protect against other affinity changers and IMR manipulation */ | |
137 | spin_lock_irqsave(&desc->lock, flags); | |
138 | spin_lock(&sb1250_imr_lock); | |
139 | ||
140 | /* Swizzle each CPU's IMR (but leave the IP selection alone) */ | |
141 | old_cpu = sb1250_irq_owner[irq]; | |
65bda1a9 MR |
142 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + |
143 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 LT |
144 | int_on = !(cur_ints & (((u64) 1) << irq)); |
145 | if (int_on) { | |
146 | /* If it was on, mask it */ | |
147 | cur_ints |= (((u64) 1) << irq); | |
65bda1a9 MR |
148 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + |
149 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 LT |
150 | } |
151 | sb1250_irq_owner[irq] = cpu; | |
152 | if (int_on) { | |
153 | /* unmask for the new CPU */ | |
65bda1a9 MR |
154 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
155 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 | 156 | cur_ints &= ~(((u64) 1) << irq); |
65bda1a9 MR |
157 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
158 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 LT |
159 | } |
160 | spin_unlock(&sb1250_imr_lock); | |
161 | spin_unlock_irqrestore(&desc->lock, flags); | |
162 | } | |
163 | #endif | |
164 | ||
1da177e4 LT |
165 | /*****************************************************************************/ |
166 | ||
167 | static unsigned int startup_sb1250_irq(unsigned int irq) | |
168 | { | |
169 | sb1250_unmask_irq(sb1250_irq_owner[irq], irq); | |
170 | ||
171 | return 0; /* never anything pending */ | |
172 | } | |
173 | ||
174 | ||
175 | static void disable_sb1250_irq(unsigned int irq) | |
176 | { | |
177 | sb1250_mask_irq(sb1250_irq_owner[irq], irq); | |
178 | } | |
179 | ||
180 | static void enable_sb1250_irq(unsigned int irq) | |
181 | { | |
182 | sb1250_unmask_irq(sb1250_irq_owner[irq], irq); | |
183 | } | |
184 | ||
185 | ||
186 | static void ack_sb1250_irq(unsigned int irq) | |
187 | { | |
188 | #ifdef CONFIG_SIBYTE_HAS_LDT | |
189 | u64 pending; | |
190 | ||
191 | /* | |
192 | * If the interrupt was an HT interrupt, now is the time to | |
193 | * clear it. NOTE: we assume the HT bridge was set up to | |
194 | * deliver the interrupts to all CPUs (which makes affinity | |
195 | * changing easier for us) | |
196 | */ | |
65bda1a9 MR |
197 | pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], |
198 | R_IMR_LDT_INTERRUPT))); | |
1da177e4 LT |
199 | pending &= ((u64)1 << (irq)); |
200 | if (pending) { | |
201 | int i; | |
202 | for (i=0; i<NR_CPUS; i++) { | |
203 | int cpu; | |
204 | #ifdef CONFIG_SMP | |
205 | cpu = cpu_logical_map(i); | |
206 | #else | |
207 | cpu = i; | |
208 | #endif | |
209 | /* | |
210 | * Clear for all CPUs so an affinity switch | |
211 | * doesn't find an old status | |
212 | */ | |
65bda1a9 MR |
213 | __raw_writeq(pending, |
214 | IOADDR(A_IMR_REGISTER(cpu, | |
1da177e4 LT |
215 | R_IMR_LDT_INTERRUPT_CLR))); |
216 | } | |
217 | ||
218 | /* | |
219 | * Generate EOI. For Pass 1 parts, EOI is a nop. For | |
220 | * Pass 2, the LDT world may be edge-triggered, but | |
221 | * this EOI shouldn't hurt. If they are | |
222 | * level-sensitive, the EOI is required. | |
223 | */ | |
224 | *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0; | |
225 | } | |
226 | #endif | |
227 | sb1250_mask_irq(sb1250_irq_owner[irq], irq); | |
228 | } | |
229 | ||
230 | ||
231 | static void end_sb1250_irq(unsigned int irq) | |
232 | { | |
233 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { | |
234 | sb1250_unmask_irq(sb1250_irq_owner[irq], irq); | |
235 | } | |
236 | } | |
237 | ||
238 | ||
239 | void __init init_sb1250_irqs(void) | |
240 | { | |
241 | int i; | |
242 | ||
243 | for (i = 0; i < NR_IRQS; i++) { | |
244 | irq_desc[i].status = IRQ_DISABLED; | |
245 | irq_desc[i].action = 0; | |
246 | irq_desc[i].depth = 1; | |
247 | if (i < SB1250_NR_IRQS) { | |
d1bef4ed | 248 | irq_desc[i].chip = &sb1250_irq_type; |
1da177e4 LT |
249 | sb1250_irq_owner[i] = 0; |
250 | } else { | |
94dee171 | 251 | irq_desc[i].chip = &no_irq_chip; |
1da177e4 LT |
252 | } |
253 | } | |
254 | } | |
255 | ||
256 | ||
937a8015 | 257 | static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id) |
1da177e4 LT |
258 | { |
259 | return IRQ_NONE; | |
260 | } | |
261 | ||
262 | static struct irqaction sb1250_dummy_action = { | |
263 | .handler = sb1250_dummy_handler, | |
264 | .flags = 0, | |
265 | .mask = CPU_MASK_NONE, | |
266 | .name = "sb1250-private", | |
267 | .next = NULL, | |
268 | .dev_id = 0 | |
269 | }; | |
270 | ||
271 | int sb1250_steal_irq(int irq) | |
272 | { | |
94dee171 | 273 | struct irq_desc *desc = irq_desc + irq; |
1da177e4 LT |
274 | unsigned long flags; |
275 | int retval = 0; | |
276 | ||
277 | if (irq >= SB1250_NR_IRQS) | |
278 | return -EINVAL; | |
279 | ||
280 | spin_lock_irqsave(&desc->lock,flags); | |
281 | /* Don't allow sharing at all for these */ | |
282 | if (desc->action != NULL) | |
283 | retval = -EBUSY; | |
284 | else { | |
285 | desc->action = &sb1250_dummy_action; | |
286 | desc->depth = 0; | |
287 | } | |
288 | spin_unlock_irqrestore(&desc->lock,flags); | |
289 | return 0; | |
290 | } | |
291 | ||
292 | /* | |
293 | * arch_init_irq is called early in the boot sequence from init/main.c via | |
294 | * init_IRQ. It is responsible for setting up the interrupt mapper and | |
295 | * installing the handler that will be responsible for dispatching interrupts | |
296 | * to the "right" place. | |
297 | */ | |
298 | /* | |
299 | * For now, map all interrupts to IP[2]. We could save | |
300 | * some cycles by parceling out system interrupts to different | |
301 | * IP lines, but keep it simple for bringup. We'll also direct | |
302 | * all interrupts to a single CPU; we should probably route | |
303 | * PCI and LDT to one cpu and everything else to the other | |
304 | * to balance the load a bit. | |
305 | * | |
306 | * On the second cpu, everything is set to IP5, which is | |
307 | * ignored, EXCEPT the mailbox interrupt. That one is | |
308 | * set to IP[2] so it is handled. This is needed so we | |
309 | * can do cross-cpu function calls, as requred by SMP | |
310 | */ | |
311 | ||
312 | #define IMR_IP2_VAL K_INT_MAP_I0 | |
313 | #define IMR_IP3_VAL K_INT_MAP_I1 | |
314 | #define IMR_IP4_VAL K_INT_MAP_I2 | |
315 | #define IMR_IP5_VAL K_INT_MAP_I3 | |
316 | #define IMR_IP6_VAL K_INT_MAP_I4 | |
317 | ||
318 | void __init arch_init_irq(void) | |
319 | { | |
320 | ||
321 | unsigned int i; | |
322 | u64 tmp; | |
323 | unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | | |
324 | STATUSF_IP1 | STATUSF_IP0; | |
325 | ||
326 | /* Default everything to IP2 */ | |
327 | for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ | |
65bda1a9 MR |
328 | __raw_writeq(IMR_IP2_VAL, |
329 | IOADDR(A_IMR_REGISTER(0, | |
330 | R_IMR_INTERRUPT_MAP_BASE) + | |
331 | (i << 3))); | |
332 | __raw_writeq(IMR_IP2_VAL, | |
333 | IOADDR(A_IMR_REGISTER(1, | |
334 | R_IMR_INTERRUPT_MAP_BASE) + | |
335 | (i << 3))); | |
1da177e4 LT |
336 | } |
337 | ||
338 | init_sb1250_irqs(); | |
339 | ||
340 | /* | |
341 | * Map the high 16 bits of the mailbox registers to IP[3], for | |
342 | * inter-cpu messages | |
343 | */ | |
344 | /* Was I1 */ | |
65bda1a9 MR |
345 | __raw_writeq(IMR_IP3_VAL, |
346 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + | |
347 | (K_INT_MBOX_0 << 3))); | |
348 | __raw_writeq(IMR_IP3_VAL, | |
349 | IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + | |
350 | (K_INT_MBOX_0 << 3))); | |
1da177e4 LT |
351 | |
352 | /* Clear the mailboxes. The firmware may leave them dirty */ | |
65bda1a9 MR |
353 | __raw_writeq(0xffffffffffffffffULL, |
354 | IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); | |
355 | __raw_writeq(0xffffffffffffffffULL, | |
356 | IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); | |
1da177e4 LT |
357 | |
358 | /* Mask everything except the mailbox registers for both cpus */ | |
359 | tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); | |
65bda1a9 MR |
360 | __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); |
361 | __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); | |
1da177e4 LT |
362 | |
363 | sb1250_steal_irq(K_INT_MBOX_0); | |
364 | ||
365 | /* | |
366 | * Note that the timer interrupts are also mapped, but this is | |
42a3b4f2 | 367 | * done in sb1250_time_init(). Also, the profiling driver |
1da177e4 LT |
368 | * does its own management of IP7. |
369 | */ | |
370 | ||
371 | #ifdef CONFIG_KGDB | |
372 | imask |= STATUSF_IP6; | |
373 | #endif | |
374 | /* Enable necessary IPs, disable the rest */ | |
375 | change_c0_status(ST0_IM, imask); | |
1da177e4 LT |
376 | |
377 | #ifdef CONFIG_KGDB | |
378 | if (kgdb_flag) { | |
379 | kgdb_irq = K_INT_UART_0 + kgdb_port; | |
380 | ||
42a3b4f2 | 381 | #ifdef CONFIG_SIBYTE_SB1250_DUART |
1da177e4 LT |
382 | sb1250_duart_present[kgdb_port] = 0; |
383 | #endif | |
384 | /* Setup uart 1 settings, mapper */ | |
65bda1a9 MR |
385 | __raw_writeq(M_DUART_IMR_BRK, |
386 | IOADDR(A_DUART_IMRREG(kgdb_port))); | |
1da177e4 LT |
387 | |
388 | sb1250_steal_irq(kgdb_irq); | |
65bda1a9 MR |
389 | __raw_writeq(IMR_IP6_VAL, |
390 | IOADDR(A_IMR_REGISTER(0, | |
391 | R_IMR_INTERRUPT_MAP_BASE) + | |
392 | (kgdb_irq << 3))); | |
1da177e4 LT |
393 | sb1250_unmask_irq(0, kgdb_irq); |
394 | } | |
395 | #endif | |
396 | } | |
397 | ||
398 | #ifdef CONFIG_KGDB | |
399 | ||
400 | #include <linux/delay.h> | |
401 | ||
402 | #define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) | |
403 | #define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) | |
404 | ||
937a8015 | 405 | static void sb1250_kgdb_interrupt(void) |
1da177e4 LT |
406 | { |
407 | /* | |
408 | * Clear break-change status (allow some time for the remote | |
409 | * host to stop the break, since we would see another | |
410 | * interrupt on the end-of-break too) | |
411 | */ | |
412 | kstat_this_cpu.irqs[kgdb_irq]++; | |
413 | mdelay(500); | |
414 | duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT | | |
415 | M_DUART_RX_EN | M_DUART_TX_EN); | |
937a8015 | 416 | set_async_breakpoint(&get_irq_regs()->cp0_epc); |
1da177e4 LT |
417 | } |
418 | ||
419 | #endif /* CONFIG_KGDB */ | |
e4ac58af | 420 | |
937a8015 RB |
421 | extern void sb1250_timer_interrupt(void); |
422 | extern void sb1250_mailbox_interrupt(void); | |
4fb60a4b | 423 | |
937a8015 | 424 | asmlinkage void plat_irq_dispatch(void) |
e4ac58af RB |
425 | { |
426 | unsigned int pending; | |
427 | ||
428 | #ifdef CONFIG_SIBYTE_SB1250_PROF | |
429 | /* Set compare to count to silence count/compare timer interrupts */ | |
4fb60a4b | 430 | write_c0_compare(read_c0_count()); |
e4ac58af RB |
431 | #endif |
432 | ||
433 | /* | |
434 | * What a pain. We have to be really careful saving the upper 32 bits | |
435 | * of any * register across function calls if we don't want them | |
436 | * trashed--since were running in -o32, the calling routing never saves | |
437 | * the full 64 bits of a register across a function call. Being the | |
438 | * interrupt handler, we're guaranteed that interrupts are disabled | |
439 | * during this code so we don't have to worry about random interrupts | |
440 | * blasting the high 32 bits. | |
441 | */ | |
442 | ||
d599def5 | 443 | pending = read_c0_cause() & read_c0_status(); |
e4ac58af RB |
444 | |
445 | #ifdef CONFIG_SIBYTE_SB1250_PROF | |
6e61e85b | 446 | if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ |
937a8015 | 447 | sbprof_cpu_intr(); |
6e61e85b | 448 | else |
e4ac58af RB |
449 | #endif |
450 | ||
451 | if (pending & CAUSEF_IP4) | |
937a8015 | 452 | sb1250_timer_interrupt(); |
e4ac58af RB |
453 | |
454 | #ifdef CONFIG_SMP | |
6e61e85b | 455 | else if (pending & CAUSEF_IP3) |
937a8015 | 456 | sb1250_mailbox_interrupt(); |
e4ac58af RB |
457 | #endif |
458 | ||
459 | #ifdef CONFIG_KGDB | |
6e61e85b | 460 | else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */ |
937a8015 | 461 | sb1250_kgdb_interrupt(); |
e4ac58af RB |
462 | #endif |
463 | ||
6e61e85b | 464 | else if (pending & CAUSEF_IP2) { |
e4ac58af RB |
465 | unsigned long long mask; |
466 | ||
467 | /* | |
468 | * Default...we've hit an IP[2] interrupt, which means we've | |
469 | * got to check the 1250 interrupt registers to figure out what | |
470 | * to do. Need to detect which CPU we're on, now that | |
4fb60a4b | 471 | * smp_affinity is supported. |
e4ac58af RB |
472 | */ |
473 | mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(), | |
474 | R_IMR_INTERRUPT_STATUS_BASE))); | |
475 | if (mask) | |
937a8015 | 476 | do_IRQ(fls64(mask) - 1); |
d599def5 | 477 | else |
937a8015 | 478 | spurious_interrupt(); |
d599def5 | 479 | } else |
937a8015 | 480 | spurious_interrupt(); |
e4ac58af | 481 | } |