[mirror_ubuntu-jammy-kernel.git] / arch / mips / sibyte / sb1250 / irq.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/kernel_stat.h>

#include <asm/errno.h>
#include <asm/signal.h>
#include <asm/time.h>
#include <asm/io.h>

#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sb1250_uart.h>
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/sb1250.h>

/*
 * These are the routines that handle all the low level interrupt stuff.
 * Actions handled here are: initialization of the interrupt map, requesting of
 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
 * for interrupt lines
 */

#ifdef CONFIG_SIBYTE_HAS_LDT
extern unsigned long ldt_eoi_space;
#endif

/* Store the CPU id (not the logical number) */
int sb1250_irq_owner[SB1250_NR_IRQS];

static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);

void sb1250_mask_irq(int cpu, int irq)
{
	unsigned long flags;
	u64 cur_ints;

	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	cur_ints |= (((u64) 1) << irq);
	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}

void sb1250_unmask_irq(int cpu, int irq)
{
	unsigned long flags;
	u64 cur_ints;

	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	cur_ints &= ~(((u64) 1) << irq);
	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}

#ifdef CONFIG_SMP
static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask,
			       bool force)
{
	int i = 0, old_cpu, cpu, int_on;
	unsigned int irq = d->irq;
	u64 cur_ints;
	unsigned long flags;

	i = cpumask_first_and(mask, cpu_online_mask);

	/* Convert logical CPU to physical CPU */
	cpu = cpu_logical_map(i);

	/* Protect against other affinity changers and IMR manipulation */
	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);

	/* Swizzle each CPU's IMR (but leave the IP selection alone) */
	old_cpu = sb1250_irq_owner[irq];
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
					R_IMR_INTERRUPT_MASK));
	int_on = !(cur_ints & (((u64) 1) << irq));
	if (int_on) {
		/* If it was on, mask it */
		cur_ints |= (((u64) 1) << irq);
		____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
					R_IMR_INTERRUPT_MASK));
	}
	sb1250_irq_owner[irq] = cpu;
	if (int_on) {
		/* unmask for the new CPU */
		cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
		cur_ints &= ~(((u64) 1) << irq);
		____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	}
	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);

	return 0;
}
#endif

static void disable_sb1250_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
}

static void enable_sb1250_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
}


static void ack_sb1250_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;
#ifdef CONFIG_SIBYTE_HAS_LDT
	u64 pending;

	/*
	 * If the interrupt was an HT interrupt, now is the time to
	 * clear it.  NOTE: we assume the HT bridge was set up to
	 * deliver the interrupts to all CPUs (which makes affinity
	 * changing easier for us)
	 */
	pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
						    R_IMR_LDT_INTERRUPT)));
	pending &= ((u64)1 << (irq));
	if (pending) {
		int i;
		for (i=0; i<NR_CPUS; i++) {
			int cpu;
#ifdef CONFIG_SMP
			cpu = cpu_logical_map(i);
#else
			cpu = i;
#endif
			/*
			 * Clear for all CPUs so an affinity switch
			 * doesn't find an old status
			 */
			__raw_writeq(pending,
				     IOADDR(A_IMR_REGISTER(cpu,
						R_IMR_LDT_INTERRUPT_CLR)));
		}

		/*
		 * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
		 * Pass 2, the LDT world may be edge-triggered, but
		 * this EOI shouldn't hurt.  If they are
		 * level-sensitive, the EOI is required.
		 */
		*(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
	}
#endif
	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
}

static struct irq_chip sb1250_irq_type = {
	.name = "SB1250-IMR",
	.irq_mask_ack = ack_sb1250_irq,
	.irq_unmask = enable_sb1250_irq,
	.irq_mask = disable_sb1250_irq,
#ifdef CONFIG_SMP
	.irq_set_affinity = sb1250_set_affinity
#endif
};

void __init init_sb1250_irqs(void)
{
	int i;

	for (i = 0; i < SB1250_NR_IRQS; i++) {
		irq_set_chip_and_handler(i, &sb1250_irq_type,
					 handle_level_irq);
		sb1250_irq_owner[i] = 0;
	}
}


/*
 *  arch_init_irq is called early in the boot sequence from init/main.c via
 *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 *  installing the handler that will be responsible for dispatching interrupts
 *  to the "right" place.
 */
/*
 * For now, map all interrupts to IP[2].  We could save
 * some cycles by parceling out system interrupts to different
 * IP lines, but keep it simple for bringup.  We'll also direct
 * all interrupts to a single CPU; we should probably route
 * PCI and LDT to one cpu and everything else to the other
 * to balance the load a bit.
 *
 * On the second cpu, everything is set to IP5, which is
 * ignored, EXCEPT the mailbox interrupt.  That one is
 * set to IP[2] so it is handled.  This is needed so we
 * can do cross-cpu function calls, as required by SMP
 */

#define IMR_IP2_VAL	K_INT_MAP_I0
#define IMR_IP3_VAL	K_INT_MAP_I1
#define IMR_IP4_VAL	K_INT_MAP_I2
#define IMR_IP5_VAL	K_INT_MAP_I3
#define IMR_IP6_VAL	K_INT_MAP_I4

void __init arch_init_irq(void)
{

	unsigned int i;
	u64 tmp;
	unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
		STATUSF_IP1 | STATUSF_IP0;

	/* Default everything to IP2 */
	for (i = 0; i < SB1250_NR_IRQS; i++) {	/* was I0 */
		__raw_writeq(IMR_IP2_VAL,
			     IOADDR(A_IMR_REGISTER(0,
						   R_IMR_INTERRUPT_MAP_BASE) +
				    (i << 3)));
		__raw_writeq(IMR_IP2_VAL,
			     IOADDR(A_IMR_REGISTER(1,
						   R_IMR_INTERRUPT_MAP_BASE) +
				    (i << 3)));
	}

	init_sb1250_irqs();

	/*
	 * Map the high 16 bits of the mailbox registers to IP[3], for
	 * inter-cpu messages
	 */
	/* Was I1 */
	__raw_writeq(IMR_IP3_VAL,
		     IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
			    (K_INT_MBOX_0 << 3)));
	__raw_writeq(IMR_IP3_VAL,
		     IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
			    (K_INT_MBOX_0 << 3)));

	/* Clear the mailboxes.	 The firmware may leave them dirty */
	__raw_writeq(0xffffffffffffffffULL,
		     IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
	__raw_writeq(0xffffffffffffffffULL,
		     IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));

	/* Mask everything except the mailbox registers for both cpus */
	tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));

	/*
	 * Note that the timer interrupts are also mapped, but this is
	 * done in sb1250_time_init().	Also, the profiling driver
	 * does its own management of IP7.
	 */

	/* Enable necessary IPs, disable the rest */
	change_c0_status(ST0_IM, imask);
}

extern void sb1250_mailbox_interrupt(void);

static inline void dispatch_ip2(void)
{
	unsigned int cpu = smp_processor_id();
	unsigned long long mask;

	/*
	 * Default...we've hit an IP[2] interrupt, which means we've got to
	 * check the 1250 interrupt registers to figure out what to do.	 Need
	 * to detect which CPU we're on, now that smp_affinity is supported.
	 */
	mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
				  R_IMR_INTERRUPT_STATUS_BASE)));
	if (mask)
		do_IRQ(fls64(mask) - 1);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int cpu = smp_processor_id();
	unsigned int pending;

	/*
	 * What a pain. We have to be really careful saving the upper 32 bits
	 * of any * register across function calls if we don't want them
	 * trashed--since were running in -o32, the calling routing never saves
	 * the full 64 bits of a register across a function call.  Being the
	 * interrupt handler, we're guaranteed that interrupts are disabled
	 * during this code so we don't have to worry about random interrupts
	 * blasting the high 32 bits.
	 */

	pending = read_c0_cause() & read_c0_status() & ST0_IM;

	if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
	else if (pending & CAUSEF_IP4)
		do_IRQ(K_INT_TIMER_0 + cpu);	/* sb1250_timer_interrupt() */

#ifdef CONFIG_SMP
	else if (pending & CAUSEF_IP3)
		sb1250_mailbox_interrupt();
#endif

	else if (pending & CAUSEF_IP2)
		dispatch_ip2();
	else
		spurious_interrupt();
}
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
1da177e4 LT	3	* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
1da177e4	4	*/
1da177e4 LT	5	#include <linux/kernel.h>
	6	#include <linux/init.h>
	7	#include <linux/linkage.h>
	8	#include <linux/interrupt.h>
	9	#include <linux/spinlock.h>
	10	#include <linux/smp.h>
	11	#include <linux/mm.h>
1da177e4 LT	12	#include <linux/kernel_stat.h>
	13
	14	#include <asm/errno.h>
	15	#include <asm/signal.h>
7bcf7717	16	#include <asm/time.h>
1da177e4 LT	17	#include <asm/io.h>
	18
	19	#include <asm/sibyte/sb1250_regs.h>
	20	#include <asm/sibyte/sb1250_int.h>
	21	#include <asm/sibyte/sb1250_uart.h>
	22	#include <asm/sibyte/sb1250_scd.h>
	23	#include <asm/sibyte/sb1250.h>
	24
	25	/*
	26	* These are the routines that handle all the low level interrupt stuff.
	27	* Actions handled here are: initialization of the interrupt map, requesting of
	28	* interrupt lines by handlers, dispatching if interrupts to handlers, probing
	29	* for interrupt lines
	30	*/
	31
1da177e4 LT	32	#ifdef CONFIG_SIBYTE_HAS_LDT
	33	extern unsigned long ldt_eoi_space;
	34	#endif
	35
1da177e4 LT	36	/* Store the CPU id (not the logical number) */
	37	int sb1250_irq_owner[SB1250_NR_IRQS];
	38
5772f6de	39	static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
1da177e4 LT	40
	41	void sb1250_mask_irq(int cpu, int irq)
	42	{
	43	unsigned long flags;
	44	u64 cur_ints;
	45
5772f6de	46	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
65bda1a9 MR	47	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	48	R_IMR_INTERRUPT_MASK));
1da177e4	49	cur_ints \|= (((u64) 1) << irq);
65bda1a9 MR	50	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	51	R_IMR_INTERRUPT_MASK));
5772f6de	52	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
1da177e4 LT	53	}
	54
	55	void sb1250_unmask_irq(int cpu, int irq)
	56	{
	57	unsigned long flags;
	58	u64 cur_ints;
	59
5772f6de	60	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
65bda1a9 MR	61	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	62	R_IMR_INTERRUPT_MASK));
1da177e4	63	cur_ints &= ~(((u64) 1) << irq);
65bda1a9 MR	64	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	65	R_IMR_INTERRUPT_MASK));
5772f6de	66	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
1da177e4 LT	67	}
	68
	69	#ifdef CONFIG_SMP
d6d5d5c4 TG	70	static int sb1250_set_affinity(struct irq_data d, const struct cpumask mask,
d6d5d5c4 TG	71	bool force)
1da177e4 LT	72	{
1da177e4 LT	73	int i = 0, old_cpu, cpu, int_on;
d6d5d5c4	74	unsigned int irq = d->irq;
1da177e4	75	u64 cur_ints;
1da177e4 LT	76	unsigned long flags;
1da177e4 LT	77
421d1563	78	i = cpumask_first_and(mask, cpu_online_mask);
1da177e4	79
1da177e4 LT	80	/* Convert logical CPU to physical CPU */
	81	cpu = cpu_logical_map(i);
	82
	83	/* Protect against other affinity changers and IMR manipulation */
5772f6de	84	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
1da177e4 LT	85
	86	/* Swizzle each CPU's IMR (but leave the IP selection alone) */
	87	old_cpu = sb1250_irq_owner[irq];
65bda1a9 MR	88	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
65bda1a9 MR	89	R_IMR_INTERRUPT_MASK));
1da177e4 LT	90	int_on = !(cur_ints & (((u64) 1) << irq));
	91	if (int_on) {
	92	/* If it was on, mask it */
	93	cur_ints \|= (((u64) 1) << irq);
65bda1a9 MR	94	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
65bda1a9 MR	95	R_IMR_INTERRUPT_MASK));
1da177e4 LT	96	}
	97	sb1250_irq_owner[irq] = cpu;
	98	if (int_on) {
	99	/* unmask for the new CPU */
65bda1a9 MR	100	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	101	R_IMR_INTERRUPT_MASK));
1da177e4	102	cur_ints &= ~(((u64) 1) << irq);
65bda1a9 MR	103	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	104	R_IMR_INTERRUPT_MASK));
1da177e4	105	}
5772f6de	106	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
d5dedd45 YL	107
d5dedd45 YL	108	return 0;
1da177e4 LT	109	}
	110	#endif
	111
1544129d TG	112	static void disable_sb1250_irq(struct irq_data *d)
	113	{
	114	unsigned int irq = d->irq;
	115
	116	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
	117	}
	118
d6d5d5c4	119	static void enable_sb1250_irq(struct irq_data *d)
1da177e4	120	{
d6d5d5c4	121	unsigned int irq = d->irq;
1da177e4	122
1da177e4 LT	123	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
	124	}
	125
	126
d6d5d5c4	127	static void ack_sb1250_irq(struct irq_data *d)
1da177e4	128	{
d6d5d5c4	129	unsigned int irq = d->irq;
1da177e4 LT	130	#ifdef CONFIG_SIBYTE_HAS_LDT
	131	u64 pending;
	132
	133	/*
	134	* If the interrupt was an HT interrupt, now is the time to
	135	* clear it. NOTE: we assume the HT bridge was set up to
	136	* deliver the interrupts to all CPUs (which makes affinity
	137	* changing easier for us)
	138	*/
65bda1a9 MR	139	pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
65bda1a9 MR	140	R_IMR_LDT_INTERRUPT)));
1da177e4 LT	141	pending &= ((u64)1 << (irq));
	142	if (pending) {
	143	int i;
	144	for (i=0; i<NR_CPUS; i++) {
	145	int cpu;
	146	#ifdef CONFIG_SMP
	147	cpu = cpu_logical_map(i);
	148	#else
	149	cpu = i;
	150	#endif
	151	/*
	152	* Clear for all CPUs so an affinity switch
	153	* doesn't find an old status
	154	*/
65bda1a9 MR	155	__raw_writeq(pending,
65bda1a9 MR	156	IOADDR(A_IMR_REGISTER(cpu,
1da177e4 LT	157	R_IMR_LDT_INTERRUPT_CLR)));
	158	}
	159
	160	/*
	161	* Generate EOI. For Pass 1 parts, EOI is a nop. For
	162	* Pass 2, the LDT world may be edge-triggered, but
	163	* this EOI shouldn't hurt. If they are
	164	* level-sensitive, the EOI is required.
	165	*/
	166	(uint32_t )(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
	167	}
	168	#endif
	169	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
	170	}
	171
d6d5d5c4 TG	172	static struct irq_chip sb1250_irq_type = {
	173	.name = "SB1250-IMR",
	174	.irq_mask_ack = ack_sb1250_irq,
	175	.irq_unmask = enable_sb1250_irq,
1544129d	176	.irq_mask = disable_sb1250_irq,
d6d5d5c4 TG	177	#ifdef CONFIG_SMP
	178	.irq_set_affinity = sb1250_set_affinity
	179	#endif
	180	};
1da177e4 LT	181
	182	void __init init_sb1250_irqs(void)
	183	{
	184	int i;
	185
1603b5ac	186	for (i = 0; i < SB1250_NR_IRQS; i++) {
e4ec7989 TG	187	irq_set_chip_and_handler(i, &sb1250_irq_type,
e4ec7989 TG	188	handle_level_irq);
1603b5ac	189	sb1250_irq_owner[i] = 0;
1da177e4 LT	190	}
	191	}
	192
	193
1da177e4 LT	194	/*
	195	* arch_init_irq is called early in the boot sequence from init/main.c via
	196	* init_IRQ. It is responsible for setting up the interrupt mapper and
	197	* installing the handler that will be responsible for dispatching interrupts
	198	* to the "right" place.
	199	*/
	200	/*
	201	* For now, map all interrupts to IP[2]. We could save
	202	* some cycles by parceling out system interrupts to different
	203	* IP lines, but keep it simple for bringup. We'll also direct
	204	* all interrupts to a single CPU; we should probably route
	205	* PCI and LDT to one cpu and everything else to the other
	206	* to balance the load a bit.
	207	*
	208	* On the second cpu, everything is set to IP5, which is
	209	* ignored, EXCEPT the mailbox interrupt. That one is
	210	* set to IP[2] so it is handled. This is needed so we
f77f13e2	211	* can do cross-cpu function calls, as required by SMP
1da177e4 LT	212	*/
	213
	214	#define IMR_IP2_VAL K_INT_MAP_I0
	215	#define IMR_IP3_VAL K_INT_MAP_I1
	216	#define IMR_IP4_VAL K_INT_MAP_I2
	217	#define IMR_IP5_VAL K_INT_MAP_I3
	218	#define IMR_IP6_VAL K_INT_MAP_I4
	219
	220	void __init arch_init_irq(void)
	221	{
	222
	223	unsigned int i;
	224	u64 tmp;
	225	unsigned int imask = STATUSF_IP4 \| STATUSF_IP3 \| STATUSF_IP2 \|
	226	STATUSF_IP1 \| STATUSF_IP0;
	227
	228	/* Default everything to IP2 */
	229	for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
65bda1a9 MR	230	__raw_writeq(IMR_IP2_VAL,
	231	IOADDR(A_IMR_REGISTER(0,
	232	R_IMR_INTERRUPT_MAP_BASE) +
	233	(i << 3)));
	234	__raw_writeq(IMR_IP2_VAL,
	235	IOADDR(A_IMR_REGISTER(1,
	236	R_IMR_INTERRUPT_MAP_BASE) +
	237	(i << 3)));
1da177e4 LT	238	}
	239
	240	init_sb1250_irqs();
	241
	242	/*
	243	* Map the high 16 bits of the mailbox registers to IP[3], for
	244	* inter-cpu messages
	245	*/
	246	/* Was I1 */
65bda1a9 MR	247	__raw_writeq(IMR_IP3_VAL,
	248	IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
	249	(K_INT_MBOX_0 << 3)));
	250	__raw_writeq(IMR_IP3_VAL,
	251	IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
	252	(K_INT_MBOX_0 << 3)));
1da177e4	253
70342287	254	/* Clear the mailboxes. The firmware may leave them dirty */
65bda1a9 MR	255	__raw_writeq(0xffffffffffffffffULL,
	256	IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
	257	__raw_writeq(0xffffffffffffffffULL,
	258	IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
1da177e4 LT	259
	260	/* Mask everything except the mailbox registers for both cpus */
	261	tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
65bda1a9 MR	262	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
65bda1a9 MR	263	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
1da177e4	264
1da177e4 LT	265	/*
1da177e4 LT	266	* Note that the timer interrupts are also mapped, but this is
70342287	267	* done in sb1250_time_init(). Also, the profiling driver
1da177e4 LT	268	* does its own management of IP7.
	269	*/
	270
1da177e4 LT	271	/* Enable necessary IPs, disable the rest */
1da177e4 LT	272	change_c0_status(ST0_IM, imask);
1da177e4 LT	273	}
1da177e4 LT	274
937a8015	275	extern void sb1250_mailbox_interrupt(void);
4fb60a4b	276
d0453365 RB	277	static inline void dispatch_ip2(void)
	278	{
	279	unsigned int cpu = smp_processor_id();
	280	unsigned long long mask;
	281
	282	/*
	283	* Default...we've hit an IP[2] interrupt, which means we've got to
70342287	284	* check the 1250 interrupt registers to figure out what to do. Need
d0453365 RB	285	* to detect which CPU we're on, now that smp_affinity is supported.
	286	*/
	287	mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
	288	R_IMR_INTERRUPT_STATUS_BASE)));
	289	if (mask)
	290	do_IRQ(fls64(mask) - 1);
	291	}
	292
937a8015	293	asmlinkage void plat_irq_dispatch(void)
e4ac58af	294	{
d527eef5	295	unsigned int cpu = smp_processor_id();
e4ac58af RB	296	unsigned int pending;
e4ac58af RB	297
e4ac58af RB	298	/*
	299	* What a pain. We have to be really careful saving the upper 32 bits
	300	* of any * register across function calls if we don't want them
	301	* trashed--since were running in -o32, the calling routing never saves
	302	* the full 64 bits of a register across a function call. Being the
	303	* interrupt handler, we're guaranteed that interrupts are disabled
	304	* during this code so we don't have to worry about random interrupts
	305	* blasting the high 32 bits.
	306	*/
	307
119537c0	308	pending = read_c0_cause() & read_c0_status() & ST0_IM;
e4ac58af	309
7bcf7717 RB	310	if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
	311	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
	312	else if (pending & CAUSEF_IP4)
70342287	313	do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
e4ac58af RB	314
e4ac58af RB	315	#ifdef CONFIG_SMP
6e61e85b	316	else if (pending & CAUSEF_IP3)
937a8015	317	sb1250_mailbox_interrupt();
e4ac58af RB	318	#endif
e4ac58af RB	319
d0453365 RB	320	else if (pending & CAUSEF_IP2)
	321	dispatch_ip2();
	322	else
937a8015	323	spurious_interrupt();
e4ac58af	324	}