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c066a32a TB |
1 | /* |
2 | * PCIMT specific code | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org) | |
9 | * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/serial_8250.h> | |
16 | ||
17 | #include <asm/mc146818-time.h> | |
18 | #include <asm/sni.h> | |
19 | #include <asm/time.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/irq_cpu.h> | |
22 | ||
23 | #define cacheconf (*(volatile unsigned int *)PCIMT_CACHECONF) | |
24 | #define invspace (*(volatile unsigned int *)PCIMT_INVSPACE) | |
25 | ||
26 | static void __init sni_pcimt_sc_init(void) | |
27 | { | |
28 | unsigned int scsiz, sc_size; | |
29 | ||
30 | scsiz = cacheconf & 7; | |
31 | if (scsiz == 0) { | |
32 | printk("Second level cache is deactived.\n"); | |
33 | return; | |
34 | } | |
35 | if (scsiz >= 6) { | |
36 | printk("Invalid second level cache size configured, " | |
37 | "deactivating second level cache.\n"); | |
38 | cacheconf = 0; | |
39 | return; | |
40 | } | |
41 | ||
42 | sc_size = 128 << scsiz; | |
43 | printk("%dkb second level cache detected, deactivating.\n", sc_size); | |
44 | cacheconf = 0; | |
45 | } | |
46 | ||
47 | ||
48 | /* | |
49 | * A bit more gossip about the iron we're running on ... | |
50 | */ | |
51 | static inline void sni_pcimt_detect(void) | |
52 | { | |
53 | char boardtype[80]; | |
54 | unsigned char csmsr; | |
55 | char *p = boardtype; | |
56 | unsigned int asic; | |
57 | ||
58 | csmsr = *(volatile unsigned char *)PCIMT_CSMSR; | |
59 | ||
60 | p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300"); | |
61 | if ((csmsr & 0x80) == 0) | |
62 | p += sprintf(p, ", board revision %s", | |
63 | (csmsr & 0x20) ? "D" : "C"); | |
64 | asic = csmsr & 0x80; | |
65 | asic = (csmsr & 0x08) ? asic : !asic; | |
66 | p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1"); | |
67 | printk("%s.\n", boardtype); | |
68 | } | |
69 | ||
70 | #define PORT(_base,_irq) \ | |
71 | { \ | |
72 | .iobase = _base, \ | |
73 | .irq = _irq, \ | |
74 | .uartclk = 1843200, \ | |
75 | .iotype = UPIO_PORT, \ | |
76 | .flags = UPF_BOOT_AUTOCONF, \ | |
77 | } | |
78 | ||
79 | static struct plat_serial8250_port pcimt_data[] = { | |
80 | PORT(0x3f8, 4), | |
81 | PORT(0x2f8, 3), | |
82 | { }, | |
83 | }; | |
84 | ||
85 | static struct platform_device pcimt_serial8250_device = { | |
86 | .name = "serial8250", | |
87 | .id = PLAT8250_DEV_PLATFORM, | |
88 | .dev = { | |
89 | .platform_data = pcimt_data, | |
90 | }, | |
91 | }; | |
92 | ||
93 | static struct resource sni_io_resource = { | |
94 | .start = 0x00001000UL, | |
95 | .end = 0x03bfffffUL, | |
96 | .name = "PCIMT IO MEM", | |
97 | .flags = IORESOURCE_IO, | |
98 | }; | |
99 | ||
100 | static struct resource pcimt_io_resources[] = { | |
101 | { | |
102 | .start = 0x00, | |
103 | .end = 0x1f, | |
104 | .name = "dma1", | |
105 | .flags = IORESOURCE_BUSY | |
106 | }, { | |
107 | .start = 0x40, | |
108 | .end = 0x5f, | |
109 | .name = "timer", | |
110 | .flags = IORESOURCE_BUSY | |
111 | }, { | |
112 | .start = 0x60, | |
113 | .end = 0x6f, | |
114 | .name = "keyboard", | |
115 | .flags = IORESOURCE_BUSY | |
116 | }, { | |
117 | .start = 0x80, | |
118 | .end = 0x8f, | |
119 | .name = "dma page reg", | |
120 | .flags = IORESOURCE_BUSY | |
121 | }, { | |
122 | .start = 0xc0, | |
123 | .end = 0xdf, | |
124 | .name = "dma2", | |
125 | .flags = IORESOURCE_BUSY | |
126 | }, { | |
127 | .start = 0xcfc, | |
128 | .end = 0xcff, | |
129 | .name = "PCI config data", | |
130 | .flags = IORESOURCE_BUSY | |
131 | } | |
132 | }; | |
133 | ||
134 | static struct resource sni_mem_resource = { | |
135 | .start = 0x10000000UL, | |
136 | .end = 0xffffffffUL, | |
137 | .name = "PCIMT PCI MEM", | |
138 | .flags = IORESOURCE_MEM | |
139 | }; | |
140 | ||
141 | /* | |
142 | * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used | |
143 | * for other purposes. Be paranoid and allocate all of the before the PCI | |
144 | * code gets a chance to to map anything else there ... | |
145 | * | |
146 | * This leaves the following areas available: | |
147 | * | |
148 | * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory | |
149 | * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory | |
150 | * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory | |
151 | * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory | |
152 | * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory | |
153 | */ | |
154 | static struct resource pcimt_mem_resources[] = { | |
155 | { | |
156 | .start = 0x100a0000, | |
157 | .end = 0x100bffff, | |
158 | .name = "Video RAM area", | |
159 | .flags = IORESOURCE_BUSY | |
160 | }, { | |
161 | .start = 0x100c0000, | |
162 | .end = 0x100fffff, | |
163 | .name = "ISA Reserved", | |
164 | .flags = IORESOURCE_BUSY | |
165 | }, { | |
166 | .start = 0x14000000, | |
167 | .end = 0x17bfffff, | |
168 | .name = "PCI IO", | |
169 | .flags = IORESOURCE_BUSY | |
170 | }, { | |
171 | .start = 0x17c00000, | |
172 | .end = 0x17ffffff, | |
173 | .name = "Cache Replacement Area", | |
174 | .flags = IORESOURCE_BUSY | |
175 | }, { | |
176 | .start = 0x1a000000, | |
177 | .end = 0x1a000003, | |
178 | .name = "PCI INT Acknowledge", | |
179 | .flags = IORESOURCE_BUSY | |
180 | }, { | |
181 | .start = 0x1fc00000, | |
182 | .end = 0x1fc7ffff, | |
183 | .name = "Boot PROM", | |
184 | .flags = IORESOURCE_BUSY | |
185 | }, { | |
186 | .start = 0x1fc80000, | |
187 | .end = 0x1fcfffff, | |
188 | .name = "Diag PROM", | |
189 | .flags = IORESOURCE_BUSY | |
190 | }, { | |
191 | .start = 0x1fd00000, | |
192 | .end = 0x1fdfffff, | |
193 | .name = "X-Bus", | |
194 | .flags = IORESOURCE_BUSY | |
195 | }, { | |
196 | .start = 0x1fe00000, | |
197 | .end = 0x1fefffff, | |
198 | .name = "BIOS map", | |
199 | .flags = IORESOURCE_BUSY | |
200 | }, { | |
201 | .start = 0x1ff00000, | |
202 | .end = 0x1ff7ffff, | |
203 | .name = "NVRAM / EEPROM", | |
204 | .flags = IORESOURCE_BUSY | |
205 | }, { | |
206 | .start = 0x1fff0000, | |
207 | .end = 0x1fffefff, | |
208 | .name = "ASIC PCI", | |
209 | .flags = IORESOURCE_BUSY | |
210 | }, { | |
211 | .start = 0x1ffff000, | |
212 | .end = 0x1fffffff, | |
213 | .name = "MP Agent", | |
214 | .flags = IORESOURCE_BUSY | |
215 | }, { | |
216 | .start = 0x20000000, | |
217 | .end = 0x9fffffff, | |
218 | .name = "Main Memory", | |
219 | .flags = IORESOURCE_BUSY | |
220 | } | |
221 | }; | |
222 | ||
223 | static void __init sni_pcimt_resource_init(void) | |
224 | { | |
225 | int i; | |
226 | ||
227 | /* request I/O space for devices used on all i[345]86 PCs */ | |
228 | for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++) | |
229 | request_resource(&ioport_resource, pcimt_io_resources + i); | |
230 | ||
231 | /* request mem space for pcimt-specific devices */ | |
232 | for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++) | |
233 | request_resource(&sni_mem_resource, pcimt_mem_resources + i); | |
234 | ||
235 | ioport_resource.end = sni_io_resource.end; | |
236 | } | |
237 | ||
238 | extern struct pci_ops sni_pcimt_ops; | |
239 | ||
240 | static struct pci_controller sni_controller = { | |
241 | .pci_ops = &sni_pcimt_ops, | |
242 | .mem_resource = &sni_mem_resource, | |
243 | .mem_offset = 0x10000000UL, | |
244 | .io_resource = &sni_io_resource, | |
245 | .io_offset = 0x00000000UL | |
246 | }; | |
247 | ||
248 | static void enable_pcimt_irq(unsigned int irq) | |
249 | { | |
250 | unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); | |
251 | ||
252 | *(volatile u8 *) PCIMT_IRQSEL |= mask; | |
253 | } | |
254 | ||
255 | void disable_pcimt_irq(unsigned int irq) | |
256 | { | |
257 | unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); | |
258 | ||
259 | *(volatile u8 *) PCIMT_IRQSEL &= mask; | |
260 | } | |
261 | ||
262 | static void end_pcimt_irq(unsigned int irq) | |
263 | { | |
264 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
265 | enable_pcimt_irq(irq); | |
266 | } | |
267 | ||
268 | static struct irq_chip pcimt_irq_type = { | |
269 | .typename = "PCIMT", | |
270 | .ack = disable_pcimt_irq, | |
271 | .mask = disable_pcimt_irq, | |
272 | .mask_ack = disable_pcimt_irq, | |
273 | .unmask = enable_pcimt_irq, | |
274 | .end = end_pcimt_irq, | |
275 | }; | |
276 | ||
277 | /* | |
278 | * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug | |
279 | * button interrupts. Later ... | |
280 | */ | |
281 | static void pcimt_hwint0(void) | |
282 | { | |
283 | panic("Received int0 but no handler yet ..."); | |
284 | } | |
285 | ||
286 | /* | |
287 | * hwint 1 deals with EISA and SCSI interrupts, | |
288 | * | |
289 | * The EISA_INT bit in CSITPEND is high active, all others are low active. | |
290 | */ | |
291 | static void pcimt_hwint1(void) | |
292 | { | |
293 | u8 pend = *(volatile char *)PCIMT_CSITPEND; | |
294 | unsigned long flags; | |
295 | ||
296 | if (pend & IT_EISA) { | |
297 | int irq; | |
298 | /* | |
299 | * Note: ASIC PCI's builtin interrupt achknowledge feature is | |
300 | * broken. Using it may result in loss of some or all i8259 | |
301 | * interupts, so don't use PCIMT_INT_ACKNOWLEDGE ... | |
302 | */ | |
303 | irq = i8259_irq(); | |
304 | if (unlikely(irq < 0)) | |
305 | return; | |
306 | ||
307 | do_IRQ(irq); | |
308 | } | |
309 | ||
310 | if (!(pend & IT_SCSI)) { | |
311 | flags = read_c0_status(); | |
312 | clear_c0_status(ST0_IM); | |
313 | do_IRQ(PCIMT_IRQ_SCSI); | |
314 | write_c0_status(flags); | |
315 | } | |
316 | } | |
317 | ||
318 | /* | |
319 | * hwint 3 should deal with the PCI A - D interrupts, | |
320 | */ | |
321 | static void pcimt_hwint3(void) | |
322 | { | |
323 | u8 pend = *(volatile char *)PCIMT_CSITPEND; | |
324 | int irq; | |
325 | ||
326 | pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD); | |
327 | pend ^= (IT_INTA | IT_INTB | IT_INTC | IT_INTD); | |
328 | clear_c0_status(IE_IRQ3); | |
329 | irq = PCIMT_IRQ_INT2 + ffs(pend) - 1; | |
330 | do_IRQ(irq); | |
331 | set_c0_status(IE_IRQ3); | |
332 | } | |
333 | ||
334 | static void sni_pcimt_hwint(void) | |
335 | { | |
336 | u32 pending = (read_c0_cause() & read_c0_status()); | |
337 | ||
338 | if (pending & C_IRQ5) | |
339 | do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 7); | |
340 | else if (pending & C_IRQ4) | |
341 | do_IRQ (SNI_MIPS_IRQ_CPU_BASE + 6); | |
342 | else if (pending & C_IRQ3) | |
343 | pcimt_hwint3(); | |
344 | else if (pending & C_IRQ1) | |
345 | pcimt_hwint1(); | |
346 | else if (pending & C_IRQ0) { | |
347 | pcimt_hwint0(); | |
348 | } | |
349 | } | |
350 | ||
351 | void __init sni_pcimt_irq_init(void) | |
352 | { | |
353 | int i; | |
354 | ||
355 | *(volatile u8 *) PCIMT_IRQSEL = IT_ETH | IT_EISA; | |
356 | mips_cpu_irq_init(); | |
357 | /* Actually we've got more interrupts to handle ... */ | |
358 | for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++) | |
359 | set_irq_chip(i, &pcimt_irq_type); | |
360 | sni_hwint = sni_pcimt_hwint; | |
361 | change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3); | |
362 | } | |
363 | ||
364 | void sni_pcimt_init(void) | |
365 | { | |
366 | sni_pcimt_resource_init(); | |
367 | sni_pcimt_detect(); | |
368 | sni_pcimt_sc_init(); | |
369 | rtc_mips_get_time = mc146818_get_cmos_time; | |
370 | rtc_mips_set_time = mc146818_set_rtc_mmss; | |
371 | board_time_init = sni_cpu_time_init; | |
372 | #ifdef CONFIG_PCI | |
373 | register_pci_controller(&sni_controller); | |
374 | #endif | |
375 | } | |
376 | ||
377 | static int __init snirm_pcimt_setup_devinit(void) | |
378 | { | |
379 | switch (sni_brd_type) { | |
380 | case SNI_BRD_PCI_MTOWER: | |
381 | case SNI_BRD_PCI_DESKTOP: | |
382 | case SNI_BRD_PCI_MTOWER_CPLUS: | |
383 | platform_device_register(&pcimt_serial8250_device); | |
384 | break; | |
385 | } | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | device_initcall(snirm_pcimt_setup_devinit); |