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1 | /* |
2 | * Interface for smsc fdc48m81x Super IO chip | |
3 | * | |
4 | * Author: MontaVista Software, Inc. source@mvista.com | |
5 | * | |
6 | * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | * | |
11 | * Copyright 2004 (c) MontaVista Software, Inc. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/types.h> | |
15 | #include <asm/io.h> | |
16 | #include <asm/tx4927/smsc_fdc37m81x.h> | |
17 | ||
18 | #define DEBUG | |
19 | ||
20 | /* Common Registers */ | |
21 | #define SMSC_FDC37M81X_CONFIG_INDEX 0x00 | |
22 | #define SMSC_FDC37M81X_CONFIG_DATA 0x01 | |
23 | #define SMSC_FDC37M81X_CONF 0x02 | |
24 | #define SMSC_FDC37M81X_INDEX 0x03 | |
25 | #define SMSC_FDC37M81X_DNUM 0x07 | |
26 | #define SMSC_FDC37M81X_DID 0x20 | |
27 | #define SMSC_FDC37M81X_DREV 0x21 | |
28 | #define SMSC_FDC37M81X_PCNT 0x22 | |
29 | #define SMSC_FDC37M81X_PMGT 0x23 | |
30 | #define SMSC_FDC37M81X_OSC 0x24 | |
31 | #define SMSC_FDC37M81X_CONFPA0 0x26 | |
32 | #define SMSC_FDC37M81X_CONFPA1 0x27 | |
33 | #define SMSC_FDC37M81X_TEST4 0x2B | |
34 | #define SMSC_FDC37M81X_TEST5 0x2C | |
35 | #define SMSC_FDC37M81X_TEST1 0x2D | |
36 | #define SMSC_FDC37M81X_TEST2 0x2E | |
37 | #define SMSC_FDC37M81X_TEST3 0x2F | |
38 | ||
39 | /* Logical device numbers */ | |
40 | #define SMSC_FDC37M81X_FDD 0x00 | |
41 | #define SMSC_FDC37M81X_SERIAL1 0x04 | |
42 | #define SMSC_FDC37M81X_SERIAL2 0x05 | |
43 | #define SMSC_FDC37M81X_KBD 0x07 | |
44 | ||
45 | /* Logical device Config Registers */ | |
46 | #define SMSC_FDC37M81X_ACTIVE 0x30 | |
47 | #define SMSC_FDC37M81X_BASEADDR0 0x60 | |
48 | #define SMSC_FDC37M81X_BASEADDR1 0x61 | |
49 | #define SMSC_FDC37M81X_INT 0x70 | |
50 | #define SMSC_FDC37M81X_INT2 0x72 | |
51 | #define SMSC_FDC37M81X_MODE 0xF0 | |
52 | ||
53 | /* Chip Config Values */ | |
54 | #define SMSC_FDC37M81X_CONFIG_ENTER 0x55 | |
55 | #define SMSC_FDC37M81X_CONFIG_EXIT 0xaa | |
56 | #define SMSC_FDC37M81X_CHIP_ID 0x4d | |
57 | ||
58 | static unsigned long g_smsc_fdc37m81x_base = 0; | |
59 | ||
60 | static inline unsigned char smsc_fdc37m81x_rd(unsigned char index) | |
61 | { | |
62 | outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); | |
63 | ||
64 | return inb(g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); | |
65 | } | |
66 | ||
67 | static inline void smsc_dc37m81x_wr(unsigned char index, unsigned char data) | |
68 | { | |
69 | outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); | |
70 | outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); | |
71 | } | |
72 | ||
73 | void smsc_fdc37m81x_config_beg(void) | |
74 | { | |
75 | if (g_smsc_fdc37m81x_base) { | |
76 | outb(SMSC_FDC37M81X_CONFIG_ENTER, | |
77 | g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); | |
78 | } | |
79 | } | |
80 | ||
81 | void smsc_fdc37m81x_config_end(void) | |
82 | { | |
83 | if (g_smsc_fdc37m81x_base) | |
84 | outb(SMSC_FDC37M81X_CONFIG_EXIT, | |
85 | g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); | |
86 | } | |
87 | ||
88 | u8 smsc_fdc37m81x_config_get(u8 reg) | |
89 | { | |
90 | u8 val = 0; | |
91 | ||
92 | if (g_smsc_fdc37m81x_base) | |
93 | val = smsc_fdc37m81x_rd(reg); | |
94 | ||
95 | return val; | |
96 | } | |
97 | ||
98 | void smsc_fdc37m81x_config_set(u8 reg, u8 val) | |
99 | { | |
100 | if (g_smsc_fdc37m81x_base) | |
101 | smsc_dc37m81x_wr(reg, val); | |
102 | } | |
103 | ||
104 | unsigned long __init smsc_fdc37m81x_init(unsigned long port) | |
105 | { | |
106 | const int field = sizeof(unsigned long) * 2; | |
107 | u8 chip_id; | |
108 | ||
109 | if (g_smsc_fdc37m81x_base) | |
110 | printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n", | |
111 | field, g_smsc_fdc37m81x_base); | |
112 | ||
113 | g_smsc_fdc37m81x_base = port; | |
114 | ||
115 | smsc_fdc37m81x_config_beg(); | |
116 | ||
117 | chip_id = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DID); | |
118 | if (chip_id == SMSC_FDC37M81X_CHIP_ID) | |
119 | smsc_fdc37m81x_config_end(); | |
120 | else { | |
121 | printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n", | |
122 | chip_id); | |
123 | g_smsc_fdc37m81x_base = 0; | |
124 | } | |
125 | ||
126 | return g_smsc_fdc37m81x_base; | |
127 | } | |
128 | ||
129 | #ifdef DEBUG | |
130 | void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg) | |
131 | { | |
132 | printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, | |
133 | smsc_fdc37m81x_rd(reg)); | |
134 | } | |
135 | ||
136 | void smsc_fdc37m81x_config_dump(void) | |
137 | { | |
138 | u8 orig; | |
139 | char *fname = "smsc_fdc37m81x_config_dump()"; | |
140 | ||
141 | smsc_fdc37m81x_config_beg(); | |
142 | ||
143 | orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM); | |
144 | ||
145 | printk("%s: common\n", fname); | |
146 | smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, | |
147 | SMSC_FDC37M81X_DNUM); | |
148 | smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, | |
149 | SMSC_FDC37M81X_DID); | |
150 | smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, | |
151 | SMSC_FDC37M81X_DREV); | |
152 | smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, | |
153 | SMSC_FDC37M81X_PCNT); | |
154 | smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE, | |
155 | SMSC_FDC37M81X_PMGT); | |
156 | ||
157 | printk("%s: keyboard\n", fname); | |
158 | smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD); | |
159 | smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, | |
160 | SMSC_FDC37M81X_ACTIVE); | |
161 | smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, | |
162 | SMSC_FDC37M81X_INT); | |
163 | smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, | |
164 | SMSC_FDC37M81X_INT2); | |
165 | smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD, | |
166 | SMSC_FDC37M81X_LDCR_F0); | |
167 | ||
168 | smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, orig); | |
169 | ||
170 | smsc_fdc37m81x_config_end(); | |
171 | } | |
172 | #endif |