[mirror_ubuntu-focal-kernel.git] / arch / mips / txx9 / generic / pci.c

/*
 * linux/arch/mips/txx9/pci.c
 *
 * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
 *	    linux/arch/mips/txx9/rbtx4938/setup.c,
 *	    and RBTX49xx patch from CELF patch archive.
 *
 * Copyright 2001-2005 MontaVista Software Inc.
 * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/io.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/pci.h>
#ifdef CONFIG_TOSHIBA_FPCIB0
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <asm/i8259.h>
#include <asm/txx9/smsc_fdc37m81x.h>
#endif

static int __init
early_read_config_word(struct pci_controller *hose,
		       int top_bus, int bus, int devfn, int offset, u16 *value)
{
	struct pci_bus fake_bus;

	fake_bus.number = bus;
	fake_bus.sysdata = hose;
	fake_bus.ops = hose->pci_ops;

	if (bus != top_bus)
		/* Fake a parent bus structure. */
		fake_bus.parent = &fake_bus;
	else
		fake_bus.parent = NULL;

	return pci_bus_read_config_word(&fake_bus, devfn, offset, value);
}

int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
			    int current_bus)
{
	u32 pci_devfn;
	unsigned short vid;
	int cap66 = -1;
	u16 stat;

	/* It seems SLC90E66 needs some time after PCI reset... */
	mdelay(80);

	pr_info("PCI: Checking 66MHz capabilities...\n");

	for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
		if (PCI_FUNC(pci_devfn))
			continue;
		if (early_read_config_word(hose, top_bus, current_bus,
					   pci_devfn, PCI_VENDOR_ID, &vid) !=
		    PCIBIOS_SUCCESSFUL)
			continue;
		if (vid == 0xffff)
			continue;

		/* check 66MHz capability */
		if (cap66 < 0)
			cap66 = 1;
		if (cap66) {
			early_read_config_word(hose, top_bus, current_bus,
					       pci_devfn, PCI_STATUS, &stat);
			if (!(stat & PCI_STATUS_66MHZ)) {
				pr_debug("PCI: %02x:%02x not 66MHz capable.\n",
					 current_bus, pci_devfn);
				cap66 = 0;
				break;
			}
		}
	}
	return cap66 > 0;
}

static struct resource primary_pci_mem_res[2] = {
	{ .name = "PCI MEM" },
	{ .name = "PCI MMIO" },
};
static struct resource primary_pci_io_res = { .name = "PCI IO" };
struct pci_controller txx9_primary_pcic = {
	.mem_resource = &primary_pci_mem_res[0],
	.io_resource = &primary_pci_io_res,
};

#ifdef CONFIG_64BIT
int txx9_pci_mem_high __initdata = 1;
#else
int txx9_pci_mem_high __initdata;
#endif

/*
 * allocate pci_controller and resources.
 * mem_base, io_base: physical address.	 0 for auto assignment.
 * mem_size and io_size means max size on auto assignment.
 * pcic must be &txx9_primary_pcic or NULL.
 */
struct pci_controller *__init
txx9_alloc_pci_controller(struct pci_controller *pcic,
			  unsigned long mem_base, unsigned long mem_size,
			  unsigned long io_base, unsigned long io_size)
{
	struct pcic {
		struct pci_controller c;
		struct resource r_mem[2];
		struct resource r_io;
	} *new = NULL;
	int min_size = 0x10000;

	if (!pcic) {
		new = kzalloc(sizeof(*new), GFP_KERNEL);
		if (!new)
			return NULL;
		new->r_mem[0].name = "PCI mem";
		new->r_mem[1].name = "PCI mmio";
		new->r_io.name = "PCI io";
		new->c.mem_resource = new->r_mem;
		new->c.io_resource = &new->r_io;
		pcic = &new->c;
	} else
		BUG_ON(pcic != &txx9_primary_pcic);
	pcic->io_resource->flags = IORESOURCE_IO;

	/*
	 * for auto assignment, first search a (big) region for PCI
	 * MEM, then search a region for PCI IO.
	 */
	if (mem_base) {
		pcic->mem_resource[0].start = mem_base;
		pcic->mem_resource[0].end = mem_base + mem_size - 1;
		if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
			goto free_and_exit;
	} else {
		unsigned long min = 0, max = 0x20000000; /* low 512MB */
		if (!mem_size) {
			/* default size for auto assignment */
			if (txx9_pci_mem_high)
				mem_size = 0x20000000;	/* mem:512M(max) */
			else
				mem_size = 0x08000000;	/* mem:128M(max) */
		}
		if (txx9_pci_mem_high) {
			min = 0x20000000;
			max = 0xe0000000;
		}
		/* search free region for PCI MEM */
		for (; mem_size >= min_size; mem_size /= 2) {
			if (allocate_resource(&iomem_resource,
					      &pcic->mem_resource[0],
					      mem_size, min, max,
					      mem_size, NULL, NULL) == 0)
				break;
		}
		if (mem_size < min_size)
			goto free_and_exit;
	}

	pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
	if (io_base) {
		pcic->mem_resource[1].start = io_base;
		pcic->mem_resource[1].end = io_base + io_size - 1;
		if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
			goto release_and_exit;
	} else {
		if (!io_size)
			/* default size for auto assignment */
			io_size = 0x01000000;	/* io:16M(max) */
		/* search free region for PCI IO in low 512MB */
		for (; io_size >= min_size; io_size /= 2) {
			if (allocate_resource(&iomem_resource,
					      &pcic->mem_resource[1],
					      io_size, 0, 0x20000000,
					      io_size, NULL, NULL) == 0)
				break;
		}
		if (io_size < min_size)
			goto release_and_exit;
		io_base = pcic->mem_resource[1].start;
	}

	pcic->mem_resource[0].flags = IORESOURCE_MEM;
	if (pcic == &txx9_primary_pcic &&
	    mips_io_port_base == (unsigned long)-1) {
		/* map ioport 0 to PCI I/O space address 0 */
		set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
		pcic->io_resource->start = 0;
		pcic->io_offset = 0;	/* busaddr == ioaddr */
		pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
	} else {
		/* physaddr to ioaddr */
		pcic->io_resource->start =
			io_base - (mips_io_port_base - IO_BASE);
		pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
		pcic->io_map_base = mips_io_port_base;
	}
	pcic->io_resource->end = pcic->io_resource->start + io_size - 1;

	pcic->mem_offset = 0;	/* busaddr == physaddr */

	pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1],
		&pcic->mem_resource[0]);

	/* register_pci_controller() will request MEM resource */
	release_resource(&pcic->mem_resource[0]);
	return pcic;
 release_and_exit:
	release_resource(&pcic->mem_resource[0]);
 free_and_exit:
	kfree(new);
	pr_err("PCI: Failed to allocate resources.\n");
	return NULL;
}

static int __init
txx9_arch_pci_init(void)
{
	PCIBIOS_MIN_IO = 0x8000;	/* reseve legacy I/O space */
	return 0;
}
arch_initcall(txx9_arch_pci_init);

/* IRQ/IDSEL mapping */
int txx9_pci_option =
#ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
	TXX9_PCI_OPT_PICMG |
#endif
	TXX9_PCI_OPT_CLK_AUTO;

enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;

#ifdef CONFIG_TOSHIBA_FPCIB0
static irqreturn_t i8259_interrupt(int irq, void *dev_id)
{
	int isairq;

	isairq = i8259_irq();
	if (unlikely(isairq <= I8259A_IRQ_BASE))
		return IRQ_NONE;
	generic_handle_irq(isairq);
	return IRQ_HANDLED;
}

static int txx9_i8259_irq_setup(int irq)
{
	int err;

	init_i8259_irqs();
	err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
			  "cascade(i8259)", (void *)(long)irq);
	if (!err)
		pr_info("PCI-ISA bridge PIC (irq %d)\n", irq);
	return err;
}

static void __ref quirk_slc90e66_bridge(struct pci_dev *dev)
{
	int irq;	/* PCI/ISA Bridge interrupt */
	u8 reg_64;
	u32 reg_b0;
	u8 reg_e1;
	irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
	if (!irq)
		return;
	txx9_i8259_irq_setup(irq);
	pci_read_config_byte(dev, 0x64, &reg_64);
	pci_read_config_dword(dev, 0xb0, &reg_b0);
	pci_read_config_byte(dev, 0xe1, &reg_e1);
	/* serial irq control */
	reg_64 = 0xd0;
	/* serial irq pin */
	reg_b0 |= 0x00010000;
	/* ide irq on isa14 */
	reg_e1 &= 0xf0;
	reg_e1 |= 0x0d;
	pci_write_config_byte(dev, 0x64, reg_64);
	pci_write_config_dword(dev, 0xb0, reg_b0);
	pci_write_config_byte(dev, 0xe1, reg_e1);

	smsc_fdc37m81x_init(0x3f0);
	smsc_fdc37m81x_config_beg();
	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
				  SMSC_FDC37M81X_KBD);
	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
				  1);
	smsc_fdc37m81x_config_end();
}

static void quirk_slc90e66_ide(struct pci_dev *dev)
{
	unsigned char dat;
	int regs[2] = {0x41, 0x43};
	int i;

	/* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
	pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat);
	/* enable SMSC SLC90E66 IDE */
	for (i = 0; i < ARRAY_SIZE(regs); i++) {
		pci_read_config_byte(dev, regs[i], &dat);
		pci_write_config_byte(dev, regs[i], dat | 0x80);
		pci_read_config_byte(dev, regs[i], &dat);
		pr_cont(" IDETIM%d %02x", i, dat);
	}
	pci_read_config_byte(dev, 0x5c, &dat);
	/*
	 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
	 *
	 * This line of code is intended to provide the user with a work
	 * around solution to the anomalies cited in SMSC's anomaly sheet
	 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
	 *
	 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
	 */
	dat |= 0x01;
	pci_write_config_byte(dev, 0x5c, dat);
	pci_read_config_byte(dev, 0x5c, &dat);
	pr_cont(" REG5C %02x\n", dat);
}
#endif /* CONFIG_TOSHIBA_FPCIB0 */

static void tc35815_fixup(struct pci_dev *dev)
{
	/* This device may have PM registers but not they are not supported. */
	if (dev->pm_cap) {
		dev_info(&dev->dev, "PM disabled\n");
		dev->pm_cap = 0;
	}
}

static void final_fixup(struct pci_dev *dev)
{
	unsigned char bist;

	/* Do build-in self test */
	if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
	    (bist & PCI_BIST_CAPABLE)) {
		unsigned long timeout;
		pci_set_power_state(dev, PCI_D0);
		pr_info("PCI: %s BIST...", pci_name(dev));
		pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
		timeout = jiffies + HZ * 2;	/* timeout after 2 sec */
		do {
			pci_read_config_byte(dev, PCI_BIST, &bist);
			if (time_after(jiffies, timeout))
				break;
		} while (bist & PCI_BIST_START);
		if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
			pr_cont("failed. (0x%x)\n", bist);
		else
			pr_cont("OK.\n");
	}
}

#ifdef CONFIG_TOSHIBA_FPCIB0
#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
	quirk_slc90e66_bridge);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
	quirk_slc90e66_ide);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
	quirk_slc90e66_ide);
#endif
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
			PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
			PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);

int pcibios_plat_dev_init(struct pci_dev *dev)
{
	return 0;
}

static int (*txx9_pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	return txx9_pci_map_irq(dev, slot, pin);
}

char * (*txx9_board_pcibios_setup)(char *str) __initdata;

char *__init txx9_pcibios_setup(char *str)
{
	if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
		return NULL;
	if (!strcmp(str, "picmg")) {
		/* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
		   (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
		txx9_pci_option |= TXX9_PCI_OPT_PICMG;
		return NULL;
	} else if (!strcmp(str, "nopicmg")) {
		/* non-PICMG compliant backplane (TOSHIBA
		   RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
		txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
		return NULL;
	} else if (!strncmp(str, "clk=", 4)) {
		char *val = str + 4;
		txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
		if (strcmp(val, "33") == 0)
			txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
		else if (strcmp(val, "66") == 0)
			txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
		else /* "auto" */
			txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
		return NULL;
	} else if (!strncmp(str, "err=", 4)) {
		if (!strcmp(str + 4, "panic"))
			txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
		else if (!strcmp(str + 4, "ignore"))
			txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
		return NULL;
	}

	txx9_pci_map_irq = txx9_board_vec->pci_map_irq;

	return str;
}
Commit	Line	Data
89d63fe1 AN	1	/*
	2	* linux/arch/mips/txx9/pci.c
	3	*
	4	* Based on linux/arch/mips/txx9/rbtx4927/setup.c,
70342287	5	* linux/arch/mips/txx9/rbtx4938/setup.c,
89d63fe1 AN	6	* and RBTX49xx patch from CELF patch archive.
	7	*
	8	* Copyright 2001-2005 MontaVista Software Inc.
	9	* Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
	10	* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
	11	*
	12	* This file is subject to the terms and conditions of the GNU General Public
	13	* License. See the file "COPYING" in the main directory of this archive
	14	* for more details.
	15	*/
	16	#include <linux/delay.h>
	17	#include <linux/jiffies.h>
	18	#include <linux/io.h>
edcaf1a6	19	#include <asm/txx9/generic.h>
89d63fe1 AN	20	#include <asm/txx9/pci.h>
	21	#ifdef CONFIG_TOSHIBA_FPCIB0
	22	#include <linux/interrupt.h>
5a0e3ad6	23	#include <linux/slab.h>
89d63fe1 AN	24	#include <asm/i8259.h>
	25	#include <asm/txx9/smsc_fdc37m81x.h>
	26	#endif
	27
	28	static int __init
	29	early_read_config_word(struct pci_controller *hose,
	30	int top_bus, int bus, int devfn, int offset, u16 *value)
	31	{
89d63fe1 AN	32	struct pci_bus fake_bus;
89d63fe1 AN	33
89d63fe1 AN	34	fake_bus.number = bus;
	35	fake_bus.sysdata = hose;
	36	fake_bus.ops = hose->pci_ops;
	37
	38	if (bus != top_bus)
	39	/* Fake a parent bus structure. */
	40	fake_bus.parent = &fake_bus;
	41	else
	42	fake_bus.parent = NULL;
	43
5f926354	44	return pci_bus_read_config_word(&fake_bus, devfn, offset, value);
89d63fe1 AN	45	}
	46
	47	int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
	48	int current_bus)
	49	{
	50	u32 pci_devfn;
	51	unsigned short vid;
	52	int cap66 = -1;
	53	u16 stat;
	54
	55	/* It seems SLC90E66 needs some time after PCI reset... */
	56	mdelay(80);
	57
2cec11d8	58	pr_info("PCI: Checking 66MHz capabilities...\n");
89d63fe1 AN	59
	60	for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
	61	if (PCI_FUNC(pci_devfn))
	62	continue;
	63	if (early_read_config_word(hose, top_bus, current_bus,
	64	pci_devfn, PCI_VENDOR_ID, &vid) !=
	65	PCIBIOS_SUCCESSFUL)
	66	continue;
	67	if (vid == 0xffff)
	68	continue;
	69
	70	/* check 66MHz capability */
	71	if (cap66 < 0)
	72	cap66 = 1;
	73	if (cap66) {
	74	early_read_config_word(hose, top_bus, current_bus,
	75	pci_devfn, PCI_STATUS, &stat);
	76	if (!(stat & PCI_STATUS_66MHZ)) {
2cec11d8 GU	77	pr_debug("PCI: %02x:%02x not 66MHz capable.\n",
2cec11d8 GU	78	current_bus, pci_devfn);
89d63fe1 AN	79	cap66 = 0;
	80	break;
	81	}
	82	}
	83	}
	84	return cap66 > 0;
	85	}
	86
	87	static struct resource primary_pci_mem_res[2] = {
	88	{ .name = "PCI MEM" },
	89	{ .name = "PCI MMIO" },
	90	};
	91	static struct resource primary_pci_io_res = { .name = "PCI IO" };
	92	struct pci_controller txx9_primary_pcic = {
	93	.mem_resource = &primary_pci_mem_res[0],
	94	.io_resource = &primary_pci_io_res,
	95	};
	96
	97	#ifdef CONFIG_64BIT
	98	int txx9_pci_mem_high __initdata = 1;
	99	#else
	100	int txx9_pci_mem_high __initdata;
	101	#endif
	102
	103	/*
	104	* allocate pci_controller and resources.
70342287	105	* mem_base, io_base: physical address. 0 for auto assignment.
89d63fe1 AN	106	* mem_size and io_size means max size on auto assignment.
	107	* pcic must be &txx9_primary_pcic or NULL.
	108	*/
	109	struct pci_controller *__init
	110	txx9_alloc_pci_controller(struct pci_controller *pcic,
	111	unsigned long mem_base, unsigned long mem_size,
	112	unsigned long io_base, unsigned long io_size)
	113	{
	114	struct pcic {
	115	struct pci_controller c;
	116	struct resource r_mem[2];
	117	struct resource r_io;
	118	} *new = NULL;
	119	int min_size = 0x10000;
	120
	121	if (!pcic) {
	122	new = kzalloc(sizeof(*new), GFP_KERNEL);
	123	if (!new)
	124	return NULL;
	125	new->r_mem[0].name = "PCI mem";
	126	new->r_mem[1].name = "PCI mmio";
	127	new->r_io.name = "PCI io";
	128	new->c.mem_resource = new->r_mem;
	129	new->c.io_resource = &new->r_io;
	130	pcic = &new->c;
	131	} else
	132	BUG_ON(pcic != &txx9_primary_pcic);
	133	pcic->io_resource->flags = IORESOURCE_IO;
	134
	135	/*
	136	* for auto assignment, first search a (big) region for PCI
	137	* MEM, then search a region for PCI IO.
	138	*/
	139	if (mem_base) {
	140	pcic->mem_resource[0].start = mem_base;
	141	pcic->mem_resource[0].end = mem_base + mem_size - 1;
	142	if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
	143	goto free_and_exit;
	144	} else {
	145	unsigned long min = 0, max = 0x20000000; /* low 512MB */
	146	if (!mem_size) {
	147	/* default size for auto assignment */
	148	if (txx9_pci_mem_high)
	149	mem_size = 0x20000000; /* mem:512M(max) */
	150	else
	151	mem_size = 0x08000000; /* mem:128M(max) */
	152	}
	153	if (txx9_pci_mem_high) {
	154	min = 0x20000000;
	155	max = 0xe0000000;
	156	}
	157	/* search free region for PCI MEM */
	158	for (; mem_size >= min_size; mem_size /= 2) {
	159	if (allocate_resource(&iomem_resource,
	160	&pcic->mem_resource[0],
	161	mem_size, min, max,
	162	mem_size, NULL, NULL) == 0)
	163	break;
	164	}
	165	if (mem_size < min_size)
	166	goto free_and_exit;
	167	}
	168
	169	pcic->mem_resource[1].flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
170	if (io_base) {
171	pcic->mem_resource[1].start = io_base;
172	pcic->mem_resource[1].end = io_base + io_size - 1;
173	if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
174	goto release_and_exit;
175	} else {
176	if (!io_size)
177	/* default size for auto assignment */
178	io_size = 0x01000000; /* io:16M(max) */
179	/* search free region for PCI IO in low 512MB */
180	for (; io_size >= min_size; io_size /= 2) {
181	if (allocate_resource(&iomem_resource,
182	&pcic->mem_resource[1],
183	io_size, 0, 0x20000000,
184	io_size, NULL, NULL) == 0)
185	break;
186	}
187	if (io_size < min_size)
188	goto release_and_exit;
189	io_base = pcic->mem_resource[1].start;
190	}
191
192	pcic->mem_resource[0].flags = IORESOURCE_MEM;
193	if (pcic == &txx9_primary_pcic &&
194	mips_io_port_base == (unsigned long)-1) {
195	/* map ioport 0 to PCI I/O space address 0 */
196	set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
197	pcic->io_resource->start = 0;
198	pcic->io_offset = 0; /* busaddr == ioaddr */
199	pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
200	} else {
201	/* physaddr to ioaddr */
202	pcic->io_resource->start =
203	io_base - (mips_io_port_base - IO_BASE);
204	pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
205	pcic->io_map_base = mips_io_port_base;
206	}
207	pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
208
209	pcic->mem_offset = 0; /* busaddr == physaddr */
210
2cec11d8 GU	211	pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1],
2cec11d8 GU	212	&pcic->mem_resource[0]);
89d63fe1 AN	213
	214	/* register_pci_controller() will request MEM resource */
	215	release_resource(&pcic->mem_resource[0]);
	216	return pcic;
	217	release_and_exit:
	218	release_resource(&pcic->mem_resource[0]);
	219	free_and_exit:
	220	kfree(new);
2cec11d8	221	pr_err("PCI: Failed to allocate resources.\n");
89d63fe1 AN	222	return NULL;
	223	}
	224
	225	static int __init
	226	txx9_arch_pci_init(void)
	227	{
	228	PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */
	229	return 0;
	230	}
	231	arch_initcall(txx9_arch_pci_init);
	232
	233	/* IRQ/IDSEL mapping */
	234	int txx9_pci_option =
	235	#ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
	236	TXX9_PCI_OPT_PICMG \|
	237	#endif
	238	TXX9_PCI_OPT_CLK_AUTO;
	239
	240	enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
	241
	242	#ifdef CONFIG_TOSHIBA_FPCIB0
	243	static irqreturn_t i8259_interrupt(int irq, void *dev_id)
	244	{
	245	int isairq;
	246
	247	isairq = i8259_irq();
	248	if (unlikely(isairq <= I8259A_IRQ_BASE))
	249	return IRQ_NONE;
	250	generic_handle_irq(isairq);
	251	return IRQ_HANDLED;
	252	}
	253
28eb0e46	254	static int txx9_i8259_irq_setup(int irq)
89d63fe1 AN	255	{
	256	int err;
	257
	258	init_i8259_irqs();
8b5690f8	259	err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
89d63fe1 AN	260	"cascade(i8259)", (void *)(long)irq);
89d63fe1 AN	261	if (!err)
2cec11d8	262	pr_info("PCI-ISA bridge PIC (irq %d)\n", irq);
89d63fe1 AN	263	return err;
	264	}
	265
bd721ea7	266	static void __ref quirk_slc90e66_bridge(struct pci_dev *dev)
89d63fe1 AN	267	{
	268	int irq; /* PCI/ISA Bridge interrupt */
	269	u8 reg_64;
	270	u32 reg_b0;
	271	u8 reg_e1;
	272	irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
	273	if (!irq)
	274	return;
	275	txx9_i8259_irq_setup(irq);
	276	pci_read_config_byte(dev, 0x64, &reg_64);
	277	pci_read_config_dword(dev, 0xb0, &reg_b0);
	278	pci_read_config_byte(dev, 0xe1, &reg_e1);
	279	/* serial irq control */
	280	reg_64 = 0xd0;
	281	/* serial irq pin */
	282	reg_b0 \|= 0x00010000;
	283	/* ide irq on isa14 */
	284	reg_e1 &= 0xf0;
	285	reg_e1 \|= 0x0d;
	286	pci_write_config_byte(dev, 0x64, reg_64);
	287	pci_write_config_dword(dev, 0xb0, reg_b0);
	288	pci_write_config_byte(dev, 0xe1, reg_e1);
	289
	290	smsc_fdc37m81x_init(0x3f0);
	291	smsc_fdc37m81x_config_beg();
	292	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
	293	SMSC_FDC37M81X_KBD);
	294	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
	295	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
	296	smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
	297	1);
	298	smsc_fdc37m81x_config_end();
	299	}
	300
28eb0e46	301	static void quirk_slc90e66_ide(struct pci_dev *dev)
89d63fe1 AN	302	{
	303	unsigned char dat;
	304	int regs[2] = {0x41, 0x43};
	305	int i;
	306
	307	/* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
	308	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
	309	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
2cec11d8	310	pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat);
89d63fe1 AN	311	/* enable SMSC SLC90E66 IDE */
	312	for (i = 0; i < ARRAY_SIZE(regs); i++) {
	313	pci_read_config_byte(dev, regs[i], &dat);
	314	pci_write_config_byte(dev, regs[i], dat \| 0x80);
	315	pci_read_config_byte(dev, regs[i], &dat);
2cec11d8	316	pr_cont(" IDETIM%d %02x", i, dat);
89d63fe1 AN	317	}
	318	pci_read_config_byte(dev, 0x5c, &dat);
	319	/*
	320	* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
	321	*
	322	* This line of code is intended to provide the user with a work
	323	* around solution to the anomalies cited in SMSC's anomaly sheet
	324	* entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
	325	*
	326	* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
	327	*/
	328	dat \|= 0x01;
ad6f9022	329	pci_write_config_byte(dev, 0x5c, dat);
89d63fe1	330	pci_read_config_byte(dev, 0x5c, &dat);
2cec11d8	331	pr_cont(" REG5C %02x\n", dat);
89d63fe1 AN	332	}
	333	#endif /* CONFIG_TOSHIBA_FPCIB0 */
	334
28eb0e46	335	static void tc35815_fixup(struct pci_dev *dev)
13680ade	336	{
02582e9b	337	/* This device may have PM registers but not they are not supported. */
13680ade AN	338	if (dev->pm_cap) {
	339	dev_info(&dev->dev, "PM disabled\n");
	340	dev->pm_cap = 0;
	341	}
	342	}
	343
28eb0e46	344	static void final_fixup(struct pci_dev *dev)
89d63fe1 AN	345	{
	346	unsigned char bist;
	347
	348	/* Do build-in self test */
	349	if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
	350	(bist & PCI_BIST_CAPABLE)) {
	351	unsigned long timeout;
	352	pci_set_power_state(dev, PCI_D0);
2cec11d8	353	pr_info("PCI: %s BIST...", pci_name(dev));
89d63fe1 AN	354	pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
	355	timeout = jiffies + HZ * 2; /* timeout after 2 sec */
	356	do {
	357	pci_read_config_byte(dev, PCI_BIST, &bist);
	358	if (time_after(jiffies, timeout))
	359	break;
	360	} while (bist & PCI_BIST_START);
	361	if (bist & (PCI_BIST_CODE_MASK \| PCI_BIST_START))
2cec11d8	362	pr_cont("failed. (0x%x)\n", bist);
89d63fe1	363	else
2cec11d8	364	pr_cont("OK.\n");
89d63fe1 AN	365	}
	366	}
	367
	368	#ifdef CONFIG_TOSHIBA_FPCIB0
	369	#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
	370	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
	371	quirk_slc90e66_bridge);
	372	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
	373	quirk_slc90e66_ide);
	374	DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
	375	quirk_slc90e66_ide);
	376	#endif
13680ade AN	377	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
	378	PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
	379	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
	380	PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
89d63fe1 AN	381	DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
89d63fe1 AN	382	DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
edcaf1a6 AN	383
	384	int pcibios_plat_dev_init(struct pci_dev *dev)
	385	{
	386	return 0;
	387	}
	388
19a8d6b7 LP	389	static int (txx9_pci_map_irq)(const struct pci_dev dev, u8 slot, u8 pin);
19a8d6b7 LP	390	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
edcaf1a6	391	{
19a8d6b7	392	return txx9_pci_map_irq(dev, slot, pin);
edcaf1a6	393	}
07517529	394
938ca516	395	char * (txx9_board_pcibios_setup)(char str) __initdata;
07517529	396
938ca516	397	char __init txx9_pcibios_setup(char str)
07517529 AN	398	{
	399	if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
	400	return NULL;
	401	if (!strcmp(str, "picmg")) {
	402	/* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
	403	(5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
	404	txx9_pci_option \|= TXX9_PCI_OPT_PICMG;
	405	return NULL;
	406	} else if (!strcmp(str, "nopicmg")) {
	407	/* non-PICMG compliant backplane (TOSHIBA
	408	RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
	409	txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
	410	return NULL;
	411	} else if (!strncmp(str, "clk=", 4)) {
	412	char *val = str + 4;
	413	txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
	414	if (strcmp(val, "33") == 0)
	415	txx9_pci_option \|= TXX9_PCI_OPT_CLK_33;
	416	else if (strcmp(val, "66") == 0)
	417	txx9_pci_option \|= TXX9_PCI_OPT_CLK_66;
	418	else /* "auto" */
	419	txx9_pci_option \|= TXX9_PCI_OPT_CLK_AUTO;
	420	return NULL;
	421	} else if (!strncmp(str, "err=", 4)) {
	422	if (!strcmp(str + 4, "panic"))
	423	txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
	424	else if (!strcmp(str + 4, "ignore"))
	425	txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
	426	return NULL;
	427	}
19a8d6b7 LP	428
	429	txx9_pci_map_irq = txx9_board_vec->pci_map_irq;
	430
07517529 AN	431	return str;
07517529 AN	432	}