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94a4c329 AN |
1 | /* |
2 | * TX4927 setup routines | |
3 | * Based on linux/arch/mips/txx9/rbtx4938/setup.c, | |
4 | * and RBTX49xx patch from CELF patch archive. | |
5 | * | |
6 | * 2003-2005 (c) MontaVista Software, Inc. | |
7 | * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 | |
8 | * | |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/delay.h> | |
94a4c329 | 16 | #include <linux/param.h> |
ce8e7411 | 17 | #include <linux/ptrace.h> |
51f607c7 | 18 | #include <linux/mtd/physmap.h> |
496a3b5c | 19 | #include <asm/reboot.h> |
ce8e7411 | 20 | #include <asm/traps.h> |
94a4c329 AN |
21 | #include <asm/txx9irq.h> |
22 | #include <asm/txx9tmr.h> | |
23 | #include <asm/txx9pio.h> | |
24 | #include <asm/txx9/generic.h> | |
25 | #include <asm/txx9/tx4927.h> | |
26 | ||
68314725 | 27 | static void __init tx4927_wdr_init(void) |
94a4c329 | 28 | { |
496a3b5c AN |
29 | /* report watchdog reset status */ |
30 | if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST) | |
31 | pr_warning("Watchdog reset detected at 0x%lx\n", | |
32 | read_c0_errorepc()); | |
94a4c329 AN |
33 | /* clear WatchDogReset (W1C) */ |
34 | tx4927_ccfg_set(TX4927_CCFG_WDRST); | |
35 | /* do reset on watchdog */ | |
36 | tx4927_ccfg_set(TX4927_CCFG_WR); | |
37 | } | |
38 | ||
68314725 AN |
39 | void __init tx4927_wdt_init(void) |
40 | { | |
41 | txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL); | |
42 | } | |
43 | ||
496a3b5c AN |
44 | static void tx4927_machine_restart(char *command) |
45 | { | |
46 | local_irq_disable(); | |
47 | pr_emerg("Rebooting (with %s watchdog reset)...\n", | |
48 | (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) ? | |
49 | "external" : "internal"); | |
50 | /* clear watchdog status */ | |
51 | tx4927_ccfg_set(TX4927_CCFG_WDRST); /* W1C */ | |
52 | txx9_wdt_now(TX4927_TMR_REG(2) & 0xfffffffffULL); | |
53 | while (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST)) | |
54 | ; | |
55 | mdelay(10); | |
56 | if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) { | |
57 | pr_emerg("Rebooting (with internal watchdog reset)...\n"); | |
58 | /* External WDRST failed. Do internal watchdog reset */ | |
59 | tx4927_ccfg_clear(TX4927_CCFG_WDREXEN); | |
60 | } | |
61 | /* fallback */ | |
62 | (*_machine_halt)(); | |
63 | } | |
64 | ||
ce8e7411 AN |
65 | void show_registers(struct pt_regs *regs); |
66 | static int tx4927_be_handler(struct pt_regs *regs, int is_fixup) | |
67 | { | |
68 | int data = regs->cp0_cause & 4; | |
69 | console_verbose(); | |
70 | pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc); | |
71 | pr_err("ccfg:%llx, toea:%llx\n", | |
72 | (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg), | |
73 | (unsigned long long)____raw_readq(&tx4927_ccfgptr->toea)); | |
74 | #ifdef CONFIG_PCI | |
75 | tx4927_report_pcic_status(); | |
76 | #endif | |
77 | show_registers(regs); | |
78 | panic("BusError!"); | |
79 | } | |
80 | static void __init tx4927_be_init(void) | |
81 | { | |
82 | board_be_handler = tx4927_be_handler; | |
83 | } | |
84 | ||
94a4c329 AN |
85 | static struct resource tx4927_sdram_resource[4]; |
86 | ||
87 | void __init tx4927_setup(void) | |
88 | { | |
89 | int i; | |
90 | __u32 divmode; | |
740ebe4a | 91 | unsigned int cpuclk = 0; |
94a4c329 AN |
92 | u64 ccfg; |
93 | ||
94 | txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE, | |
95 | TX4927_REG_SIZE); | |
d10e025f | 96 | set_c0_config(TX49_CONF_CWFON); |
94a4c329 AN |
97 | |
98 | /* SDRAMC,EBUSC are configured by PROM */ | |
99 | for (i = 0; i < 8; i++) { | |
100 | if (!(TX4927_EBUSC_CR(i) & 0x8)) | |
101 | continue; /* disabled */ | |
102 | txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i); | |
103 | txx9_ce_res[i].end = | |
104 | txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1; | |
105 | request_resource(&iomem_resource, &txx9_ce_res[i]); | |
106 | } | |
107 | ||
108 | /* clocks */ | |
109 | ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg); | |
110 | if (txx9_master_clock) { | |
111 | /* calculate gbus_clock and cpu_clock from master_clock */ | |
112 | divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK; | |
113 | switch (divmode) { | |
114 | case TX4927_CCFG_DIVMODE_8: | |
115 | case TX4927_CCFG_DIVMODE_10: | |
116 | case TX4927_CCFG_DIVMODE_12: | |
117 | case TX4927_CCFG_DIVMODE_16: | |
118 | txx9_gbus_clock = txx9_master_clock * 4; break; | |
119 | default: | |
120 | txx9_gbus_clock = txx9_master_clock; | |
121 | } | |
122 | switch (divmode) { | |
123 | case TX4927_CCFG_DIVMODE_2: | |
124 | case TX4927_CCFG_DIVMODE_8: | |
125 | cpuclk = txx9_gbus_clock * 2; break; | |
126 | case TX4927_CCFG_DIVMODE_2_5: | |
127 | case TX4927_CCFG_DIVMODE_10: | |
128 | cpuclk = txx9_gbus_clock * 5 / 2; break; | |
129 | case TX4927_CCFG_DIVMODE_3: | |
130 | case TX4927_CCFG_DIVMODE_12: | |
131 | cpuclk = txx9_gbus_clock * 3; break; | |
132 | case TX4927_CCFG_DIVMODE_4: | |
133 | case TX4927_CCFG_DIVMODE_16: | |
134 | cpuclk = txx9_gbus_clock * 4; break; | |
135 | } | |
136 | txx9_cpu_clock = cpuclk; | |
137 | } else { | |
138 | if (txx9_cpu_clock == 0) | |
139 | txx9_cpu_clock = 200000000; /* 200MHz */ | |
140 | /* calculate gbus_clock and master_clock from cpu_clock */ | |
141 | cpuclk = txx9_cpu_clock; | |
142 | divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK; | |
143 | switch (divmode) { | |
144 | case TX4927_CCFG_DIVMODE_2: | |
145 | case TX4927_CCFG_DIVMODE_8: | |
146 | txx9_gbus_clock = cpuclk / 2; break; | |
147 | case TX4927_CCFG_DIVMODE_2_5: | |
148 | case TX4927_CCFG_DIVMODE_10: | |
149 | txx9_gbus_clock = cpuclk * 2 / 5; break; | |
150 | case TX4927_CCFG_DIVMODE_3: | |
151 | case TX4927_CCFG_DIVMODE_12: | |
152 | txx9_gbus_clock = cpuclk / 3; break; | |
153 | case TX4927_CCFG_DIVMODE_4: | |
154 | case TX4927_CCFG_DIVMODE_16: | |
155 | txx9_gbus_clock = cpuclk / 4; break; | |
156 | } | |
157 | switch (divmode) { | |
158 | case TX4927_CCFG_DIVMODE_8: | |
159 | case TX4927_CCFG_DIVMODE_10: | |
160 | case TX4927_CCFG_DIVMODE_12: | |
161 | case TX4927_CCFG_DIVMODE_16: | |
162 | txx9_master_clock = txx9_gbus_clock / 4; break; | |
163 | default: | |
164 | txx9_master_clock = txx9_gbus_clock; | |
165 | } | |
166 | } | |
167 | /* change default value to udelay/mdelay take reasonable time */ | |
168 | loops_per_jiffy = txx9_cpu_clock / HZ / 2; | |
169 | ||
170 | /* CCFG */ | |
171 | tx4927_wdr_init(); | |
172 | /* clear BusErrorOnWrite flag (W1C) */ | |
173 | tx4927_ccfg_set(TX4927_CCFG_BEOW); | |
174 | /* enable Timeout BusError */ | |
175 | if (txx9_ccfg_toeon) | |
176 | tx4927_ccfg_set(TX4927_CCFG_TOE); | |
177 | ||
178 | /* DMA selection */ | |
179 | txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL); | |
180 | ||
181 | /* Use external clock for external arbiter */ | |
182 | if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB)) | |
183 | txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL); | |
184 | ||
185 | printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", | |
186 | txx9_pcode_str, | |
187 | (cpuclk + 500000) / 1000000, | |
188 | (txx9_master_clock + 500000) / 1000000, | |
189 | (__u32)____raw_readq(&tx4927_ccfgptr->crir), | |
190 | (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg), | |
191 | (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg)); | |
192 | ||
193 | printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); | |
194 | for (i = 0; i < 4; i++) { | |
195 | __u64 cr = TX4927_SDRAMC_CR(i); | |
196 | unsigned long base, size; | |
197 | if (!((__u32)cr & 0x00000400)) | |
198 | continue; /* disabled */ | |
199 | base = (unsigned long)(cr >> 49) << 21; | |
200 | size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21; | |
201 | printk(" CR%d:%016llx", i, (unsigned long long)cr); | |
202 | tx4927_sdram_resource[i].name = "SDRAM"; | |
203 | tx4927_sdram_resource[i].start = base; | |
204 | tx4927_sdram_resource[i].end = base + size - 1; | |
205 | tx4927_sdram_resource[i].flags = IORESOURCE_MEM; | |
206 | request_resource(&iomem_resource, &tx4927_sdram_resource[i]); | |
207 | } | |
208 | printk(" TR:%09llx\n", | |
209 | (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr)); | |
210 | ||
211 | /* TMR */ | |
212 | /* disable all timers */ | |
213 | for (i = 0; i < TX4927_NR_TMR; i++) | |
214 | txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL); | |
215 | ||
216 | /* PIO */ | |
217 | txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO); | |
218 | __raw_writel(0, &tx4927_pioptr->maskcpu); | |
219 | __raw_writel(0, &tx4927_pioptr->maskext); | |
496a3b5c AN |
220 | |
221 | _machine_restart = tx4927_machine_restart; | |
ce8e7411 | 222 | board_be_init = tx4927_be_init; |
94a4c329 AN |
223 | } |
224 | ||
225 | void __init tx4927_time_init(unsigned int tmrnr) | |
226 | { | |
227 | if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) | |
228 | txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL, | |
229 | TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr), | |
230 | TXX9_IMCLK); | |
231 | } | |
232 | ||
7779a5e0 | 233 | void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask) |
94a4c329 | 234 | { |
94a4c329 | 235 | int i; |
7779a5e0 AN |
236 | |
237 | for (i = 0; i < 2; i++) | |
238 | txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL, | |
239 | TXX9_IRQ_BASE + TX4927_IR_SIO(i), | |
240 | i, sclk, (1 << i) & cts_mask); | |
94a4c329 | 241 | } |
51f607c7 AN |
242 | |
243 | void __init tx4927_mtd_init(int ch) | |
244 | { | |
245 | struct physmap_flash_data pdata = { | |
246 | .width = TX4927_EBUSC_WIDTH(ch) / 8, | |
247 | }; | |
248 | unsigned long start = txx9_ce_res[ch].start; | |
249 | unsigned long size = txx9_ce_res[ch].end - start + 1; | |
250 | ||
251 | if (!(TX4927_EBUSC_CR(ch) & 0x8)) | |
252 | return; /* disabled */ | |
253 | txx9_physmap_flash_init(ch, start, size, &pdata); | |
254 | } | |
f6d9831b AN |
255 | |
256 | static void __init tx4927_stop_unused_modules(void) | |
257 | { | |
258 | __u64 pcfg, rst = 0, ckd = 0; | |
259 | char buf[128]; | |
260 | ||
261 | buf[0] = '\0'; | |
262 | local_irq_disable(); | |
263 | pcfg = ____raw_readq(&tx4927_ccfgptr->pcfg); | |
264 | if (!(pcfg & TX4927_PCFG_SEL2)) { | |
265 | rst |= TX4927_CLKCTR_ACLRST; | |
266 | ckd |= TX4927_CLKCTR_ACLCKD; | |
267 | strcat(buf, " ACLC"); | |
268 | } | |
269 | if (rst | ckd) { | |
270 | txx9_set64(&tx4927_ccfgptr->clkctr, rst); | |
271 | txx9_set64(&tx4927_ccfgptr->clkctr, ckd); | |
272 | } | |
273 | local_irq_enable(); | |
274 | if (buf[0]) | |
275 | pr_info("%s: stop%s\n", txx9_pcode_str, buf); | |
276 | } | |
277 | ||
278 | static int __init tx4927_late_init(void) | |
279 | { | |
280 | if (txx9_pcode != 0x4927) | |
281 | return -ENODEV; | |
282 | tx4927_stop_unused_modules(); | |
283 | return 0; | |
284 | } | |
285 | late_initcall(tx4927_late_init); |