[mirror_ubuntu-artful-kernel.git] / arch / mips / txx9 / generic / setup_tx4927.c

/*
 * TX4927 setup routines
 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
 *	    and RBTX49xx patch from CELF patch archive.
 *
 * 2003-2005 (c) MontaVista Software, Inc.
 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/param.h>
#include <asm/txx9irq.h>
#include <asm/txx9tmr.h>
#include <asm/txx9pio.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/tx4927.h>

static void __init tx4927_wdr_init(void)
{
	/* clear WatchDogReset (W1C) */
	tx4927_ccfg_set(TX4927_CCFG_WDRST);
	/* do reset on watchdog */
	tx4927_ccfg_set(TX4927_CCFG_WR);
}

void __init tx4927_wdt_init(void)
{
	txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
}

static struct resource tx4927_sdram_resource[4];

void __init tx4927_setup(void)
{
	int i;
	__u32 divmode;
	int cpuclk = 0;
	u64 ccfg;

	txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
			  TX4927_REG_SIZE);
	set_c0_config(TX49_CONF_CWFON);

	/* SDRAMC,EBUSC are configured by PROM */
	for (i = 0; i < 8; i++) {
		if (!(TX4927_EBUSC_CR(i) & 0x8))
			continue;	/* disabled */
		txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
		txx9_ce_res[i].end =
			txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
		request_resource(&iomem_resource, &txx9_ce_res[i]);
	}

	/* clocks */
	ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
	if (txx9_master_clock) {
		/* calculate gbus_clock and cpu_clock from master_clock */
		divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
		switch (divmode) {
		case TX4927_CCFG_DIVMODE_8:
		case TX4927_CCFG_DIVMODE_10:
		case TX4927_CCFG_DIVMODE_12:
		case TX4927_CCFG_DIVMODE_16:
			txx9_gbus_clock = txx9_master_clock * 4; break;
		default:
			txx9_gbus_clock = txx9_master_clock;
		}
		switch (divmode) {
		case TX4927_CCFG_DIVMODE_2:
		case TX4927_CCFG_DIVMODE_8:
			cpuclk = txx9_gbus_clock * 2; break;
		case TX4927_CCFG_DIVMODE_2_5:
		case TX4927_CCFG_DIVMODE_10:
			cpuclk = txx9_gbus_clock * 5 / 2; break;
		case TX4927_CCFG_DIVMODE_3:
		case TX4927_CCFG_DIVMODE_12:
			cpuclk = txx9_gbus_clock * 3; break;
		case TX4927_CCFG_DIVMODE_4:
		case TX4927_CCFG_DIVMODE_16:
			cpuclk = txx9_gbus_clock * 4; break;
		}
		txx9_cpu_clock = cpuclk;
	} else {
		if (txx9_cpu_clock == 0)
			txx9_cpu_clock = 200000000;	/* 200MHz */
		/* calculate gbus_clock and master_clock from cpu_clock */
		cpuclk = txx9_cpu_clock;
		divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
		switch (divmode) {
		case TX4927_CCFG_DIVMODE_2:
		case TX4927_CCFG_DIVMODE_8:
			txx9_gbus_clock = cpuclk / 2; break;
		case TX4927_CCFG_DIVMODE_2_5:
		case TX4927_CCFG_DIVMODE_10:
			txx9_gbus_clock = cpuclk * 2 / 5; break;
		case TX4927_CCFG_DIVMODE_3:
		case TX4927_CCFG_DIVMODE_12:
			txx9_gbus_clock = cpuclk / 3; break;
		case TX4927_CCFG_DIVMODE_4:
		case TX4927_CCFG_DIVMODE_16:
			txx9_gbus_clock = cpuclk / 4; break;
		}
		switch (divmode) {
		case TX4927_CCFG_DIVMODE_8:
		case TX4927_CCFG_DIVMODE_10:
		case TX4927_CCFG_DIVMODE_12:
		case TX4927_CCFG_DIVMODE_16:
			txx9_master_clock = txx9_gbus_clock / 4; break;
		default:
			txx9_master_clock = txx9_gbus_clock;
		}
	}
	/* change default value to udelay/mdelay take reasonable time */
	loops_per_jiffy = txx9_cpu_clock / HZ / 2;

	/* CCFG */
	tx4927_wdr_init();
	/* clear BusErrorOnWrite flag (W1C) */
	tx4927_ccfg_set(TX4927_CCFG_BEOW);
	/* enable Timeout BusError */
	if (txx9_ccfg_toeon)
		tx4927_ccfg_set(TX4927_CCFG_TOE);

	/* DMA selection */
	txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);

	/* Use external clock for external arbiter */
	if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
		txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);

	printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
	       txx9_pcode_str,
	       (cpuclk + 500000) / 1000000,
	       (txx9_master_clock + 500000) / 1000000,
	       (__u32)____raw_readq(&tx4927_ccfgptr->crir),
	       (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
	       (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));

	printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
	for (i = 0; i < 4; i++) {
		__u64 cr = TX4927_SDRAMC_CR(i);
		unsigned long base, size;
		if (!((__u32)cr & 0x00000400))
			continue;	/* disabled */
		base = (unsigned long)(cr >> 49) << 21;
		size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
		printk(" CR%d:%016llx", i, (unsigned long long)cr);
		tx4927_sdram_resource[i].name = "SDRAM";
		tx4927_sdram_resource[i].start = base;
		tx4927_sdram_resource[i].end = base + size - 1;
		tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
		request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
	}
	printk(" TR:%09llx\n",
	       (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));

	/* TMR */
	/* disable all timers */
	for (i = 0; i < TX4927_NR_TMR; i++)
		txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);

	/* PIO */
	txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
	__raw_writel(0, &tx4927_pioptr->maskcpu);
	__raw_writel(0, &tx4927_pioptr->maskext);
}

void __init tx4927_time_init(unsigned int tmrnr)
{
	if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
		txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
				     TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
				     TXX9_IMCLK);
}

void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
{
	int i;

	for (i = 0; i < 2; i++)
		txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL,
			      TXX9_IRQ_BASE + TX4927_IR_SIO(i),
			      i, sclk, (1 << i) & cts_mask);
}
Commit	Line	Data
94a4c329 AN	1	/*
	2	* TX4927 setup routines
	3	* Based on linux/arch/mips/txx9/rbtx4938/setup.c,
	4	* and RBTX49xx patch from CELF patch archive.
	5	*
	6	* 2003-2005 (c) MontaVista Software, Inc.
	7	* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/init.h>
	14	#include <linux/ioport.h>
	15	#include <linux/delay.h>
94a4c329 AN	16	#include <linux/param.h>
	17	#include <asm/txx9irq.h>
	18	#include <asm/txx9tmr.h>
	19	#include <asm/txx9pio.h>
	20	#include <asm/txx9/generic.h>
	21	#include <asm/txx9/tx4927.h>
	22
68314725	23	static void __init tx4927_wdr_init(void)
94a4c329 AN	24	{
	25	/* clear WatchDogReset (W1C) */
	26	tx4927_ccfg_set(TX4927_CCFG_WDRST);
	27	/* do reset on watchdog */
	28	tx4927_ccfg_set(TX4927_CCFG_WR);
	29	}
	30
68314725 AN	31	void __init tx4927_wdt_init(void)
	32	{
	33	txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
	34	}
	35
94a4c329 AN	36	static struct resource tx4927_sdram_resource[4];
	37
	38	void __init tx4927_setup(void)
	39	{
	40	int i;
	41	__u32 divmode;
	42	int cpuclk = 0;
	43	u64 ccfg;
	44
	45	txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
	46	TX4927_REG_SIZE);
d10e025f	47	set_c0_config(TX49_CONF_CWFON);
94a4c329 AN	48
	49	/* SDRAMC,EBUSC are configured by PROM */
	50	for (i = 0; i < 8; i++) {
	51	if (!(TX4927_EBUSC_CR(i) & 0x8))
	52	continue; /* disabled */
	53	txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
	54	txx9_ce_res[i].end =
	55	txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
	56	request_resource(&iomem_resource, &txx9_ce_res[i]);
	57	}
	58
	59	/* clocks */
	60	ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
	61	if (txx9_master_clock) {
	62	/* calculate gbus_clock and cpu_clock from master_clock */
	63	divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
	64	switch (divmode) {
	65	case TX4927_CCFG_DIVMODE_8:
	66	case TX4927_CCFG_DIVMODE_10:
	67	case TX4927_CCFG_DIVMODE_12:
	68	case TX4927_CCFG_DIVMODE_16:
	69	txx9_gbus_clock = txx9_master_clock * 4; break;
	70	default:
	71	txx9_gbus_clock = txx9_master_clock;
	72	}
	73	switch (divmode) {
	74	case TX4927_CCFG_DIVMODE_2:
	75	case TX4927_CCFG_DIVMODE_8:
	76	cpuclk = txx9_gbus_clock * 2; break;
	77	case TX4927_CCFG_DIVMODE_2_5:
	78	case TX4927_CCFG_DIVMODE_10:
	79	cpuclk = txx9_gbus_clock * 5 / 2; break;
	80	case TX4927_CCFG_DIVMODE_3:
	81	case TX4927_CCFG_DIVMODE_12:
	82	cpuclk = txx9_gbus_clock * 3; break;
	83	case TX4927_CCFG_DIVMODE_4:
	84	case TX4927_CCFG_DIVMODE_16:
	85	cpuclk = txx9_gbus_clock * 4; break;
	86	}
	87	txx9_cpu_clock = cpuclk;
	88	} else {
	89	if (txx9_cpu_clock == 0)
	90	txx9_cpu_clock = 200000000; /* 200MHz */
	91	/* calculate gbus_clock and master_clock from cpu_clock */
	92	cpuclk = txx9_cpu_clock;
	93	divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
	94	switch (divmode) {
	95	case TX4927_CCFG_DIVMODE_2:
	96	case TX4927_CCFG_DIVMODE_8:
	97	txx9_gbus_clock = cpuclk / 2; break;
	98	case TX4927_CCFG_DIVMODE_2_5:
	99	case TX4927_CCFG_DIVMODE_10:
	100	txx9_gbus_clock = cpuclk * 2 / 5; break;
	101	case TX4927_CCFG_DIVMODE_3:
	102	case TX4927_CCFG_DIVMODE_12:
	103	txx9_gbus_clock = cpuclk / 3; break;
	104	case TX4927_CCFG_DIVMODE_4:
	105	case TX4927_CCFG_DIVMODE_16:
	106	txx9_gbus_clock = cpuclk / 4; break;
	107	}
	108	switch (divmode) {
	109	case TX4927_CCFG_DIVMODE_8:
	110	case TX4927_CCFG_DIVMODE_10:
	111	case TX4927_CCFG_DIVMODE_12:
112	case TX4927_CCFG_DIVMODE_16:
113	txx9_master_clock = txx9_gbus_clock / 4; break;
114	default:
115	txx9_master_clock = txx9_gbus_clock;
116	}
117	}
118	/* change default value to udelay/mdelay take reasonable time */
119	loops_per_jiffy = txx9_cpu_clock / HZ / 2;
120
121	/* CCFG */
122	tx4927_wdr_init();
123	/* clear BusErrorOnWrite flag (W1C) */
124	tx4927_ccfg_set(TX4927_CCFG_BEOW);
125	/* enable Timeout BusError */
126	if (txx9_ccfg_toeon)
127	tx4927_ccfg_set(TX4927_CCFG_TOE);
128
129	/* DMA selection */
130	txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
131
132	/* Use external clock for external arbiter */
133	if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
134	txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
135
136	printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
137	txx9_pcode_str,
138	(cpuclk + 500000) / 1000000,
139	(txx9_master_clock + 500000) / 1000000,
140	(__u32)____raw_readq(&tx4927_ccfgptr->crir),
141	(unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
142	(unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
143
144	printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
145	for (i = 0; i < 4; i++) {
146	__u64 cr = TX4927_SDRAMC_CR(i);
147	unsigned long base, size;
148	if (!((__u32)cr & 0x00000400))
149	continue; /* disabled */
150	base = (unsigned long)(cr >> 49) << 21;
151	size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
152	printk(" CR%d:%016llx", i, (unsigned long long)cr);
153	tx4927_sdram_resource[i].name = "SDRAM";
154	tx4927_sdram_resource[i].start = base;
155	tx4927_sdram_resource[i].end = base + size - 1;
156	tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
157	request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
158	}
159	printk(" TR:%09llx\n",
160	(unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
161
162	/* TMR */
163	/* disable all timers */
164	for (i = 0; i < TX4927_NR_TMR; i++)
165	txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
166
167	/* PIO */
168	txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
169	__raw_writel(0, &tx4927_pioptr->maskcpu);
170	__raw_writel(0, &tx4927_pioptr->maskext);
171	}
172
173	void __init tx4927_time_init(unsigned int tmrnr)
174	{
175	if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
176	txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
177	TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
178	TXX9_IMCLK);
179	}
180
7779a5e0	181	void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
94a4c329	182	{
94a4c329	183	int i;
7779a5e0 AN	184
	185	for (i = 0; i < 2; i++)
	186	txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL,
	187	TXX9_IRQ_BASE + TX4927_IR_SIO(i),
	188	i, sclk, (1 << i) & cts_mask);
94a4c329	189	}