[mirror_ubuntu-artful-kernel.git] / arch / mips / txx9 / generic / setup_tx4939.c

/*
 * TX4939 setup routines
 * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
 *	    and RBTX49xx patch from CELF patch archive.
 *
 * 2003-2005 (c) MontaVista Software, Inc.
 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/notifier.h>
#include <linux/device.h>
#include <linux/ethtool.h>
#include <linux/param.h>
#include <linux/ptrace.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/traps.h>
#include <asm/txx9irq.h>
#include <asm/txx9tmr.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/ndfmc.h>
#include <asm/txx9/dmac.h>
#include <asm/txx9/tx4939.h>

static void __init tx4939_wdr_init(void)
{
	/* report watchdog reset status */
	if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
		pr_warn("Watchdog reset detected at 0x%lx\n",
			read_c0_errorepc());
	/* clear WatchDogReset (W1C) */
	tx4939_ccfg_set(TX4939_CCFG_WDRST);
	/* do reset on watchdog */
	tx4939_ccfg_set(TX4939_CCFG_WR);
}

void __init tx4939_wdt_init(void)
{
	txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
}

static void tx4939_machine_restart(char *command)
{
	local_irq_disable();
	pr_emerg("Rebooting (with %s watchdog reset)...\n",
		 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
		 "external" : "internal");
	/* clear watchdog status */
	tx4939_ccfg_set(TX4939_CCFG_WDRST);	/* W1C */
	txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
	while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
		;
	mdelay(10);
	if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
		pr_emerg("Rebooting (with internal watchdog reset)...\n");
		/* External WDRST failed.  Do internal watchdog reset */
		tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
	}
	/* fallback */
	(*_machine_halt)();
}

void show_registers(struct pt_regs *regs);
static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
{
	int data = regs->cp0_cause & 4;
	console_verbose();
	pr_err("%cBE exception at %#lx\n",
	       data ? 'D' : 'I', regs->cp0_epc);
	pr_err("ccfg:%llx, toea:%llx\n",
	       (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
	       (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
#ifdef CONFIG_PCI
	tx4927_report_pcic_status();
#endif
	show_registers(regs);
	panic("BusError!");
}
static void __init tx4939_be_init(void)
{
	board_be_handler = tx4939_be_handler;
}

static struct resource tx4939_sdram_resource[4];
static struct resource tx4939_sram_resource;
#define TX4939_SRAM_SIZE 0x800

void __init tx4939_add_memory_regions(void)
{
	int i;
	unsigned long start, size;
	u64 win;

	for (i = 0; i < 4; i++) {
		if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
			continue;
		win = ____raw_readq(&tx4939_ddrcptr->win[i]);
		start = (unsigned long)(win >> 48);
		size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
		add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
	}
}

void __init tx4939_setup(void)
{
	int i;
	__u32 divmode;
	__u64 pcfg;
	unsigned int cpuclk = 0;

	txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
			  TX4939_REG_SIZE);
	set_c0_config(TX49_CONF_CWFON);

	/* SDRAMC,EBUSC are configured by PROM */
	for (i = 0; i < 4; i++) {
		if (!(TX4939_EBUSC_CR(i) & 0x8))
			continue;	/* disabled */
		txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
		txx9_ce_res[i].end =
			txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
		request_resource(&iomem_resource, &txx9_ce_res[i]);
	}

	/* clocks */
	if (txx9_master_clock) {
		/* calculate cpu_clock from master_clock */
		divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
			TX4939_CCFG_MULCLK_MASK;
		cpuclk = txx9_master_clock * 20 / 2;
		switch (divmode) {
		case TX4939_CCFG_MULCLK_8:
			cpuclk = cpuclk / 3 * 4 /* / 6 *  8 */; break;
		case TX4939_CCFG_MULCLK_9:
			cpuclk = cpuclk / 2 * 3 /* / 6 *  9 */; break;
		case TX4939_CCFG_MULCLK_10:
			cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
		case TX4939_CCFG_MULCLK_11:
			cpuclk = cpuclk / 6 * 11; break;
		case TX4939_CCFG_MULCLK_12:
			cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
		case TX4939_CCFG_MULCLK_13:
			cpuclk = cpuclk / 6 * 13; break;
		case TX4939_CCFG_MULCLK_14:
			cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
		case TX4939_CCFG_MULCLK_15:
			cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
		}
		txx9_cpu_clock = cpuclk;
	} else {
		if (txx9_cpu_clock == 0)
			txx9_cpu_clock = 400000000;	/* 400MHz */
		/* calculate master_clock from cpu_clock */
		cpuclk = txx9_cpu_clock;
		divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
			TX4939_CCFG_MULCLK_MASK;
		switch (divmode) {
		case TX4939_CCFG_MULCLK_8:
			txx9_master_clock = cpuclk * 6 / 8; break;
		case TX4939_CCFG_MULCLK_9:
			txx9_master_clock = cpuclk * 6 / 9; break;
		case TX4939_CCFG_MULCLK_10:
			txx9_master_clock = cpuclk * 6 / 10; break;
		case TX4939_CCFG_MULCLK_11:
			txx9_master_clock = cpuclk * 6 / 11; break;
		case TX4939_CCFG_MULCLK_12:
			txx9_master_clock = cpuclk * 6 / 12; break;
		case TX4939_CCFG_MULCLK_13:
			txx9_master_clock = cpuclk * 6 / 13; break;
		case TX4939_CCFG_MULCLK_14:
			txx9_master_clock = cpuclk * 6 / 14; break;
		case TX4939_CCFG_MULCLK_15:
			txx9_master_clock = cpuclk * 6 / 15; break;
		}
		txx9_master_clock /= 10; /* * 2 / 20 */
	}
	/* calculate gbus_clock from cpu_clock */
	divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
		TX4939_CCFG_YDIVMODE_MASK;
	txx9_gbus_clock = txx9_cpu_clock;
	switch (divmode) {
	case TX4939_CCFG_YDIVMODE_2:
		txx9_gbus_clock /= 2; break;
	case TX4939_CCFG_YDIVMODE_3:
		txx9_gbus_clock /= 3; break;
	case TX4939_CCFG_YDIVMODE_5:
		txx9_gbus_clock /= 5; break;
	case TX4939_CCFG_YDIVMODE_6:
		txx9_gbus_clock /= 6; break;
	}
	/* change default value to udelay/mdelay take reasonable time */
	loops_per_jiffy = txx9_cpu_clock / HZ / 2;

	/* CCFG */
	tx4939_wdr_init();
	/* clear BusErrorOnWrite flag (W1C) */
	tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
	/* enable Timeout BusError */
	if (txx9_ccfg_toeon)
		tx4939_ccfg_set(TX4939_CCFG_TOE);

	/* DMA selection */
	txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);

	/* Use external clock for external arbiter */
	if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
		txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);

	pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
		txx9_pcode_str,
		(cpuclk + 500000) / 1000000,
		(txx9_master_clock + 500000) / 1000000,
		(txx9_gbus_clock + 500000) / 1000000,
		(__u32)____raw_readq(&tx4939_ccfgptr->crir),
		____raw_readq(&tx4939_ccfgptr->ccfg),
		____raw_readq(&tx4939_ccfgptr->pcfg));

	pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
		(__u32)____raw_readq(&tx4939_ddrcptr->winen));
	for (i = 0; i < 4; i++) {
		__u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
		if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
			continue;	/* disabled */
		pr_cont(" #%d:%016llx", i, win);
		tx4939_sdram_resource[i].name = "DDR SDRAM";
		tx4939_sdram_resource[i].start =
			(unsigned long)(win >> 48) << 20;
		tx4939_sdram_resource[i].end =
			((((unsigned long)(win >> 32) & 0xffff) + 1) <<
			 20) - 1;
		tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
		request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
	}
	pr_cont("\n");

	/* SRAM */
	if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
		unsigned int size = TX4939_SRAM_SIZE;
		tx4939_sram_resource.name = "SRAM";
		tx4939_sram_resource.start =
			(____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
			& ~(size - 1);
		tx4939_sram_resource.end =
			tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
		tx4939_sram_resource.flags = IORESOURCE_MEM;
		request_resource(&iomem_resource, &tx4939_sram_resource);
	}

	/* TMR */
	/* disable all timers */
	for (i = 0; i < TX4939_NR_TMR; i++)
		txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);

	/* set PCIC1 reset (required to prevent hangup on BIST) */
	txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
	pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
	if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
		mdelay(1);	/* at least 128 cpu clock */
		/* clear PCIC1 reset */
		txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
	} else {
		pr_info("%s: stop PCIC1\n", txx9_pcode_str);
		/* stop PCIC1 */
		txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
	}
	if (!(pcfg & TX4939_PCFG_ET0MODE)) {
		pr_info("%s: stop ETH0\n", txx9_pcode_str);
		txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
		txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
	}
	if (!(pcfg & TX4939_PCFG_ET1MODE)) {
		pr_info("%s: stop ETH1\n", txx9_pcode_str);
		txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
		txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
	}

	_machine_restart = tx4939_machine_restart;
	board_be_init = tx4939_be_init;
}

void __init tx4939_time_init(unsigned int tmrnr)
{
	if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
		txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
				     TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
				     TXX9_IMCLK);
}

void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
{
	int i;
	unsigned int ch_mask = 0;
	__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);

	cts_mask |= ~1; /* only SIO0 have RTS/CTS */
	if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
		cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
	if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
		ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
	if (pcfg & TX4939_PCFG_SIO3MODE)
		ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
	for (i = 0; i < 4; i++) {
		if ((1 << i) & ch_mask)
			continue;
		txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
			      TXX9_IRQ_BASE + TX4939_IR_SIO(i),
			      i, sclk, (1 << i) & cts_mask);
	}
}

#if IS_ENABLED(CONFIG_TC35815)
static u32 tx4939_get_eth_speed(struct net_device *dev)
{
	struct ethtool_link_ksettings cmd;

	if (__ethtool_get_link_ksettings(dev, &cmd))
		return 100;	/* default 100Mbps */

	return cmd.base.speed;
}

static int tx4939_netdev_event(struct notifier_block *this,
			       unsigned long event,
			       void *ptr)
{
	struct net_device *dev = netdev_notifier_info_to_dev(ptr);

	if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
		__u64 bit = 0;
		if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
			bit = TX4939_PCFG_SPEED0;
		else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
			bit = TX4939_PCFG_SPEED1;
		if (bit) {
			if (tx4939_get_eth_speed(dev) == 100)
				txx9_set64(&tx4939_ccfgptr->pcfg, bit);
			else
				txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
		}
	}
	return NOTIFY_DONE;
}

static struct notifier_block tx4939_netdev_notifier = {
	.notifier_call = tx4939_netdev_event,
	.priority = 1,
};

void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
{
	u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);

	if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
		txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
	if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
		txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
	register_netdevice_notifier(&tx4939_netdev_notifier);
}
#else
void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
{
}
#endif

void __init tx4939_mtd_init(int ch)
{
	struct physmap_flash_data pdata = {
		.width = TX4939_EBUSC_WIDTH(ch) / 8,
	};
	unsigned long start = txx9_ce_res[ch].start;
	unsigned long size = txx9_ce_res[ch].end - start + 1;

	if (!(TX4939_EBUSC_CR(ch) & 0x8))
		return; /* disabled */
	txx9_physmap_flash_init(ch, start, size, &pdata);
}

#define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
void __init tx4939_ata_init(void)
{
	static struct resource ata0_res[] = {
		{
			.start = TX4939_ATA_REG_PHYS(0),
			.end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
			.flags = IORESOURCE_MEM,
		}, {
			.start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
			.flags = IORESOURCE_IRQ,
		},
	};
	static struct resource ata1_res[] = {
		{
			.start = TX4939_ATA_REG_PHYS(1),
			.end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
			.flags = IORESOURCE_MEM,
		}, {
			.start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
			.flags = IORESOURCE_IRQ,
		},
	};
	static struct platform_device ata0_dev = {
		.name = "tx4939ide",
		.id = 0,
		.num_resources = ARRAY_SIZE(ata0_res),
		.resource = ata0_res,
	};
	static struct platform_device ata1_dev = {
		.name = "tx4939ide",
		.id = 1,
		.num_resources = ARRAY_SIZE(ata1_res),
		.resource = ata1_res,
	};
	__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);

	if (pcfg & TX4939_PCFG_ATA0MODE)
		platform_device_register(&ata0_dev);
	if ((pcfg & (TX4939_PCFG_ATA1MODE |
		     TX4939_PCFG_ET1MODE |
		     TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
		platform_device_register(&ata1_dev);
}

void __init tx4939_rtc_init(void)
{
	static struct resource res[] = {
		{
			.start = TX4939_RTC_REG & 0xfffffffffULL,
			.end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1,
			.flags = IORESOURCE_MEM,
		}, {
			.start = TXX9_IRQ_BASE + TX4939_IR_RTC,
			.flags = IORESOURCE_IRQ,
		},
	};
	static struct platform_device rtc_dev = {
		.name = "tx4939rtc",
		.id = -1,
		.num_resources = ARRAY_SIZE(res),
		.resource = res,
	};

	platform_device_register(&rtc_dev);
}

void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
			      unsigned char ch_mask, unsigned char wide_mask)
{
	struct txx9ndfmc_platform_data plat_data = {
		.shift = 1,
		.gbus_clock = txx9_gbus_clock,
		.hold = hold,
		.spw = spw,
		.flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD |
			 NDFMC_PLAT_FLAG_DUMMYWRITE,
		.ch_mask = ch_mask,
		.wide_mask = wide_mask,
	};
	txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
}

void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1)
{
	struct txx9dmac_platform_data plat_data = {
		.have_64bit_regs = true,
	};
	int i;

	for (i = 0; i < 2; i++) {
		plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
		txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL,
			       TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0),
			       &plat_data);
	}
}

void __init tx4939_aclc_init(void)
{
	u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);

	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC)
		txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL,
			       TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1);
}

void __init tx4939_sramc_init(void)
{
	if (tx4939_sram_resource.start)
		txx9_sramc_init(&tx4939_sram_resource);
}

void __init tx4939_rng_init(void)
{
	static struct resource res = {
		.start = TX4939_RNG_REG & 0xfffffffffULL,
		.end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1,
		.flags = IORESOURCE_MEM,
	};
	static struct platform_device pdev = {
		.name = "tx4939-rng",
		.id = -1,
		.num_resources = 1,
		.resource = &res,
	};

	platform_device_register(&pdev);
}

static void __init tx4939_stop_unused_modules(void)
{
	__u64 pcfg, rst = 0, ckd = 0;
	char buf[128];

	buf[0] = '\0';
	local_irq_disable();
	pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
	    TX4939_PCFG_I2SMODE_ACLC) {
		rst |= TX4939_CLKCTR_ACLRST;
		ckd |= TX4939_CLKCTR_ACLCKD;
		strcat(buf, " ACLC");
	}
	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
	    TX4939_PCFG_I2SMODE_I2S &&
	    (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
	    TX4939_PCFG_I2SMODE_I2S_ALT) {
		rst |= TX4939_CLKCTR_I2SRST;
		ckd |= TX4939_CLKCTR_I2SCKD;
		strcat(buf, " I2S");
	}
	if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
		rst |= TX4939_CLKCTR_ATA0RST;
		ckd |= TX4939_CLKCTR_ATA0CKD;
		strcat(buf, " ATA0");
	}
	if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
		rst |= TX4939_CLKCTR_ATA1RST;
		ckd |= TX4939_CLKCTR_ATA1CKD;
		strcat(buf, " ATA1");
	}
	if (pcfg & TX4939_PCFG_SPIMODE) {
		rst |= TX4939_CLKCTR_SPIRST;
		ckd |= TX4939_CLKCTR_SPICKD;
		strcat(buf, " SPI");
	}
	if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
		rst |= TX4939_CLKCTR_VPCRST;
		ckd |= TX4939_CLKCTR_VPCCKD;
		strcat(buf, " VPC");
	}
	if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
		rst |= TX4939_CLKCTR_SIO2RST;
		ckd |= TX4939_CLKCTR_SIO2CKD;
		strcat(buf, " SIO2");
	}
	if (pcfg & TX4939_PCFG_SIO3MODE) {
		rst |= TX4939_CLKCTR_SIO3RST;
		ckd |= TX4939_CLKCTR_SIO3CKD;
		strcat(buf, " SIO3");
	}
	if (rst | ckd) {
		txx9_set64(&tx4939_ccfgptr->clkctr, rst);
		txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
	}
	local_irq_enable();
	if (buf[0])
		pr_info("%s: stop%s\n", txx9_pcode_str, buf);
}

static int __init tx4939_late_init(void)
{
	if (txx9_pcode != 0x4939)
		return -ENODEV;
	tx4939_stop_unused_modules();
	return 0;
}
late_initcall(tx4939_late_init);
Commit	Line	Data
0dcdbe6a AN	1	/*
	2	* TX4939 setup routines
	3	* Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
	4	* and RBTX49xx patch from CELF patch archive.
	5	*
	6	* 2003-2005 (c) MontaVista Software, Inc.
	7	* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/init.h>
	14	#include <linux/ioport.h>
	15	#include <linux/delay.h>
	16	#include <linux/netdevice.h>
	17	#include <linux/notifier.h>
edbaa603	18	#include <linux/device.h>
0dcdbe6a AN	19	#include <linux/ethtool.h>
	20	#include <linux/param.h>
	21	#include <linux/ptrace.h>
	22	#include <linux/mtd/physmap.h>
4bacc687	23	#include <linux/platform_device.h>
0dcdbe6a AN	24	#include <asm/bootinfo.h>
	25	#include <asm/reboot.h>
	26	#include <asm/traps.h>
	27	#include <asm/txx9irq.h>
	28	#include <asm/txx9tmr.h>
	29	#include <asm/txx9/generic.h>
a591f5d3	30	#include <asm/txx9/ndfmc.h>
f48c8c95	31	#include <asm/txx9/dmac.h>
0dcdbe6a AN	32	#include <asm/txx9/tx4939.h>
	33
	34	static void __init tx4939_wdr_init(void)
	35	{
	36	/* report watchdog reset status */
	37	if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
7178d2cd JP	38	pr_warn("Watchdog reset detected at 0x%lx\n",
7178d2cd JP	39	read_c0_errorepc());
0dcdbe6a AN	40	/* clear WatchDogReset (W1C) */
	41	tx4939_ccfg_set(TX4939_CCFG_WDRST);
	42	/* do reset on watchdog */
	43	tx4939_ccfg_set(TX4939_CCFG_WR);
	44	}
	45
	46	void __init tx4939_wdt_init(void)
	47	{
	48	txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
	49	}
	50
	51	static void tx4939_machine_restart(char *command)
	52	{
	53	local_irq_disable();
	54	pr_emerg("Rebooting (with %s watchdog reset)...\n",
	55	(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
	56	"external" : "internal");
	57	/* clear watchdog status */
	58	tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
	59	txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
	60	while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
	61	;
	62	mdelay(10);
	63	if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
	64	pr_emerg("Rebooting (with internal watchdog reset)...\n");
	65	/* External WDRST failed. Do internal watchdog reset */
	66	tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
	67	}
	68	/* fallback */
	69	(*_machine_halt)();
	70	}
	71
	72	void show_registers(struct pt_regs *regs);
	73	static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
	74	{
	75	int data = regs->cp0_cause & 4;
	76	console_verbose();
	77	pr_err("%cBE exception at %#lx\n",
	78	data ? 'D' : 'I', regs->cp0_epc);
	79	pr_err("ccfg:%llx, toea:%llx\n",
	80	(unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
	81	(unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
	82	#ifdef CONFIG_PCI
	83	tx4927_report_pcic_status();
	84	#endif
	85	show_registers(regs);
	86	panic("BusError!");
	87	}
	88	static void __init tx4939_be_init(void)
	89	{
	90	board_be_handler = tx4939_be_handler;
	91	}
	92
	93	static struct resource tx4939_sdram_resource[4];
	94	static struct resource tx4939_sram_resource;
	95	#define TX4939_SRAM_SIZE 0x800
	96
	97	void __init tx4939_add_memory_regions(void)
	98	{
	99	int i;
	100	unsigned long start, size;
	101	u64 win;
	102
	103	for (i = 0; i < 4; i++) {
104	if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
105	continue;
106	win = ____raw_readq(&tx4939_ddrcptr->win[i]);
107	start = (unsigned long)(win >> 48);
108	size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
109	add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
110	}
111	}
112
113	void __init tx4939_setup(void)
114	{
115	int i;
116	__u32 divmode;
117	__u64 pcfg;
740ebe4a	118	unsigned int cpuclk = 0;
0dcdbe6a AN	119
	120	txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
	121	TX4939_REG_SIZE);
	122	set_c0_config(TX49_CONF_CWFON);
	123
	124	/* SDRAMC,EBUSC are configured by PROM */
	125	for (i = 0; i < 4; i++) {
	126	if (!(TX4939_EBUSC_CR(i) & 0x8))
	127	continue; /* disabled */
	128	txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
	129	txx9_ce_res[i].end =
	130	txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
	131	request_resource(&iomem_resource, &txx9_ce_res[i]);
	132	}
	133
	134	/* clocks */
	135	if (txx9_master_clock) {
	136	/* calculate cpu_clock from master_clock */
	137	divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
	138	TX4939_CCFG_MULCLK_MASK;
	139	cpuclk = txx9_master_clock * 20 / 2;
	140	switch (divmode) {
	141	case TX4939_CCFG_MULCLK_8:
	142	cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
	143	case TX4939_CCFG_MULCLK_9:
	144	cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
	145	case TX4939_CCFG_MULCLK_10:
	146	cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
	147	case TX4939_CCFG_MULCLK_11:
	148	cpuclk = cpuclk / 6 * 11; break;
	149	case TX4939_CCFG_MULCLK_12:
	150	cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
	151	case TX4939_CCFG_MULCLK_13:
	152	cpuclk = cpuclk / 6 * 13; break;
	153	case TX4939_CCFG_MULCLK_14:
	154	cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
	155	case TX4939_CCFG_MULCLK_15:
	156	cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
	157	}
	158	txx9_cpu_clock = cpuclk;
	159	} else {
	160	if (txx9_cpu_clock == 0)
	161	txx9_cpu_clock = 400000000; /* 400MHz */
	162	/* calculate master_clock from cpu_clock */
	163	cpuclk = txx9_cpu_clock;
	164	divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
	165	TX4939_CCFG_MULCLK_MASK;
	166	switch (divmode) {
	167	case TX4939_CCFG_MULCLK_8:
	168	txx9_master_clock = cpuclk * 6 / 8; break;
	169	case TX4939_CCFG_MULCLK_9:
	170	txx9_master_clock = cpuclk * 6 / 9; break;
	171	case TX4939_CCFG_MULCLK_10:
	172	txx9_master_clock = cpuclk * 6 / 10; break;
	173	case TX4939_CCFG_MULCLK_11:
	174	txx9_master_clock = cpuclk * 6 / 11; break;
	175	case TX4939_CCFG_MULCLK_12:
	176	txx9_master_clock = cpuclk * 6 / 12; break;
	177	case TX4939_CCFG_MULCLK_13:
	178	txx9_master_clock = cpuclk * 6 / 13; break;
	179	case TX4939_CCFG_MULCLK_14:
	180	txx9_master_clock = cpuclk * 6 / 14; break;
	181	case TX4939_CCFG_MULCLK_15:
	182	txx9_master_clock = cpuclk * 6 / 15; break;
183	}
184	txx9_master_clock /= 10; /* * 2 / 20 */
185	}
186	/* calculate gbus_clock from cpu_clock */
187	divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
188	TX4939_CCFG_YDIVMODE_MASK;
189	txx9_gbus_clock = txx9_cpu_clock;
190	switch (divmode) {
191	case TX4939_CCFG_YDIVMODE_2:
192	txx9_gbus_clock /= 2; break;
193	case TX4939_CCFG_YDIVMODE_3:
194	txx9_gbus_clock /= 3; break;
195	case TX4939_CCFG_YDIVMODE_5:
196	txx9_gbus_clock /= 5; break;
197	case TX4939_CCFG_YDIVMODE_6:
198	txx9_gbus_clock /= 6; break;
199	}
200	/* change default value to udelay/mdelay take reasonable time */
201	loops_per_jiffy = txx9_cpu_clock / HZ / 2;
202
203	/* CCFG */
204	tx4939_wdr_init();
205	/* clear BusErrorOnWrite flag (W1C) */
206	tx4939_ccfg_set(TX4939_CCFG_WDRST \| TX4939_CCFG_BEOW);
207	/* enable Timeout BusError */
208	if (txx9_ccfg_toeon)
209	tx4939_ccfg_set(TX4939_CCFG_TOE);
210
211	/* DMA selection */
212	txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
213
214	/* Use external clock for external arbiter */
215	if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
216	txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
217
218	pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
219	txx9_pcode_str,
220	(cpuclk + 500000) / 1000000,
221	(txx9_master_clock + 500000) / 1000000,
222	(txx9_gbus_clock + 500000) / 1000000,
223	(__u32)____raw_readq(&tx4939_ccfgptr->crir),
2cec11d8 GU	224	____raw_readq(&tx4939_ccfgptr->ccfg),
2cec11d8 GU	225	____raw_readq(&tx4939_ccfgptr->pcfg));
0dcdbe6a AN	226
	227	pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
	228	(__u32)____raw_readq(&tx4939_ddrcptr->winen));
	229	for (i = 0; i < 4; i++) {
	230	__u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
	231	if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
	232	continue; /* disabled */
2cec11d8	233	pr_cont(" #%d:%016llx", i, win);
0dcdbe6a AN	234	tx4939_sdram_resource[i].name = "DDR SDRAM";
	235	tx4939_sdram_resource[i].start =
	236	(unsigned long)(win >> 48) << 20;
	237	tx4939_sdram_resource[i].end =
	238	((((unsigned long)(win >> 32) & 0xffff) + 1) <<
	239	20) - 1;
	240	tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
	241	request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
	242	}
2cec11d8	243	pr_cont("\n");
0dcdbe6a AN	244
	245	/* SRAM */
	246	if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
	247	unsigned int size = TX4939_SRAM_SIZE;
	248	tx4939_sram_resource.name = "SRAM";
	249	tx4939_sram_resource.start =
	250	(____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
	251	& ~(size - 1);
	252	tx4939_sram_resource.end =
	253	tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
	254	tx4939_sram_resource.flags = IORESOURCE_MEM;
	255	request_resource(&iomem_resource, &tx4939_sram_resource);
	256	}
	257
	258	/* TMR */
	259	/* disable all timers */
	260	for (i = 0; i < TX4939_NR_TMR; i++)
	261	txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
	262
0dcdbe6a AN	263	/* set PCIC1 reset (required to prevent hangup on BIST) */
	264	txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
	265	pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
	266	if (pcfg & (TX4939_PCFG_ET0MODE \| TX4939_PCFG_ET1MODE)) {
	267	mdelay(1); /* at least 128 cpu clock */
	268	/* clear PCIC1 reset */
	269	txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
	270	} else {
	271	pr_info("%s: stop PCIC1\n", txx9_pcode_str);
	272	/* stop PCIC1 */
	273	txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
	274	}
	275	if (!(pcfg & TX4939_PCFG_ET0MODE)) {
	276	pr_info("%s: stop ETH0\n", txx9_pcode_str);
	277	txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
	278	txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
	279	}
	280	if (!(pcfg & TX4939_PCFG_ET1MODE)) {
	281	pr_info("%s: stop ETH1\n", txx9_pcode_str);
	282	txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
	283	txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
	284	}
	285
	286	_machine_restart = tx4939_machine_restart;
	287	board_be_init = tx4939_be_init;
	288	}
	289
	290	void __init tx4939_time_init(unsigned int tmrnr)
	291	{
	292	if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
	293	txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
	294	TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
	295	TXX9_IMCLK);
	296	}
	297
	298	void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
	299	{
	300	int i;
	301	unsigned int ch_mask = 0;
	302	__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
	303
70342287	304	cts_mask \|= ~1; /* only SIO0 have RTS/CTS */
0dcdbe6a AN	305	if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
	306	cts_mask \|= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
	307	if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
	308	ch_mask \|= 1 << 2; /* disable SIO2 by PCFG setting */
	309	if (pcfg & TX4939_PCFG_SIO3MODE)
	310	ch_mask \|= 1 << 3; /* disable SIO3 by PCFG setting */
	311	for (i = 0; i < 4; i++) {
	312	if ((1 << i) & ch_mask)
	313	continue;
	314	txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
	315	TXX9_IRQ_BASE + TX4939_IR_SIO(i),
	316	i, sclk, (1 << i) & cts_mask);
	317	}
	318	}
	319
b33b4407	320	#if IS_ENABLED(CONFIG_TC35815)
8ae6daca	321	static u32 tx4939_get_eth_speed(struct net_device *dev)
0dcdbe6a	322	{
091a9277 DD	323	struct ethtool_link_ksettings cmd;
	324
	325	if (__ethtool_get_link_ksettings(dev, &cmd))
8ae6daca DD	326	return 100; /* default 100Mbps */
8ae6daca DD	327
091a9277	328	return cmd.base.speed;
0dcdbe6a	329	}
8ae6daca	330
0dcdbe6a AN	331	static int tx4939_netdev_event(struct notifier_block *this,
	332	unsigned long event,
	333	void *ptr)
	334	{
351638e7 JP	335	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
351638e7 JP	336
0dcdbe6a AN	337	if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
	338	__u64 bit = 0;
	339	if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
	340	bit = TX4939_PCFG_SPEED0;
	341	else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
	342	bit = TX4939_PCFG_SPEED1;
	343	if (bit) {
8ae6daca	344	if (tx4939_get_eth_speed(dev) == 100)
0dcdbe6a AN	345	txx9_set64(&tx4939_ccfgptr->pcfg, bit);
	346	else
	347	txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
	348	}
	349	}
	350	return NOTIFY_DONE;
	351	}
	352
	353	static struct notifier_block tx4939_netdev_notifier = {
	354	.notifier_call = tx4939_netdev_event,
	355	.priority = 1,
	356	};
	357
	358	void __init tx4939_ethaddr_init(unsigned char addr0, unsigned char addr1)
	359	{
	360	u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
	361
	362	if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
	363	txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
	364	if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
	365	txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
	366	register_netdevice_notifier(&tx4939_netdev_notifier);
	367	}
	368	#else
	369	void __init tx4939_ethaddr_init(unsigned char addr0, unsigned char addr1)
	370	{
	371	}
	372	#endif
	373
	374	void __init tx4939_mtd_init(int ch)
	375	{
	376	struct physmap_flash_data pdata = {
	377	.width = TX4939_EBUSC_WIDTH(ch) / 8,
	378	};
	379	unsigned long start = txx9_ce_res[ch].start;
	380	unsigned long size = txx9_ce_res[ch].end - start + 1;
	381
	382	if (!(TX4939_EBUSC_CR(ch) & 0x8))
70342287	383	return; /* disabled */
0dcdbe6a AN	384	txx9_physmap_flash_init(ch, start, size, &pdata);
	385	}
	386
4bacc687 AN	387	#define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
	388	void __init tx4939_ata_init(void)
	389	{
	390	static struct resource ata0_res[] = {
	391	{
	392	.start = TX4939_ATA_REG_PHYS(0),
	393	.end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
	394	.flags = IORESOURCE_MEM,
	395	}, {
	396	.start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
	397	.flags = IORESOURCE_IRQ,
	398	},
	399	};
	400	static struct resource ata1_res[] = {
	401	{
	402	.start = TX4939_ATA_REG_PHYS(1),
	403	.end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
	404	.flags = IORESOURCE_MEM,
	405	}, {
	406	.start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
	407	.flags = IORESOURCE_IRQ,
	408	},
	409	};
	410	static struct platform_device ata0_dev = {
	411	.name = "tx4939ide",
	412	.id = 0,
	413	.num_resources = ARRAY_SIZE(ata0_res),
	414	.resource = ata0_res,
	415	};
	416	static struct platform_device ata1_dev = {
	417	.name = "tx4939ide",
	418	.id = 1,
	419	.num_resources = ARRAY_SIZE(ata1_res),
	420	.resource = ata1_res,
	421	};
	422	__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
	423
	424	if (pcfg & TX4939_PCFG_ATA0MODE)
	425	platform_device_register(&ata0_dev);
	426	if ((pcfg & (TX4939_PCFG_ATA1MODE \|
	427	TX4939_PCFG_ET1MODE \|
	428	TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
	429	platform_device_register(&ata1_dev);
	430	}
	431
65655b5a AN	432	void __init tx4939_rtc_init(void)
	433	{
	434	static struct resource res[] = {
	435	{
	436	.start = TX4939_RTC_REG & 0xfffffffffULL,
	437	.end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1,
	438	.flags = IORESOURCE_MEM,
	439	}, {
	440	.start = TXX9_IRQ_BASE + TX4939_IR_RTC,
	441	.flags = IORESOURCE_IRQ,
	442	},
	443	};
	444	static struct platform_device rtc_dev = {
	445	.name = "tx4939rtc",
	446	.id = -1,
	447	.num_resources = ARRAY_SIZE(res),
	448	.resource = res,
	449	};
	450
	451	platform_device_register(&rtc_dev);
	452	}
	453
a591f5d3 AN	454	void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
	455	unsigned char ch_mask, unsigned char wide_mask)
	456	{
	457	struct txx9ndfmc_platform_data plat_data = {
	458	.shift = 1,
	459	.gbus_clock = txx9_gbus_clock,
	460	.hold = hold,
	461	.spw = spw,
	462	.flags = NDFMC_PLAT_FLAG_NO_RSTR \| NDFMC_PLAT_FLAG_HOLDADD \|
	463	NDFMC_PLAT_FLAG_DUMMYWRITE,
	464	.ch_mask = ch_mask,
	465	.wide_mask = wide_mask,
	466	};
	467	txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
	468	}
	469
f48c8c95 AN	470	void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1)
	471	{
	472	struct txx9dmac_platform_data plat_data = {
	473	.have_64bit_regs = true,
	474	};
	475	int i;
	476
	477	for (i = 0; i < 2; i++) {
	478	plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
	479	txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL,
	480	TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0),
	481	&plat_data);
	482	}
	483	}
	484
742cd586 AN	485	void __init tx4939_aclc_init(void)
	486	{
	487	u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
	488
	489	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC)
	490	txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL,
	491	TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1);
	492	}
	493
c3b28ae2 AN	494	void __init tx4939_sramc_init(void)
	495	{
	496	if (tx4939_sram_resource.start)
	497	txx9_sramc_init(&tx4939_sram_resource);
	498	}
	499
923e3819 AN	500	void __init tx4939_rng_init(void)
	501	{
	502	static struct resource res = {
	503	.start = TX4939_RNG_REG & 0xfffffffffULL,
	504	.end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1,
	505	.flags = IORESOURCE_MEM,
	506	};
	507	static struct platform_device pdev = {
	508	.name = "tx4939-rng",
	509	.id = -1,
	510	.num_resources = 1,
	511	.resource = &res,
	512	};
	513
	514	platform_device_register(&pdev);
	515	}
	516
0dcdbe6a AN	517	static void __init tx4939_stop_unused_modules(void)
	518	{
	519	__u64 pcfg, rst = 0, ckd = 0;
	520	char buf[128];
	521
	522	buf[0] = '\0';
	523	local_irq_disable();
	524	pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
	525	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
	526	TX4939_PCFG_I2SMODE_ACLC) {
	527	rst \|= TX4939_CLKCTR_ACLRST;
	528	ckd \|= TX4939_CLKCTR_ACLCKD;
	529	strcat(buf, " ACLC");
	530	}
	531	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
	532	TX4939_PCFG_I2SMODE_I2S &&
	533	(pcfg & TX4939_PCFG_I2SMODE_MASK) !=
	534	TX4939_PCFG_I2SMODE_I2S_ALT) {
	535	rst \|= TX4939_CLKCTR_I2SRST;
	536	ckd \|= TX4939_CLKCTR_I2SCKD;
	537	strcat(buf, " I2S");
	538	}
	539	if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
	540	rst \|= TX4939_CLKCTR_ATA0RST;
	541	ckd \|= TX4939_CLKCTR_ATA0CKD;
	542	strcat(buf, " ATA0");
	543	}
	544	if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
	545	rst \|= TX4939_CLKCTR_ATA1RST;
	546	ckd \|= TX4939_CLKCTR_ATA1CKD;
	547	strcat(buf, " ATA1");
	548	}
	549	if (pcfg & TX4939_PCFG_SPIMODE) {
	550	rst \|= TX4939_CLKCTR_SPIRST;
	551	ckd \|= TX4939_CLKCTR_SPICKD;
	552	strcat(buf, " SPI");
	553	}
	554	if (!(pcfg & (TX4939_PCFG_VSSMODE \| TX4939_PCFG_VPSMODE))) {
	555	rst \|= TX4939_CLKCTR_VPCRST;
	556	ckd \|= TX4939_CLKCTR_VPCCKD;
	557	strcat(buf, " VPC");
	558	}
	559	if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
	560	rst \|= TX4939_CLKCTR_SIO2RST;
	561	ckd \|= TX4939_CLKCTR_SIO2CKD;
	562	strcat(buf, " SIO2");
	563	}
	564	if (pcfg & TX4939_PCFG_SIO3MODE) {
	565	rst \|= TX4939_CLKCTR_SIO3RST;
	566	ckd \|= TX4939_CLKCTR_SIO3CKD;
	567	strcat(buf, " SIO3");
	568	}
	569	if (rst \| ckd) {
	570	txx9_set64(&tx4939_ccfgptr->clkctr, rst);
	571	txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
	572	}
	573	local_irq_enable();
	574	if (buf[0])
	575	pr_info("%s: stop%s\n", txx9_pcode_str, buf);
	576	}
	577
	578	static int __init tx4939_late_init(void)
	579	{
	580	if (txx9_pcode != 0x4939)
581	return -ENODEV;
582	tx4939_stop_unused_modules();
583	return 0;
584	}
585	late_initcall(tx4939_late_init);