[mirror_ubuntu-artful-kernel.git] / arch / mips / txx9 / rbtx4938 / setup.c

/*
 * Setup pointers to hardware-dependent routines.
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
 */
#include <linux/init.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/gpio.h>
#include <linux/mtd/physmap.h>

#include <asm/reboot.h>
#include <asm/io.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/pci.h>
#include <asm/txx9/rbtx4938.h>
#include <linux/spi/spi.h>
#include <asm/txx9/spi.h>
#include <asm/txx9pio.h>

static void rbtx4938_machine_restart(char *command)
{
	local_irq_disable();
	writeb(1, rbtx4938_softresetlock_addr);
	writeb(1, rbtx4938_sfvol_addr);
	writeb(1, rbtx4938_softreset_addr);
	/* fallback */
	(*_machine_halt)();
}

static void __init rbtx4938_pci_setup(void)
{
#ifdef CONFIG_PCI
	int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
	struct pci_controller *c = &txx9_primary_pcic;

	register_pci_controller(c);

	if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
		txx9_pci_option =
			(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
			TXX9_PCI_OPT_CLK_66; /* already configured */

	/* Reset PCI Bus */
	writeb(0, rbtx4938_pcireset_addr);
	/* Reset PCIC */
	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_66)
		tx4938_pciclk66_setup();
	mdelay(10);
	/* clear PCIC reset */
	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	writeb(1, rbtx4938_pcireset_addr);
	iob();

	tx4938_report_pciclk();
	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_AUTO &&
	    txx9_pci66_check(c, 0, 0)) {
		/* Reset PCI Bus */
		writeb(0, rbtx4938_pcireset_addr);
		/* Reset PCIC */
		txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
		tx4938_pciclk66_setup();
		mdelay(10);
		/* clear PCIC reset */
		txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
		writeb(1, rbtx4938_pcireset_addr);
		iob();
		/* Reinitialize PCIC */
		tx4938_report_pciclk();
		tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	}

	if (__raw_readq(&tx4938_ccfgptr->pcfg) &
	    (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
		/* Reset PCIC1 */
		txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
		/* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
		if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
		      & TX4938_CCFG_PCI1DMD))
			tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
		mdelay(10);
		/* clear PCIC1 reset */
		txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
		tx4938_report_pci1clk();

		/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
		c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
		register_pci_controller(c);
		tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
	}
	tx4938_setup_pcierr_irq();
#endif /* CONFIG_PCI */
}

/* SPI support */

/* chip select for SPI devices */
#define SEEPROM1_CS	7	/* PIO7 */
#define SEEPROM2_CS	0	/* IOC */
#define SEEPROM3_CS	1	/* IOC */
#define SRTC_CS 2	/* IOC */
#define SPI_BUSNO	0

static int __init rbtx4938_ethaddr_init(void)
{
#ifdef CONFIG_PCI
	unsigned char dat[17];
	unsigned char sum;
	int i;

	/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
	if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
		pr_err("seeprom: read error.\n");
		return -ENODEV;
	} else {
		if (strcmp(dat, "MAC") != 0)
			pr_warn("seeprom: bad signature.\n");
		for (i = 0, sum = 0; i < sizeof(dat); i++)
			sum += dat[i];
		if (sum)
			pr_warn("seeprom: bad checksum.\n");
	}
	tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
#endif /* CONFIG_PCI */
	return 0;
}

static void __init rbtx4938_spi_setup(void)
{
	/* set SPI_SEL */
	txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
}

static struct resource rbtx4938_fpga_resource;

static void __init rbtx4938_time_init(void)
{
	tx4938_time_init(0);
}

static void __init rbtx4938_mem_setup(void)
{
	unsigned long long pcfg;

	if (txx9_master_clock == 0)
		txx9_master_clock = 25000000; /* 25MHz */

	tx4938_setup();

#ifdef CONFIG_PCI
	txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
	txx9_board_pcibios_setup = tx4927_pcibios_setup;
#else
	set_io_port_base(RBTX4938_ETHER_BASE);
#endif

	tx4938_sio_init(7372800, 0);

#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
	pr_info("PIOSEL: disabling both ATA and NAND selection\n");
	txx9_clear64(&tx4938_ccfgptr->pcfg,
		     TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
#endif

#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
	pr_info("PIOSEL: enabling NAND selection\n");
	txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
	txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
#endif

#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
	pr_info("PIOSEL: enabling ATA selection\n");
	txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
	txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
#endif

#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP
	pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
	pr_info("PIOSEL: NAND %s, ATA %s\n",
		(pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled",
		(pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled");
#endif

	rbtx4938_spi_setup();
	pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);	/* updated */
	/* fixup piosel */
	if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
	    TX4938_PCFG_ATA_SEL)
		writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
		       rbtx4938_piosel_addr);
	else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
		 TX4938_PCFG_NDF_SEL)
		writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
		       rbtx4938_piosel_addr);
	else
		writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
		       rbtx4938_piosel_addr);

	rbtx4938_fpga_resource.name = "FPGA Registers";
	rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
	rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
	rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
	if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
		pr_err("request resource for fpga failed\n");

	_machine_restart = rbtx4938_machine_restart;

	writeb(0xff, rbtx4938_led_addr);
	pr_info("RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
		readb(rbtx4938_fpga_rev_addr),
		readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
}

static void __init rbtx4938_ne_init(void)
{
	struct resource res[] = {
		{
			.start	= RBTX4938_RTL_8019_BASE,
			.end	= RBTX4938_RTL_8019_BASE + 0x20 - 1,
			.flags	= IORESOURCE_IO,
		}, {
			.start	= RBTX4938_RTL_8019_IRQ,
			.flags	= IORESOURCE_IRQ,
		}
	};
	platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
}

static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);

static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
				  int value)
{
	u8 val;
	unsigned long flags;
	spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
	val = readb(rbtx4938_spics_addr);
	if (value)
		val |= 1 << offset;
	else
		val &= ~(1 << offset);
	writeb(val, rbtx4938_spics_addr);
	mmiowb();
	spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
}

static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
				     unsigned int offset, int value)
{
	rbtx4938_spi_gpio_set(chip, offset, value);
	return 0;
}

static struct gpio_chip rbtx4938_spi_gpio_chip = {
	.set = rbtx4938_spi_gpio_set,
	.direction_output = rbtx4938_spi_gpio_dir_out,
	.label = "RBTX4938-SPICS",
	.base = 16,
	.ngpio = 3,
};

static int __init rbtx4938_spi_init(void)
{
	struct spi_board_info srtc_info = {
		.modalias = "rtc-rs5c348",
		.max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
		.bus_num = 0,
		.chip_select = 16 + SRTC_CS,
		/* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS  */
		.mode = SPI_MODE_1 | SPI_CS_HIGH,
	};
	spi_register_board_info(&srtc_info, 1);
	spi_eeprom_register(SPI_BUSNO, SEEPROM1_CS, 128);
	spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM2_CS, 128);
	spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM3_CS, 128);
	gpio_request(16 + SRTC_CS, "rtc-rs5c348");
	gpio_direction_output(16 + SRTC_CS, 0);
	gpio_request(SEEPROM1_CS, "seeprom1");
	gpio_direction_output(SEEPROM1_CS, 1);
	gpio_request(16 + SEEPROM2_CS, "seeprom2");
	gpio_direction_output(16 + SEEPROM2_CS, 1);
	gpio_request(16 + SEEPROM3_CS, "seeprom3");
	gpio_direction_output(16 + SEEPROM3_CS, 1);
	tx4938_spi_init(SPI_BUSNO);
	return 0;
}

static void __init rbtx4938_mtd_init(void)
{
	struct physmap_flash_data pdata = {
		.width = 4,
	};

	switch (readb(rbtx4938_bdipsw_addr) & 7) {
	case 0:
		/* Boot */
		txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
		/* System */
		txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
		break;
	case 1:
		/* System */
		txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
		/* Boot */
		txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
		break;
	case 2:
		/* Ext */
		txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
		/* System */
		txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
		/* Boot */
		txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
		break;
	case 3:
		/* Boot */
		txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
		/* System */
		txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
		break;
	}
}

static void __init rbtx4938_arch_init(void)
{
	txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
	gpiochip_add_data(&rbtx4938_spi_gpio_chip, NULL);
	rbtx4938_pci_setup();
	rbtx4938_spi_init();
}

static void __init rbtx4938_device_init(void)
{
	rbtx4938_ethaddr_init();
	rbtx4938_ne_init();
	tx4938_wdt_init();
	rbtx4938_mtd_init();
	/* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
	tx4938_ndfmc_init(10, 35);
	tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1);
	tx4938_dmac_init(0, 2);
	tx4938_aclc_init();
	platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
	tx4938_sramc_init();
	txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
}

struct txx9_board_vec rbtx4938_vec __initdata = {
	.system = "Toshiba RBTX4938",
	.prom_init = rbtx4938_prom_init,
	.mem_setup = rbtx4938_mem_setup,
	.irq_setup = rbtx4938_irq_setup,
	.time_init = rbtx4938_time_init,
	.device_init = rbtx4938_device_init,
	.arch_init = rbtx4938_arch_init,
#ifdef CONFIG_PCI
	.pci_map_irq = rbtx4938_pci_map_irq,
#endif
};
Commit	Line	Data
23fbee9d	1	/*
23fbee9d RB	2	* Setup pointers to hardware-dependent routines.
	3	* Copyright (C) 2000-2001 Toshiba Corporation
	4	*
	5	* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
	6	* terms of the GNU General Public License version 2. This program is
	7	* licensed "as is" without any warranty of any kind, whether express
	8	* or implied.
	9	*
	10	* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
	11	*/
23fbee9d RB	12	#include <linux/init.h>
	13	#include <linux/types.h>
	14	#include <linux/ioport.h>
23fbee9d	15	#include <linux/delay.h>
57e386ce	16	#include <linux/platform_device.h>
ff53d12c	17	#include <linux/gpio/driver.h>
4cad154b	18	#include <linux/gpio.h>
51f607c7	19	#include <linux/mtd/physmap.h>
fcdb27ad	20
23fbee9d	21	#include <asm/reboot.h>
23fbee9d	22	#include <asm/io.h>
89d63fe1 AN	23	#include <asm/txx9/generic.h>
89d63fe1 AN	24	#include <asm/txx9/pci.h>
22b1d707	25	#include <asm/txx9/rbtx4938.h>
f74cf6ff	26	#include <linux/spi/spi.h>
22b1d707	27	#include <asm/txx9/spi.h>
4cad154b	28	#include <asm/txx9pio.h>
23fbee9d	29
7b226094	30	static void rbtx4938_machine_restart(char *command)
23fbee9d RB	31	{
23fbee9d RB	32	local_irq_disable();
66140c8e AN	33	writeb(1, rbtx4938_softresetlock_addr);
	34	writeb(1, rbtx4938_sfvol_addr);
	35	writeb(1, rbtx4938_softreset_addr);
a49297e8 AN	36	/* fallback */
a49297e8 AN	37	(*_machine_halt)();
23fbee9d RB	38	}
23fbee9d RB	39
89d63fe1	40	static void __init rbtx4938_pci_setup(void)
23fbee9d	41	{
23fbee9d	42	#ifdef CONFIG_PCI
89d63fe1 AN	43	int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
89d63fe1 AN	44	struct pci_controller *c = &txx9_primary_pcic;
23fbee9d	45
89d63fe1	46	register_pci_controller(c);
23fbee9d	47
89d63fe1 AN	48	if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
	49	txx9_pci_option =
	50	(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) \|
	51	TXX9_PCI_OPT_CLK_66; /* already configured */
23fbee9d RB	52
23fbee9d RB	53	/* Reset PCI Bus */
66140c8e	54	writeb(0, rbtx4938_pcireset_addr);
23fbee9d	55	/* Reset PCIC */
89d63fe1 AN	56	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	57	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	58	TXX9_PCI_OPT_CLK_66)
23fbee9d RB	59	tx4938_pciclk66_setup();
	60	mdelay(10);
	61	/* clear PCIC reset */
89d63fe1	62	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
66140c8e	63	writeb(1, rbtx4938_pcireset_addr);
89d63fe1	64	iob();
23fbee9d RB	65
23fbee9d RB	66	tx4938_report_pciclk();
89d63fe1 AN	67	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	68	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	69	TXX9_PCI_OPT_CLK_AUTO &&
	70	txx9_pci66_check(c, 0, 0)) {
23fbee9d	71	/* Reset PCI Bus */
66140c8e	72	writeb(0, rbtx4938_pcireset_addr);
23fbee9d	73	/* Reset PCIC */
89d63fe1	74	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
23fbee9d RB	75	tx4938_pciclk66_setup();
	76	mdelay(10);
	77	/* clear PCIC reset */
89d63fe1	78	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
66140c8e	79	writeb(1, rbtx4938_pcireset_addr);
89d63fe1	80	iob();
23fbee9d RB	81	/* Reinitialize PCIC */
23fbee9d RB	82	tx4938_report_pciclk();
89d63fe1	83	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
23fbee9d RB	84	}
23fbee9d RB	85
89d63fe1 AN	86	if (__raw_readq(&tx4938_ccfgptr->pcfg) &
	87	(TX4938_PCFG_ETH0_SEL\|TX4938_PCFG_ETH1_SEL)) {
	88	/* Reset PCIC1 */
	89	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
	90	/* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
	91	if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
	92	& TX4938_CCFG_PCI1DMD))
	93	tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
	94	mdelay(10);
	95	/* clear PCIC1 reset */
	96	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
	97	tx4938_report_pci1clk();
	98
	99	/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
	100	c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
	101	register_pci_controller(c);
	102	tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
	103	}
455cc256	104	tx4938_setup_pcierr_irq();
23fbee9d	105	#endif /* CONFIG_PCI */
89d63fe1	106	}
23fbee9d RB	107
	108	/* SPI support */
	109
	110	/* chip select for SPI devices */
70342287 RB	111	#define SEEPROM1_CS 7 /* PIO7 */
	112	#define SEEPROM2_CS 0 /* IOC */
	113	#define SEEPROM3_CS 1 /* IOC */
	114	#define SRTC_CS 2 /* IOC */
d75a40e9	115	#define SPI_BUSNO 0
23fbee9d	116
f74cf6ff	117	static int __init rbtx4938_ethaddr_init(void)
23fbee9d	118	{
edcaf1a6	119	#ifdef CONFIG_PCI
2db30150	120	unsigned char dat[17];
f74cf6ff AN	121	unsigned char sum;
	122	int i;
	123
	124	/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
d75a40e9	125	if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
2cec11d8	126	pr_err("seeprom: read error.\n");
2db30150 AN	127	return -ENODEV;
2db30150 AN	128	} else {
f74cf6ff	129	if (strcmp(dat, "MAC") != 0)
2cec11d8	130	pr_warn("seeprom: bad signature.\n");
f74cf6ff AN	131	for (i = 0, sum = 0; i < sizeof(dat); i++)
	132	sum += dat[i];
	133	if (sum)
2cec11d8	134	pr_warn("seeprom: bad checksum.\n");
23fbee9d	135	}
c49f91f5	136	tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
edcaf1a6	137	#endif /* CONFIG_PCI */
23fbee9d RB	138	return 0;
23fbee9d RB	139	}
23fbee9d	140
23fbee9d RB	141	static void __init rbtx4938_spi_setup(void)
	142	{
	143	/* set SPI_SEL */
89d63fe1	144	txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
23fbee9d RB	145	}
	146
	147	static struct resource rbtx4938_fpga_resource;
23fbee9d	148
edcaf1a6	149	static void __init rbtx4938_time_init(void)
23fbee9d	150	{
94a4c329	151	tx4938_time_init(0);
23fbee9d RB	152	}
23fbee9d RB	153
edcaf1a6	154	static void __init rbtx4938_mem_setup(void)
23fbee9d RB	155	{
23fbee9d RB	156	unsigned long long pcfg;
23fbee9d	157
23fbee9d RB	158	if (txx9_master_clock == 0)
23fbee9d RB	159	txx9_master_clock = 25000000; /* 25MHz */
94a4c329 AN	160
	161	tx4938_setup();
	162
	163	#ifdef CONFIG_PCI
	164	txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
07517529	165	txx9_board_pcibios_setup = tx4927_pcibios_setup;
94a4c329	166	#else
23fbee9d RB	167	set_io_port_base(RBTX4938_ETHER_BASE);
	168	#endif
	169
7779a5e0	170	tx4938_sio_init(7372800, 0);
23fbee9d RB	171
23fbee9d RB	172	#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
e6332374	173	pr_info("PIOSEL: disabling both ATA and NAND selection\n");
89d63fe1 AN	174	txx9_clear64(&tx4938_ccfgptr->pcfg,
89d63fe1 AN	175	TX4938_PCFG_NDF_SEL \| TX4938_PCFG_ATA_SEL);
23fbee9d RB	176	#endif
	177
	178	#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
e6332374	179	pr_info("PIOSEL: enabling NAND selection\n");
89d63fe1 AN	180	txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
89d63fe1 AN	181	txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
23fbee9d RB	182	#endif
	183
	184	#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
e6332374	185	pr_info("PIOSEL: enabling ATA selection\n");
89d63fe1 AN	186	txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
89d63fe1 AN	187	txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
23fbee9d RB	188	#endif
23fbee9d RB	189
e6332374 AN	190	#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP
	191	pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
	192	pr_info("PIOSEL: NAND %s, ATA %s\n",
	193	(pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled",
	194	(pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled");
	195	#endif
	196
23fbee9d	197	rbtx4938_spi_setup();
89d63fe1	198	pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
23fbee9d RB	199	/* fixup piosel */
23fbee9d RB	200	if ((pcfg & (TX4938_PCFG_ATA_SEL \| TX4938_PCFG_NDF_SEL)) ==
66140c8e AN	201	TX4938_PCFG_ATA_SEL)
	202	writeb((readb(rbtx4938_piosel_addr) & 0x03) \| 0x04,
	203	rbtx4938_piosel_addr);
23fbee9d	204	else if ((pcfg & (TX4938_PCFG_ATA_SEL \| TX4938_PCFG_NDF_SEL)) ==
66140c8e AN	205	TX4938_PCFG_NDF_SEL)
	206	writeb((readb(rbtx4938_piosel_addr) & 0x03) \| 0x08,
	207	rbtx4938_piosel_addr);
	208	else
	209	writeb(readb(rbtx4938_piosel_addr) & ~(0x08 \| 0x04),
	210	rbtx4938_piosel_addr);
23fbee9d RB	211
	212	rbtx4938_fpga_resource.name = "FPGA Registers";
	213	rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
	214	rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
	215	rbtx4938_fpga_resource.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
8d795f2a	216	if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
2cec11d8	217	pr_err("request resource for fpga failed\n");
23fbee9d	218
23fbee9d	219	_machine_restart = rbtx4938_machine_restart;
23fbee9d	220
66140c8e	221	writeb(0xff, rbtx4938_led_addr);
2cec11d8 GU	222	pr_info("RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
	223	readb(rbtx4938_fpga_rev_addr),
	224	readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
23fbee9d RB	225	}
23fbee9d RB	226
bb72f1f7	227	static void __init rbtx4938_ne_init(void)
57e386ce AN	228	{
	229	struct resource res[] = {
	230	{
	231	.start = RBTX4938_RTL_8019_BASE,
	232	.end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
	233	.flags = IORESOURCE_IO,
	234	}, {
	235	.start = RBTX4938_RTL_8019_IRQ,
	236	.flags = IORESOURCE_IRQ,
	237	}
	238	};
bb72f1f7	239	platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
57e386ce	240	}
3896b054	241
3896b054 AN	242	static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
3896b054 AN	243
4cad154b AN	244	static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
4cad154b AN	245	int value)
3896b054 AN	246	{
	247	u8 val;
	248	unsigned long flags;
3896b054	249	spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
66140c8e	250	val = readb(rbtx4938_spics_addr);
3896b054	251	if (value)
4cad154b	252	val \|= 1 << offset;
3896b054	253	else
4cad154b	254	val &= ~(1 << offset);
66140c8e	255	writeb(val, rbtx4938_spics_addr);
3896b054 AN	256	mmiowb();
	257	spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
	258	}
	259
4cad154b AN	260	static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
4cad154b AN	261	unsigned int offset, int value)
3896b054	262	{
4cad154b	263	rbtx4938_spi_gpio_set(chip, offset, value);
3896b054 AN	264	return 0;
	265	}
	266
4cad154b AN	267	static struct gpio_chip rbtx4938_spi_gpio_chip = {
	268	.set = rbtx4938_spi_gpio_set,
	269	.direction_output = rbtx4938_spi_gpio_dir_out,
	270	.label = "RBTX4938-SPICS",
	271	.base = 16,
	272	.ngpio = 3,
	273	};
f74cf6ff	274
f74cf6ff AN	275	static int __init rbtx4938_spi_init(void)
	276	{
	277	struct spi_board_info srtc_info = {
9f90a03a	278	.modalias = "rtc-rs5c348",
f74cf6ff AN	279	.max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
	280	.bus_num = 0,
	281	.chip_select = 16 + SRTC_CS,
	282	/* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
	283	.mode = SPI_MODE_1 \| SPI_CS_HIGH,
	284	};
	285	spi_register_board_info(&srtc_info, 1);
d75a40e9 AN	286	spi_eeprom_register(SPI_BUSNO, SEEPROM1_CS, 128);
	287	spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM2_CS, 128);
	288	spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM3_CS, 128);
4cad154b AN	289	gpio_request(16 + SRTC_CS, "rtc-rs5c348");
	290	gpio_direction_output(16 + SRTC_CS, 0);
	291	gpio_request(SEEPROM1_CS, "seeprom1");
	292	gpio_direction_output(SEEPROM1_CS, 1);
	293	gpio_request(16 + SEEPROM2_CS, "seeprom2");
	294	gpio_direction_output(16 + SEEPROM2_CS, 1);
	295	gpio_request(16 + SEEPROM3_CS, "seeprom3");
	296	gpio_direction_output(16 + SEEPROM3_CS, 1);
d75a40e9	297	tx4938_spi_init(SPI_BUSNO);
f74cf6ff AN	298	return 0;
f74cf6ff AN	299	}
4cad154b	300
51f607c7 AN	301	static void __init rbtx4938_mtd_init(void)
	302	{
	303	struct physmap_flash_data pdata = {
	304	.width = 4,
	305	};
	306
	307	switch (readb(rbtx4938_bdipsw_addr) & 7) {
	308	case 0:
	309	/* Boot */
	310	txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
	311	/* System */
	312	txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
	313	break;
	314	case 1:
	315	/* System */
	316	txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
	317	/* Boot */
	318	txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
	319	break;
	320	case 2:
	321	/* Ext */
	322	txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
	323	/* System */
	324	txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
	325	/* Boot */
	326	txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
	327	break;
	328	case 3:
	329	/* Boot */
	330	txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
	331	/* System */
	332	txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
	333	break;
	334	}
	335	}
	336
edcaf1a6	337	static void __init rbtx4938_arch_init(void)
4cad154b	338	{
5ac676ad	339	txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
ff53d12c	340	gpiochip_add_data(&rbtx4938_spi_gpio_chip, NULL);
89d63fe1	341	rbtx4938_pci_setup();
edcaf1a6	342	rbtx4938_spi_init();
4cad154b	343	}
f74cf6ff	344
edcaf1a6	345	static void __init rbtx4938_device_init(void)
f74cf6ff	346	{
edcaf1a6 AN	347	rbtx4938_ethaddr_init();
edcaf1a6 AN	348	rbtx4938_ne_init();
68314725	349	tx4938_wdt_init();
51f607c7	350	rbtx4938_mtd_init();
a591f5d3 AN	351	/* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
a591f5d3 AN	352	tx4938_ndfmc_init(10, 35);
5d1d2f8c	353	tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1);
f48c8c95	354	tx4938_dmac_init(0, 2);
742cd586 AN	355	tx4938_aclc_init();
742cd586 AN	356	platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
c3b28ae2	357	tx4938_sramc_init();
ae027ead	358	txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
f74cf6ff	359	}
f74cf6ff	360
edcaf1a6	361	struct txx9_board_vec rbtx4938_vec __initdata = {
edcaf1a6 AN	362	.system = "Toshiba RBTX4938",
	363	.prom_init = rbtx4938_prom_init,
	364	.mem_setup = rbtx4938_mem_setup,
	365	.irq_setup = rbtx4938_irq_setup,
	366	.time_init = rbtx4938_time_init,
	367	.device_init = rbtx4938_device_init,
	368	.arch_init = rbtx4938_arch_init,
	369	#ifdef CONFIG_PCI
	370	.pci_map_irq = rbtx4938_pci_map_irq,
	371	#endif
	372	};