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b27311e1 AN |
1 | /* |
2 | * Toshiba RBTX4939 setup routines. | |
3 | * Based on linux/arch/mips/txx9/rbtx4938/setup.c, | |
4 | * and RBTX49xx patch from CELF patch archive. | |
5 | * | |
6 | * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation | |
7 | * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the | |
8 | * terms of the GNU General Public License version 2. This program is | |
9 | * licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/leds.h> | |
1ba5a176 AN |
17 | #include <linux/interrupt.h> |
18 | #include <linux/smc91x.h> | |
cbf77c1b AN |
19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/partitions.h> | |
21 | #include <linux/mtd/map.h> | |
b27311e1 AN |
22 | #include <asm/reboot.h> |
23 | #include <asm/txx9/generic.h> | |
24 | #include <asm/txx9/pci.h> | |
25 | #include <asm/txx9/rbtx4939.h> | |
26 | ||
27 | static void rbtx4939_machine_restart(char *command) | |
28 | { | |
29 | local_irq_disable(); | |
30 | writeb(1, rbtx4939_reseten_addr); | |
31 | writeb(1, rbtx4939_softreset_addr); | |
32 | while (1) | |
33 | ; | |
34 | } | |
35 | ||
36 | static void __init rbtx4939_time_init(void) | |
37 | { | |
38 | tx4939_time_init(0); | |
39 | } | |
40 | ||
1ba5a176 AN |
41 | #if defined(__BIG_ENDIAN) && \ |
42 | (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) | |
43 | #define HAVE_RBTX4939_IOSWAB | |
44 | #define IS_CE1_ADDR(addr) \ | |
45 | ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1)) | |
46 | static u16 rbtx4939_ioswabw(volatile u16 *a, u16 x) | |
47 | { | |
48 | return IS_CE1_ADDR(a) ? x : le16_to_cpu(x); | |
49 | } | |
50 | static u16 rbtx4939_mem_ioswabw(volatile u16 *a, u16 x) | |
51 | { | |
52 | return !IS_CE1_ADDR(a) ? x : le16_to_cpu(x); | |
53 | } | |
54 | #endif /* __BIG_ENDIAN && CONFIG_SMC91X */ | |
55 | ||
b27311e1 AN |
56 | static void __init rbtx4939_pci_setup(void) |
57 | { | |
58 | #ifdef CONFIG_PCI | |
59 | int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB); | |
60 | struct pci_controller *c = &txx9_primary_pcic; | |
61 | ||
62 | register_pci_controller(c); | |
63 | ||
64 | tx4939_report_pciclk(); | |
65 | tx4927_pcic_setup(tx4939_pcicptr, c, extarb); | |
66 | if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) && | |
67 | (__raw_readq(&tx4939_ccfgptr->pcfg) & | |
68 | (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) { | |
69 | tx4939_report_pci1clk(); | |
70 | ||
71 | /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */ | |
72 | c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000); | |
73 | register_pci_controller(c); | |
74 | tx4927_pcic_setup(tx4939_pcic1ptr, c, 0); | |
75 | } | |
76 | ||
77 | tx4939_setup_pcierr_irq(); | |
78 | #endif /* CONFIG_PCI */ | |
79 | } | |
80 | ||
81 | static unsigned long long default_ebccr[] __initdata = { | |
82 | 0x01c0000000007608ULL, /* 64M ROM */ | |
83 | 0x017f000000007049ULL, /* 1M IOC */ | |
84 | 0x0180000000408608ULL, /* ISA */ | |
85 | 0, | |
86 | }; | |
87 | ||
88 | static void __init rbtx4939_ebusc_setup(void) | |
89 | { | |
90 | int i; | |
91 | unsigned int sp; | |
92 | ||
93 | /* use user-configured speed */ | |
94 | sp = TX4939_EBUSC_CR(0) & 0x30; | |
95 | default_ebccr[0] |= sp; | |
96 | default_ebccr[1] |= sp; | |
97 | default_ebccr[2] |= sp; | |
98 | /* initialise by myself */ | |
99 | for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) { | |
100 | if (default_ebccr[i]) | |
101 | ____raw_writeq(default_ebccr[i], | |
102 | &tx4939_ebuscptr->cr[i]); | |
103 | else | |
104 | ____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i]) | |
105 | & ~8, | |
106 | &tx4939_ebuscptr->cr[i]); | |
107 | } | |
108 | } | |
109 | ||
110 | static void __init rbtx4939_update_ioc_pen(void) | |
111 | { | |
112 | __u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg); | |
113 | __u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg); | |
114 | __u8 pe1 = readb(rbtx4939_pe1_addr); | |
115 | __u8 pe2 = readb(rbtx4939_pe2_addr); | |
116 | __u8 pe3 = readb(rbtx4939_pe3_addr); | |
117 | if (pcfg & TX4939_PCFG_ATA0MODE) | |
118 | pe1 |= RBTX4939_PE1_ATA(0); | |
119 | else | |
120 | pe1 &= ~RBTX4939_PE1_ATA(0); | |
121 | if (pcfg & TX4939_PCFG_ATA1MODE) { | |
122 | pe1 |= RBTX4939_PE1_ATA(1); | |
123 | pe1 &= ~(RBTX4939_PE1_RMII(0) | RBTX4939_PE1_RMII(1)); | |
124 | } else { | |
125 | pe1 &= ~RBTX4939_PE1_ATA(1); | |
126 | if (pcfg & TX4939_PCFG_ET0MODE) | |
127 | pe1 |= RBTX4939_PE1_RMII(0); | |
128 | else | |
129 | pe1 &= ~RBTX4939_PE1_RMII(0); | |
130 | if (pcfg & TX4939_PCFG_ET1MODE) | |
131 | pe1 |= RBTX4939_PE1_RMII(1); | |
132 | else | |
133 | pe1 &= ~RBTX4939_PE1_RMII(1); | |
134 | } | |
135 | if (ccfg & TX4939_CCFG_PTSEL) | |
136 | pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P | | |
137 | RBTX4939_PE3_VP_S); | |
138 | else { | |
139 | __u64 vmode = pcfg & | |
140 | (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE); | |
141 | if (vmode == 0) | |
142 | pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P | | |
143 | RBTX4939_PE3_VP_S); | |
144 | else if (vmode == TX4939_PCFG_VPSMODE) { | |
145 | pe3 |= RBTX4939_PE3_VP_P; | |
146 | pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_S); | |
147 | } else if (vmode == TX4939_PCFG_VSSMODE) { | |
148 | pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_S; | |
149 | pe3 &= ~RBTX4939_PE3_VP_P; | |
150 | } else { | |
151 | pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_P; | |
152 | pe3 &= ~RBTX4939_PE3_VP_S; | |
153 | } | |
154 | } | |
155 | if (pcfg & TX4939_PCFG_SPIMODE) { | |
156 | if (pcfg & TX4939_PCFG_SIO2MODE_GPIO) | |
157 | pe2 &= ~(RBTX4939_PE2_SIO2 | RBTX4939_PE2_SIO0); | |
158 | else { | |
159 | if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) { | |
160 | pe2 |= RBTX4939_PE2_SIO2; | |
161 | pe2 &= ~RBTX4939_PE2_SIO0; | |
162 | } else { | |
163 | pe2 |= RBTX4939_PE2_SIO0; | |
164 | pe2 &= ~RBTX4939_PE2_SIO2; | |
165 | } | |
166 | } | |
167 | if (pcfg & TX4939_PCFG_SIO3MODE) | |
168 | pe2 |= RBTX4939_PE2_SIO3; | |
169 | else | |
170 | pe2 &= ~RBTX4939_PE2_SIO3; | |
171 | pe2 &= ~RBTX4939_PE2_SPI; | |
172 | } else { | |
173 | pe2 |= RBTX4939_PE2_SPI; | |
174 | pe2 &= ~(RBTX4939_PE2_SIO3 | RBTX4939_PE2_SIO2 | | |
175 | RBTX4939_PE2_SIO0); | |
176 | } | |
177 | if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO) | |
178 | pe2 |= RBTX4939_PE2_GPIO; | |
179 | else | |
180 | pe2 &= ~RBTX4939_PE2_GPIO; | |
181 | writeb(pe1, rbtx4939_pe1_addr); | |
182 | writeb(pe2, rbtx4939_pe2_addr); | |
183 | writeb(pe3, rbtx4939_pe3_addr); | |
184 | } | |
185 | ||
186 | #define RBTX4939_MAX_7SEGLEDS 8 | |
187 | ||
188 | #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) | |
189 | static u8 led_val[RBTX4939_MAX_7SEGLEDS]; | |
190 | struct rbtx4939_led_data { | |
191 | struct led_classdev cdev; | |
192 | char name[32]; | |
193 | unsigned int num; | |
194 | }; | |
195 | ||
196 | /* Use "dot" in 7seg LEDs */ | |
197 | static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev, | |
198 | enum led_brightness value) | |
199 | { | |
200 | struct rbtx4939_led_data *led_dat = | |
201 | container_of(led_cdev, struct rbtx4939_led_data, cdev); | |
202 | unsigned int num = led_dat->num; | |
203 | unsigned long flags; | |
204 | ||
205 | local_irq_save(flags); | |
206 | led_val[num] = (led_val[num] & 0x7f) | (value ? 0x80 : 0); | |
207 | writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4)); | |
208 | local_irq_restore(flags); | |
209 | } | |
210 | ||
211 | static int __init rbtx4939_led_probe(struct platform_device *pdev) | |
212 | { | |
213 | struct rbtx4939_led_data *leds_data; | |
214 | int i; | |
215 | static char *default_triggers[] __initdata = { | |
216 | "heartbeat", | |
217 | "ide-disk", | |
218 | "nand-disk", | |
219 | }; | |
220 | ||
221 | leds_data = kzalloc(sizeof(*leds_data) * RBTX4939_MAX_7SEGLEDS, | |
222 | GFP_KERNEL); | |
223 | if (!leds_data) | |
224 | return -ENOMEM; | |
225 | for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) { | |
226 | int rc; | |
227 | struct rbtx4939_led_data *led_dat = &leds_data[i]; | |
228 | ||
229 | led_dat->num = i; | |
230 | led_dat->cdev.brightness_set = rbtx4939_led_brightness_set; | |
231 | sprintf(led_dat->name, "rbtx4939:amber:%u", i); | |
232 | led_dat->cdev.name = led_dat->name; | |
233 | if (i < ARRAY_SIZE(default_triggers)) | |
234 | led_dat->cdev.default_trigger = default_triggers[i]; | |
235 | rc = led_classdev_register(&pdev->dev, &led_dat->cdev); | |
236 | if (rc < 0) | |
237 | return rc; | |
238 | led_dat->cdev.brightness_set(&led_dat->cdev, 0); | |
239 | } | |
240 | return 0; | |
241 | ||
242 | } | |
243 | ||
244 | static struct platform_driver rbtx4939_led_driver = { | |
245 | .driver = { | |
246 | .name = "rbtx4939-led", | |
247 | .owner = THIS_MODULE, | |
248 | }, | |
249 | }; | |
250 | ||
251 | static void __init rbtx4939_led_setup(void) | |
252 | { | |
253 | platform_device_register_simple("rbtx4939-led", -1, NULL, 0); | |
254 | platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe); | |
255 | } | |
256 | #else | |
257 | static inline void rbtx4939_led_setup(void) | |
258 | { | |
259 | } | |
260 | #endif | |
261 | ||
bc89b2bd AN |
262 | static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val) |
263 | { | |
264 | #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) | |
265 | unsigned long flags; | |
266 | local_irq_save(flags); | |
267 | /* bit7: reserved for LED class */ | |
268 | led_val[pos] = (led_val[pos] & 0x80) | (val & 0x7f); | |
269 | val = led_val[pos]; | |
270 | local_irq_restore(flags); | |
271 | #endif | |
272 | writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4)); | |
273 | } | |
274 | ||
275 | static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val) | |
276 | { | |
277 | /* convert from map_to_seg7() notation */ | |
278 | val = (val & 0x88) | | |
279 | ((val & 0x40) >> 6) | | |
280 | ((val & 0x20) >> 4) | | |
281 | ((val & 0x10) >> 2) | | |
282 | ((val & 0x04) << 2) | | |
283 | ((val & 0x02) << 4) | | |
284 | ((val & 0x01) << 6); | |
285 | __rbtx4939_7segled_putc(pos, val); | |
286 | } | |
287 | ||
cbf77c1b AN |
288 | #if defined(CONFIG_MTD_RBTX4939) || defined(CONFIG_MTD_RBTX4939_MODULE) |
289 | /* special mapping for boot rom */ | |
290 | static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs) | |
291 | { | |
292 | u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; | |
293 | unsigned char shift; | |
294 | ||
295 | if (bdipsw & 8) { | |
296 | /* BOOT Mode: USER ROM1 / USER ROM2 */ | |
297 | shift = bdipsw & 3; | |
298 | /* rotate A[23:22] */ | |
299 | return (ofs & ~0xc00000) | ((((ofs >> 22) + shift) & 3) << 22); | |
300 | } | |
301 | #ifdef __BIG_ENDIAN | |
302 | if (bdipsw == 0) | |
303 | /* BOOT Mode: Monitor ROM */ | |
304 | ofs ^= 0x400000; /* swap A[22] */ | |
305 | #endif | |
306 | return ofs; | |
307 | } | |
308 | ||
309 | static map_word rbtx4939_flash_read16(struct map_info *map, unsigned long ofs) | |
310 | { | |
311 | map_word r; | |
312 | ||
313 | ofs = rbtx4939_flash_fixup_ofs(ofs); | |
314 | r.x[0] = __raw_readw(map->virt + ofs); | |
315 | return r; | |
316 | } | |
317 | ||
318 | static void rbtx4939_flash_write16(struct map_info *map, const map_word datum, | |
319 | unsigned long ofs) | |
320 | { | |
321 | ofs = rbtx4939_flash_fixup_ofs(ofs); | |
322 | __raw_writew(datum.x[0], map->virt + ofs); | |
323 | mb(); /* see inline_map_write() in mtd/map.h */ | |
324 | } | |
325 | ||
326 | static void rbtx4939_flash_copy_from(struct map_info *map, void *to, | |
327 | unsigned long from, ssize_t len) | |
328 | { | |
329 | u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; | |
330 | unsigned char shift; | |
331 | ssize_t curlen; | |
332 | ||
333 | from += (unsigned long)map->virt; | |
334 | if (bdipsw & 8) { | |
335 | /* BOOT Mode: USER ROM1 / USER ROM2 */ | |
336 | shift = bdipsw & 3; | |
337 | while (len) { | |
338 | curlen = min_t(unsigned long, len, | |
339 | 0x400000 - (from & (0x400000 - 1))); | |
340 | memcpy(to, | |
341 | (void *)((from & ~0xc00000) | | |
342 | ((((from >> 22) + shift) & 3) << 22)), | |
343 | curlen); | |
344 | len -= curlen; | |
345 | from += curlen; | |
346 | to += curlen; | |
347 | } | |
348 | return; | |
349 | } | |
350 | #ifdef __BIG_ENDIAN | |
351 | if (bdipsw == 0) { | |
352 | /* BOOT Mode: Monitor ROM */ | |
353 | while (len) { | |
354 | curlen = min_t(unsigned long, len, | |
355 | 0x400000 - (from & (0x400000 - 1))); | |
356 | memcpy(to, (void *)(from ^ 0x400000), curlen); | |
357 | len -= curlen; | |
358 | from += curlen; | |
359 | to += curlen; | |
360 | } | |
361 | return; | |
362 | } | |
363 | #endif | |
364 | memcpy(to, (void *)from, len); | |
365 | } | |
366 | ||
367 | static void rbtx4939_flash_map_init(struct map_info *map) | |
368 | { | |
369 | map->read = rbtx4939_flash_read16; | |
370 | map->write = rbtx4939_flash_write16; | |
371 | map->copy_from = rbtx4939_flash_copy_from; | |
372 | } | |
373 | ||
374 | static void __init rbtx4939_mtd_init(void) | |
375 | { | |
376 | static struct { | |
377 | struct platform_device dev; | |
378 | struct resource res; | |
379 | struct rbtx4939_flash_data data; | |
380 | } pdevs[4]; | |
381 | int i; | |
382 | static char names[4][8]; | |
383 | static struct mtd_partition parts[4]; | |
384 | struct rbtx4939_flash_data *boot_pdata = &pdevs[0].data; | |
385 | u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; | |
386 | ||
387 | if (bdipsw & 8) { | |
388 | /* BOOT Mode: USER ROM1 / USER ROM2 */ | |
389 | boot_pdata->nr_parts = 4; | |
390 | for (i = 0; i < boot_pdata->nr_parts; i++) { | |
391 | sprintf(names[i], "img%d", 4 - i); | |
392 | parts[i].name = names[i]; | |
393 | parts[i].size = 0x400000; | |
394 | parts[i].offset = MTDPART_OFS_NXTBLK; | |
395 | } | |
396 | } else if (bdipsw == 0) { | |
397 | /* BOOT Mode: Monitor ROM */ | |
398 | boot_pdata->nr_parts = 2; | |
399 | strcpy(names[0], "big"); | |
400 | strcpy(names[1], "little"); | |
401 | for (i = 0; i < boot_pdata->nr_parts; i++) { | |
402 | parts[i].name = names[i]; | |
403 | parts[i].size = 0x400000; | |
404 | parts[i].offset = MTDPART_OFS_NXTBLK; | |
405 | } | |
406 | } else { | |
407 | /* BOOT Mode: ROM Emulator */ | |
408 | boot_pdata->nr_parts = 2; | |
409 | parts[0].name = "boot"; | |
410 | parts[0].offset = 0xc00000; | |
411 | parts[0].size = 0x400000; | |
412 | parts[1].name = "user"; | |
413 | parts[1].offset = 0; | |
414 | parts[1].size = 0xc00000; | |
415 | } | |
416 | boot_pdata->parts = parts; | |
417 | boot_pdata->map_init = rbtx4939_flash_map_init; | |
418 | ||
419 | for (i = 0; i < ARRAY_SIZE(pdevs); i++) { | |
420 | struct resource *r = &pdevs[i].res; | |
421 | struct platform_device *dev = &pdevs[i].dev; | |
422 | ||
423 | r->start = 0x1f000000 - i * 0x1000000; | |
424 | r->end = r->start + 0x1000000 - 1; | |
425 | r->flags = IORESOURCE_MEM; | |
426 | pdevs[i].data.width = 2; | |
427 | dev->num_resources = 1; | |
428 | dev->resource = r; | |
429 | dev->id = i; | |
430 | dev->name = "rbtx4939-flash"; | |
431 | dev->dev.platform_data = &pdevs[i].data; | |
432 | platform_device_register(dev); | |
433 | } | |
434 | } | |
435 | #else | |
436 | static void __init rbtx4939_mtd_init(void) | |
437 | { | |
438 | } | |
439 | #endif | |
440 | ||
b27311e1 AN |
441 | static void __init rbtx4939_arch_init(void) |
442 | { | |
443 | rbtx4939_pci_setup(); | |
444 | } | |
445 | ||
446 | static void __init rbtx4939_device_init(void) | |
447 | { | |
1ba5a176 AN |
448 | unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE; |
449 | struct resource smc_res[] = { | |
450 | { | |
451 | .start = smc_addr, | |
452 | .end = smc_addr + 0x10 - 1, | |
453 | .flags = IORESOURCE_MEM, | |
454 | }, { | |
455 | .start = RBTX4939_IRQ_ETHER, | |
456 | /* override default irq flag defined in smc91x.h */ | |
457 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, | |
458 | }, | |
459 | }; | |
460 | struct smc91x_platdata smc_pdata = { | |
461 | .flags = SMC91X_USE_16BIT, | |
462 | }; | |
463 | struct platform_device *pdev; | |
b27311e1 AN |
464 | #if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE) |
465 | int i, j; | |
466 | unsigned char ethaddr[2][6]; | |
9cc45815 AN |
467 | u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; |
468 | ||
b27311e1 AN |
469 | for (i = 0; i < 2; i++) { |
470 | unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10); | |
9cc45815 AN |
471 | if (bdipsw == 0) |
472 | memcpy(ethaddr[i], (void *)area, 6); | |
473 | else { | |
b27311e1 | 474 | u16 buf[3]; |
9cc45815 AN |
475 | if (bdipsw & 8) |
476 | area -= 0x03000000; | |
477 | else | |
478 | area -= 0x01000000; | |
b27311e1 AN |
479 | for (j = 0; j < 3; j++) |
480 | buf[j] = le16_to_cpup((u16 *)(area + j * 2)); | |
481 | memcpy(ethaddr[i], buf, 6); | |
9cc45815 | 482 | } |
b27311e1 AN |
483 | } |
484 | tx4939_ethaddr_init(ethaddr[0], ethaddr[1]); | |
485 | #endif | |
1ba5a176 AN |
486 | pdev = platform_device_alloc("smc91x", -1); |
487 | if (!pdev || | |
488 | platform_device_add_resources(pdev, smc_res, ARRAY_SIZE(smc_res)) || | |
489 | platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) || | |
490 | platform_device_add(pdev)) | |
491 | platform_device_put(pdev); | |
cbf77c1b | 492 | rbtx4939_mtd_init(); |
a591f5d3 AN |
493 | /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */ |
494 | tx4939_ndfmc_init(10, 35, | |
495 | (1 << 1) | (1 << 2), | |
496 | (1 << 2)); /* ch1:8bit, ch2:16bit */ | |
b27311e1 AN |
497 | rbtx4939_led_setup(); |
498 | tx4939_wdt_init(); | |
4bacc687 | 499 | tx4939_ata_init(); |
65655b5a | 500 | tx4939_rtc_init(); |
f48c8c95 | 501 | tx4939_dmac_init(0, 2); |
742cd586 AN |
502 | tx4939_aclc_init(); |
503 | platform_device_register_simple("txx9aclc-generic", -1, NULL, 0); | |
c3b28ae2 | 504 | tx4939_sramc_init(); |
923e3819 | 505 | tx4939_rng_init(); |
b27311e1 AN |
506 | } |
507 | ||
508 | static void __init rbtx4939_setup(void) | |
509 | { | |
bc89b2bd AN |
510 | int i; |
511 | ||
b27311e1 AN |
512 | rbtx4939_ebusc_setup(); |
513 | /* always enable ATA0 */ | |
514 | txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE); | |
b27311e1 AN |
515 | if (txx9_master_clock == 0) |
516 | txx9_master_clock = 20000000; | |
517 | tx4939_setup(); | |
3e6e9218 | 518 | rbtx4939_update_ioc_pen(); |
1ba5a176 AN |
519 | #ifdef HAVE_RBTX4939_IOSWAB |
520 | ioswabw = rbtx4939_ioswabw; | |
521 | __mem_ioswabw = rbtx4939_mem_ioswabw; | |
522 | #endif | |
b27311e1 AN |
523 | |
524 | _machine_restart = rbtx4939_machine_restart; | |
525 | ||
bc89b2bd AN |
526 | txx9_7segled_init(RBTX4939_MAX_7SEGLEDS, rbtx4939_7segled_putc); |
527 | for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) | |
528 | txx9_7segled_putc(i, '-'); | |
b27311e1 AN |
529 | pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", |
530 | readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr), | |
531 | readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr)); | |
532 | ||
533 | #ifdef CONFIG_PCI | |
534 | txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0); | |
535 | txx9_board_pcibios_setup = tx4927_pcibios_setup; | |
536 | #else | |
537 | set_io_port_base(RBTX4939_ETHER_BASE); | |
538 | #endif | |
539 | ||
540 | tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0); | |
541 | } | |
542 | ||
543 | struct txx9_board_vec rbtx4939_vec __initdata = { | |
dfe99b9c | 544 | .system = "Toshiba RBTX4939", |
b27311e1 AN |
545 | .prom_init = rbtx4939_prom_init, |
546 | .mem_setup = rbtx4939_setup, | |
547 | .irq_setup = rbtx4939_irq_setup, | |
548 | .time_init = rbtx4939_time_init, | |
549 | .device_init = rbtx4939_device_init, | |
550 | .arch_init = rbtx4939_arch_init, | |
551 | #ifdef CONFIG_PCI | |
552 | .pci_map_irq = tx4939_pci_map_irq, | |
553 | #endif | |
554 | }; |