[mirror_ubuntu-hirsute-kernel.git] / arch / mips / vr41xx / common / cmu.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  cmu.c, Clock Mask Unit routines for the NEC VR4100 series.
 *
 *  Copyright (C) 2001-2002  MontaVista Software Inc.
 *    Author: Yoichi Yuasa <source@mvista.com>
 *  Copyright (C) 2003-2005  Yoichi Yuasa <yuasa@linux-mips.org>
 */
/*
 * Changes:
 *  MontaVista Software Inc. <source@mvista.com>
 *  - New creation, NEC VR4122 and VR4131 are supported.
 *  - Added support for NEC VR4111 and VR4121.
 *
 *  Yoichi Yuasa <yuasa@linux-mips.org>
 *  - Added support for NEC VR4133.
 */
#include <linux/export.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#include <asm/cpu.h>
#include <asm/io.h>
#include <asm/vr41xx/vr41xx.h>

#define CMU_TYPE1_BASE	0x0b000060UL
#define CMU_TYPE1_SIZE	0x4

#define CMU_TYPE2_BASE	0x0f000060UL
#define CMU_TYPE2_SIZE	0x4

#define CMU_TYPE3_BASE	0x0f000060UL
#define CMU_TYPE3_SIZE	0x8

#define CMUCLKMSK	0x0
 #define MSKPIU		0x0001
 #define MSKSIU		0x0002
 #define MSKAIU		0x0004
 #define MSKKIU		0x0008
 #define MSKFIR		0x0010
 #define MSKDSIU	0x0820
 #define MSKCSI		0x0040
 #define MSKPCIU	0x0080
 #define MSKSSIU	0x0100
 #define MSKSHSP	0x0200
 #define MSKFFIR	0x0400
 #define MSKSCSI	0x1000
 #define MSKPPCIU	0x2000
#define CMUCLKMSK2	0x4
 #define MSKCEU		0x0001
 #define MSKMAC0	0x0002
 #define MSKMAC1	0x0004

static void __iomem *cmu_base;
static uint16_t cmuclkmsk, cmuclkmsk2;
static DEFINE_SPINLOCK(cmu_lock);

#define cmu_read(offset)		readw(cmu_base + (offset))
#define cmu_write(offset, value)	writew((value), cmu_base + (offset))

void vr41xx_supply_clock(vr41xx_clock_t clock)
{
	spin_lock_irq(&cmu_lock);

	switch (clock) {
	case PIU_CLOCK:
		cmuclkmsk |= MSKPIU;
		break;
	case SIU_CLOCK:
		cmuclkmsk |= MSKSIU | MSKSSIU;
		break;
	case AIU_CLOCK:
		cmuclkmsk |= MSKAIU;
		break;
	case KIU_CLOCK:
		cmuclkmsk |= MSKKIU;
		break;
	case FIR_CLOCK:
		cmuclkmsk |= MSKFIR | MSKFFIR;
		break;
	case DSIU_CLOCK:
		if (current_cpu_type() == CPU_VR4111 ||
		    current_cpu_type() == CPU_VR4121)
			cmuclkmsk |= MSKDSIU;
		else
			cmuclkmsk |= MSKSIU | MSKDSIU;
		break;
	case CSI_CLOCK:
		cmuclkmsk |= MSKCSI | MSKSCSI;
		break;
	case PCIU_CLOCK:
		cmuclkmsk |= MSKPCIU;
		break;
	case HSP_CLOCK:
		cmuclkmsk |= MSKSHSP;
		break;
	case PCI_CLOCK:
		cmuclkmsk |= MSKPPCIU;
		break;
	case CEU_CLOCK:
		cmuclkmsk2 |= MSKCEU;
		break;
	case ETHER0_CLOCK:
		cmuclkmsk2 |= MSKMAC0;
		break;
	case ETHER1_CLOCK:
		cmuclkmsk2 |= MSKMAC1;
		break;
	default:
		break;
	}

	if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
	    clock == ETHER1_CLOCK)
		cmu_write(CMUCLKMSK2, cmuclkmsk2);
	else
		cmu_write(CMUCLKMSK, cmuclkmsk);

	spin_unlock_irq(&cmu_lock);
}

EXPORT_SYMBOL_GPL(vr41xx_supply_clock);

void vr41xx_mask_clock(vr41xx_clock_t clock)
{
	spin_lock_irq(&cmu_lock);

	switch (clock) {
	case PIU_CLOCK:
		cmuclkmsk &= ~MSKPIU;
		break;
	case SIU_CLOCK:
		if (current_cpu_type() == CPU_VR4111 ||
		    current_cpu_type() == CPU_VR4121) {
			cmuclkmsk &= ~(MSKSIU | MSKSSIU);
		} else {
			if (cmuclkmsk & MSKDSIU)
				cmuclkmsk &= ~MSKSSIU;
			else
				cmuclkmsk &= ~(MSKSIU | MSKSSIU);
		}
		break;
	case AIU_CLOCK:
		cmuclkmsk &= ~MSKAIU;
		break;
	case KIU_CLOCK:
		cmuclkmsk &= ~MSKKIU;
		break;
	case FIR_CLOCK:
		cmuclkmsk &= ~(MSKFIR | MSKFFIR);
		break;
	case DSIU_CLOCK:
		if (current_cpu_type() == CPU_VR4111 ||
		    current_cpu_type() == CPU_VR4121) {
			cmuclkmsk &= ~MSKDSIU;
		} else {
			if (cmuclkmsk & MSKSSIU)
				cmuclkmsk &= ~MSKDSIU;
			else
				cmuclkmsk &= ~(MSKSIU | MSKDSIU);
		}
		break;
	case CSI_CLOCK:
		cmuclkmsk &= ~(MSKCSI | MSKSCSI);
		break;
	case PCIU_CLOCK:
		cmuclkmsk &= ~MSKPCIU;
		break;
	case HSP_CLOCK:
		cmuclkmsk &= ~MSKSHSP;
		break;
	case PCI_CLOCK:
		cmuclkmsk &= ~MSKPPCIU;
		break;
	case CEU_CLOCK:
		cmuclkmsk2 &= ~MSKCEU;
		break;
	case ETHER0_CLOCK:
		cmuclkmsk2 &= ~MSKMAC0;
		break;
	case ETHER1_CLOCK:
		cmuclkmsk2 &= ~MSKMAC1;
		break;
	default:
		break;
	}

	if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
	    clock == ETHER1_CLOCK)
		cmu_write(CMUCLKMSK2, cmuclkmsk2);
	else
		cmu_write(CMUCLKMSK, cmuclkmsk);

	spin_unlock_irq(&cmu_lock);
}

EXPORT_SYMBOL_GPL(vr41xx_mask_clock);

static int __init vr41xx_cmu_init(void)
{
	unsigned long start, size;

	switch (current_cpu_type()) {
	case CPU_VR4111:
	case CPU_VR4121:
		start = CMU_TYPE1_BASE;
		size = CMU_TYPE1_SIZE;
		break;
	case CPU_VR4122:
	case CPU_VR4131:
		start = CMU_TYPE2_BASE;
		size = CMU_TYPE2_SIZE;
		break;
	case CPU_VR4133:
		start = CMU_TYPE3_BASE;
		size = CMU_TYPE3_SIZE;
		break;
	default:
		panic("Unexpected CPU of NEC VR4100 series");
		break;
	}

	if (request_mem_region(start, size, "CMU") == NULL)
		return -EBUSY;

	cmu_base = ioremap(start, size);
	if (cmu_base == NULL) {
		release_mem_region(start, size);
		return -EBUSY;
	}

	cmuclkmsk = cmu_read(CMUCLKMSK);
	if (current_cpu_type() == CPU_VR4133)
		cmuclkmsk2 = cmu_read(CMUCLKMSK2);

	spin_lock_init(&cmu_lock);

	return 0;
}

core_initcall(vr41xx_cmu_init);
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* cmu.c, Clock Mask Unit routines for the NEC VR4100 series.
	4	*
	5	* Copyright (C) 2001-2002 MontaVista Software Inc.
ada8e951	6	* Author: Yoichi Yuasa <source@mvista.com>
a320a115	7	* Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org>
1da177e4 LT	8	*/
	9	/*
	10	* Changes:
ada8e951	11	* MontaVista Software Inc. <source@mvista.com>
1da177e4 LT	12	* - New creation, NEC VR4122 and VR4131 are supported.
	13	* - Added support for NEC VR4111 and VR4121.
	14	*
ada8e951	15	* Yoichi Yuasa <yuasa@linux-mips.org>
1da177e4 LT	16	* - Added support for NEC VR4133.
1da177e4 LT	17	*/
26dd3e4f	18	#include <linux/export.h>
1da177e4 LT	19	#include <linux/init.h>
1da177e4 LT	20	#include <linux/ioport.h>
1da177e4 LT	21	#include <linux/smp.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/types.h>
	24
	25	#include <asm/cpu.h>
	26	#include <asm/io.h>
	27	#include <asm/vr41xx/vr41xx.h>
	28
	29	#define CMU_TYPE1_BASE 0x0b000060UL
	30	#define CMU_TYPE1_SIZE 0x4
	31
	32	#define CMU_TYPE2_BASE 0x0f000060UL
	33	#define CMU_TYPE2_SIZE 0x4
	34
	35	#define CMU_TYPE3_BASE 0x0f000060UL
	36	#define CMU_TYPE3_SIZE 0x8
	37
	38	#define CMUCLKMSK 0x0
	39	#define MSKPIU 0x0001
	40	#define MSKSIU 0x0002
	41	#define MSKAIU 0x0004
	42	#define MSKKIU 0x0008
	43	#define MSKFIR 0x0010
	44	#define MSKDSIU 0x0820
	45	#define MSKCSI 0x0040
	46	#define MSKPCIU 0x0080
	47	#define MSKSSIU 0x0100
	48	#define MSKSHSP 0x0200
	49	#define MSKFFIR 0x0400
	50	#define MSKSCSI 0x1000
	51	#define MSKPPCIU 0x2000
	52	#define CMUCLKMSK2 0x4
	53	#define MSKCEU 0x0001
	54	#define MSKMAC0 0x0002
	55	#define MSKMAC1 0x0004
	56
	57	static void __iomem *cmu_base;
	58	static uint16_t cmuclkmsk, cmuclkmsk2;
2f69ddcc	59	static DEFINE_SPINLOCK(cmu_lock);
1da177e4 LT	60
	61	#define cmu_read(offset) readw(cmu_base + (offset))
	62	#define cmu_write(offset, value) writew((value), cmu_base + (offset))
	63
	64	void vr41xx_supply_clock(vr41xx_clock_t clock)
	65	{
	66	spin_lock_irq(&cmu_lock);
	67
	68	switch (clock) {
	69	case PIU_CLOCK:
	70	cmuclkmsk \|= MSKPIU;
	71	break;
	72	case SIU_CLOCK:
	73	cmuclkmsk \|= MSKSIU \| MSKSSIU;
	74	break;
	75	case AIU_CLOCK:
	76	cmuclkmsk \|= MSKAIU;
	77	break;
	78	case KIU_CLOCK:
	79	cmuclkmsk \|= MSKKIU;
	80	break;
	81	case FIR_CLOCK:
	82	cmuclkmsk \|= MSKFIR \| MSKFFIR;
	83	break;
	84	case DSIU_CLOCK:
10cc3529 RB	85	if (current_cpu_type() == CPU_VR4111 \|\|
10cc3529 RB	86	current_cpu_type() == CPU_VR4121)
1da177e4 LT	87	cmuclkmsk \|= MSKDSIU;
	88	else
	89	cmuclkmsk \|= MSKSIU \| MSKDSIU;
	90	break;
	91	case CSI_CLOCK:
	92	cmuclkmsk \|= MSKCSI \| MSKSCSI;
	93	break;
	94	case PCIU_CLOCK:
	95	cmuclkmsk \|= MSKPCIU;
	96	break;
	97	case HSP_CLOCK:
	98	cmuclkmsk \|= MSKSHSP;
	99	break;
	100	case PCI_CLOCK:
	101	cmuclkmsk \|= MSKPPCIU;
	102	break;
	103	case CEU_CLOCK:
	104	cmuclkmsk2 \|= MSKCEU;
	105	break;
	106	case ETHER0_CLOCK:
	107	cmuclkmsk2 \|= MSKMAC0;
	108	break;
	109	case ETHER1_CLOCK:
	110	cmuclkmsk2 \|= MSKMAC1;
	111	break;
	112	default:
	113	break;
	114	}
	115
	116	if (clock == CEU_CLOCK \|\| clock == ETHER0_CLOCK \|\|
	117	clock == ETHER1_CLOCK)
	118	cmu_write(CMUCLKMSK2, cmuclkmsk2);
	119	else
	120	cmu_write(CMUCLKMSK, cmuclkmsk);
	121
	122	spin_unlock_irq(&cmu_lock);
	123	}
	124
	125	EXPORT_SYMBOL_GPL(vr41xx_supply_clock);
	126
	127	void vr41xx_mask_clock(vr41xx_clock_t clock)
	128	{
	129	spin_lock_irq(&cmu_lock);
	130
	131	switch (clock) {
	132	case PIU_CLOCK:
	133	cmuclkmsk &= ~MSKPIU;
	134	break;
	135	case SIU_CLOCK:
10cc3529 RB	136	if (current_cpu_type() == CPU_VR4111 \|\|
10cc3529 RB	137	current_cpu_type() == CPU_VR4121) {
1da177e4 LT	138	cmuclkmsk &= ~(MSKSIU \| MSKSSIU);
	139	} else {
	140	if (cmuclkmsk & MSKDSIU)
	141	cmuclkmsk &= ~MSKSSIU;
	142	else
	143	cmuclkmsk &= ~(MSKSIU \| MSKSSIU);
	144	}
	145	break;
	146	case AIU_CLOCK:
	147	cmuclkmsk &= ~MSKAIU;
	148	break;
	149	case KIU_CLOCK:
	150	cmuclkmsk &= ~MSKKIU;
	151	break;
	152	case FIR_CLOCK:
	153	cmuclkmsk &= ~(MSKFIR \| MSKFFIR);
	154	break;
	155	case DSIU_CLOCK:
10cc3529 RB	156	if (current_cpu_type() == CPU_VR4111 \|\|
10cc3529 RB	157	current_cpu_type() == CPU_VR4121) {
1da177e4 LT	158	cmuclkmsk &= ~MSKDSIU;
	159	} else {
	160	if (cmuclkmsk & MSKSSIU)
	161	cmuclkmsk &= ~MSKDSIU;
	162	else
	163	cmuclkmsk &= ~(MSKSIU \| MSKDSIU);
	164	}
	165	break;
	166	case CSI_CLOCK:
	167	cmuclkmsk &= ~(MSKCSI \| MSKSCSI);
	168	break;
	169	case PCIU_CLOCK:
	170	cmuclkmsk &= ~MSKPCIU;
	171	break;
	172	case HSP_CLOCK:
	173	cmuclkmsk &= ~MSKSHSP;
	174	break;
	175	case PCI_CLOCK:
	176	cmuclkmsk &= ~MSKPPCIU;
	177	break;
	178	case CEU_CLOCK:
	179	cmuclkmsk2 &= ~MSKCEU;
	180	break;
	181	case ETHER0_CLOCK:
	182	cmuclkmsk2 &= ~MSKMAC0;
	183	break;
	184	case ETHER1_CLOCK:
	185	cmuclkmsk2 &= ~MSKMAC1;
	186	break;
	187	default:
	188	break;
	189	}
	190
	191	if (clock == CEU_CLOCK \|\| clock == ETHER0_CLOCK \|\|
	192	clock == ETHER1_CLOCK)
	193	cmu_write(CMUCLKMSK2, cmuclkmsk2);
	194	else
	195	cmu_write(CMUCLKMSK, cmuclkmsk);
	196
	197	spin_unlock_irq(&cmu_lock);
	198	}
	199
	200	EXPORT_SYMBOL_GPL(vr41xx_mask_clock);
	201
	202	static int __init vr41xx_cmu_init(void)
	203	{
	204	unsigned long start, size;
	205
10cc3529	206	switch (current_cpu_type()) {
70342287 RB	207	case CPU_VR4111:
70342287 RB	208	case CPU_VR4121:
1da177e4 LT	209	start = CMU_TYPE1_BASE;
1da177e4 LT	210	size = CMU_TYPE1_SIZE;
70342287 RB	211	break;
	212	case CPU_VR4122:
	213	case CPU_VR4131:
1da177e4 LT	214	start = CMU_TYPE2_BASE;
	215	size = CMU_TYPE2_SIZE;
	216	break;
70342287	217	case CPU_VR4133:
1da177e4 LT	218	start = CMU_TYPE3_BASE;
1da177e4 LT	219	size = CMU_TYPE3_SIZE;
70342287	220	break;
1da177e4 LT	221	default:
	222	panic("Unexpected CPU of NEC VR4100 series");
	223	break;
70342287	224	}
1da177e4 LT	225
	226	if (request_mem_region(start, size, "CMU") == NULL)
	227	return -EBUSY;
	228
	229	cmu_base = ioremap(start, size);
	230	if (cmu_base == NULL) {
	231	release_mem_region(start, size);
	232	return -EBUSY;
	233	}
	234
	235	cmuclkmsk = cmu_read(CMUCLKMSK);
10cc3529	236	if (current_cpu_type() == CPU_VR4133)
1da177e4 LT	237	cmuclkmsk2 = cmu_read(CMUCLKMSK2);
	238
	239	spin_lock_init(&cmu_lock);
	240
	241	return 0;
	242	}
	243
	244	core_initcall(vr41xx_cmu_init);