[mirror_ubuntu-jammy-kernel.git] / arch / mips / vr41xx / common / irq.c

/*
 *  Interrupt handing routines for NEC VR4100 series.
 *
 *  Copyright (C) 2005-2007  Yoichi Yuasa <yuasa@linux-mips.org>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>

#include <asm/irq_cpu.h>
#include <asm/system.h>
#include <asm/vr41xx/irq.h>

typedef struct irq_cascade {
	int (*get_irq)(unsigned int);
} irq_cascade_t;

static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;

static struct irqaction cascade_irqaction = {
	.handler	= no_action,
	.name		= "cascade",
};

int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int))
{
	int retval = 0;

	if (irq >= NR_IRQS)
		return -EINVAL;

	if (irq_cascade[irq].get_irq != NULL)
		free_irq(irq, NULL);

	irq_cascade[irq].get_irq = get_irq;

	if (get_irq != NULL) {
		retval = setup_irq(irq, &cascade_irqaction);
		if (retval < 0)
			irq_cascade[irq].get_irq = NULL;
	}

	return retval;
}

EXPORT_SYMBOL_GPL(cascade_irq);

static void irq_dispatch(unsigned int irq)
{
	irq_cascade_t *cascade;

	if (irq >= NR_IRQS) {
		atomic_inc(&irq_err_count);
		return;
	}

	cascade = irq_cascade + irq;
	if (cascade->get_irq != NULL) {
		struct irq_desc *desc = irq_to_desc(irq);
		struct irq_data *idata = irq_desc_get_irq_data(desc);
		struct irq_chip *chip = irq_desc_get_chip(desc);
		int ret;

		if (chip->irq_mask_ack)
			chip->irq_mask_ack(idata);
		else {
			chip->irq_mask(idata);
			chip->irq_ack(idata);
		}
		ret = cascade->get_irq(irq);
		irq = ret;
		if (ret < 0)
			atomic_inc(&irq_err_count);
		else
			irq_dispatch(irq);
		if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
			chip->irq_unmask(idata);
	} else
		do_IRQ(irq);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;

	if (pending & CAUSEF_IP7)
		do_IRQ(TIMER_IRQ);
	else if (pending & 0x7800) {
		if (pending & CAUSEF_IP3)
			irq_dispatch(INT1_IRQ);
		else if (pending & CAUSEF_IP4)
			irq_dispatch(INT2_IRQ);
		else if (pending & CAUSEF_IP5)
			irq_dispatch(INT3_IRQ);
		else if (pending & CAUSEF_IP6)
			irq_dispatch(INT4_IRQ);
	} else if (pending & CAUSEF_IP2)
		irq_dispatch(INT0_IRQ);
	else if (pending & CAUSEF_IP0)
		do_IRQ(MIPS_SOFTINT0_IRQ);
	else if (pending & CAUSEF_IP1)
		do_IRQ(MIPS_SOFTINT1_IRQ);
	else
		spurious_interrupt();
}

void __init arch_init_irq(void)
{
	mips_cpu_irq_init();
}
Commit	Line	Data
979934da YY	1	/*
	2	* Interrupt handing routines for NEC VR4100 series.
	3	*
ada8e951	4	* Copyright (C) 2005-2007 Yoichi Yuasa <yuasa@linux-mips.org>
979934da YY	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <linux/interrupt.h>
	21	#include <linux/module.h>
ca4d3e67	22	#include <linux/irq.h>
979934da YY	23
	24	#include <asm/irq_cpu.h>
	25	#include <asm/system.h>
66151bbd	26	#include <asm/vr41xx/irq.h>
979934da YY	27
979934da YY	28	typedef struct irq_cascade {
937a8015	29	int (*get_irq)(unsigned int);
979934da YY	30	} irq_cascade_t;
	31
	32	static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
	33
	34	static struct irqaction cascade_irqaction = {
	35	.handler = no_action,
979934da YY	36	.name = "cascade",
	37	};
	38
937a8015	39	int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int))
979934da YY	40	{
	41	int retval = 0;
	42
	43	if (irq >= NR_IRQS)
	44	return -EINVAL;
	45
	46	if (irq_cascade[irq].get_irq != NULL)
	47	free_irq(irq, NULL);
	48
	49	irq_cascade[irq].get_irq = get_irq;
	50
	51	if (get_irq != NULL) {
	52	retval = setup_irq(irq, &cascade_irqaction);
	53	if (retval < 0)
	54	irq_cascade[irq].get_irq = NULL;
	55	}
	56
	57	return retval;
	58	}
	59
	60	EXPORT_SYMBOL_GPL(cascade_irq);
	61
937a8015	62	static void irq_dispatch(unsigned int irq)
979934da YY	63	{
979934da YY	64	irq_cascade_t *cascade;
979934da YY	65
	66	if (irq >= NR_IRQS) {
	67	atomic_inc(&irq_err_count);
	68	return;
	69	}
	70
	71	cascade = irq_cascade + irq;
	72	if (cascade->get_irq != NULL) {
fbaa4e2a TG	73	struct irq_desc *desc = irq_to_desc(irq);
	74	struct irq_data *idata = irq_desc_get_irq_data(desc);
	75	struct irq_chip *chip = irq_desc_get_chip(desc);
a8347954	76	int ret;
fbaa4e2a TG	77
	78	if (chip->irq_mask_ack)
	79	chip->irq_mask_ack(idata);
364ca8a8	80	else {
fbaa4e2a TG	81	chip->irq_mask(idata);
fbaa4e2a TG	82	chip->irq_ack(idata);
364ca8a8	83	}
a8347954	84	ret = cascade->get_irq(irq);
	85	irq = ret;
	86	if (ret < 0)
979934da YY	87	atomic_inc(&irq_err_count);
979934da YY	88	else
937a8015	89	irq_dispatch(irq);
fbaa4e2a TG	90	if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
fbaa4e2a TG	91	chip->irq_unmask(idata);
979934da	92	} else
937a8015	93	do_IRQ(irq);
979934da YY	94	}
979934da YY	95
937a8015	96	asmlinkage void plat_irq_dispatch(void)
e4ac58af RB	97	{
	98	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
	99
	100	if (pending & CAUSEF_IP7)
24d55728	101	do_IRQ(TIMER_IRQ);
e4ac58af RB	102	else if (pending & 0x7800) {
e4ac58af RB	103	if (pending & CAUSEF_IP3)
24d55728	104	irq_dispatch(INT1_IRQ);
e4ac58af	105	else if (pending & CAUSEF_IP4)
24d55728	106	irq_dispatch(INT2_IRQ);
e4ac58af	107	else if (pending & CAUSEF_IP5)
24d55728	108	irq_dispatch(INT3_IRQ);
e4ac58af	109	else if (pending & CAUSEF_IP6)
24d55728	110	irq_dispatch(INT4_IRQ);
e4ac58af	111	} else if (pending & CAUSEF_IP2)
24d55728	112	irq_dispatch(INT0_IRQ);
e4ac58af	113	else if (pending & CAUSEF_IP0)
24d55728	114	do_IRQ(MIPS_SOFTINT0_IRQ);
e4ac58af	115	else if (pending & CAUSEF_IP1)
24d55728	116	do_IRQ(MIPS_SOFTINT1_IRQ);
e4ac58af	117	else
937a8015	118	spurious_interrupt();
e4ac58af	119	}
979934da YY	120
	121	void __init arch_init_irq(void)
	122	{
97dcb82d	123	mips_cpu_irq_init();
979934da	124	}