[mirror_ubuntu-artful-kernel.git] / arch / mn10300 / include / asm / mmu_context.h

/* MN10300 MMU context management
 *
 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
 * Modified by David Howells (dhowells@redhat.com)
 * - Derived from include/asm-m32r/mmu_context.h
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public Licence
 * as published by the Free Software Foundation; either version
 * 2 of the Licence, or (at your option) any later version.
 *
 *
 * This implements an algorithm to provide TLB PID mappings to provide
 * selective access to the TLB for processes, thus reducing the number of TLB
 * flushes required.
 *
 * Note, however, that the M32R algorithm is technically broken as it does not
 * handle version wrap-around, and could, theoretically, have a problem with a
 * very long lived program that sleeps long enough for the version number to
 * wrap all the way around so that its TLB mappings appear valid once again.
 */
#ifndef _ASM_MMU_CONTEXT_H
#define _ASM_MMU_CONTEXT_H

#include <linux/atomic.h>
#include <linux/mm_types.h>

#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
#include <asm-generic/mm_hooks.h>

#define MMU_CONTEXT_TLBPID_NR		256
#define MMU_CONTEXT_TLBPID_MASK		0x000000ffUL
#define MMU_CONTEXT_VERSION_MASK	0xffffff00UL
#define MMU_CONTEXT_FIRST_VERSION	0x00000100UL
#define MMU_NO_CONTEXT			0x00000000UL
#define MMU_CONTEXT_TLBPID_LOCK_NR	0

#define enter_lazy_tlb(mm, tsk)	do {} while (0)

static inline void cpu_ran_vm(int cpu, struct mm_struct *mm)
{
#ifdef CONFIG_SMP
	cpumask_set_cpu(cpu, mm_cpumask(mm));
#endif
}

static inline bool cpu_maybe_ran_vm(int cpu, struct mm_struct *mm)
{
#ifdef CONFIG_SMP
	return cpumask_test_and_set_cpu(cpu, mm_cpumask(mm));
#else
	return true;
#endif
}

#ifdef CONFIG_MN10300_TLB_USE_PIDR
extern unsigned long mmu_context_cache[NR_CPUS];
#define mm_context(mm)	(mm->context.tlbpid[smp_processor_id()])

/**
 * allocate_mmu_context - Allocate storage for the arch-specific MMU data
 * @mm: The userspace VM context being set up
 */
static inline unsigned long allocate_mmu_context(struct mm_struct *mm)
{
	unsigned long *pmc = &mmu_context_cache[smp_processor_id()];
	unsigned long mc = ++(*pmc);

	if (!(mc & MMU_CONTEXT_TLBPID_MASK)) {
		/* we exhausted the TLB PIDs of this version on this CPU, so we
		 * flush this CPU's TLB in its entirety and start new cycle */
		local_flush_tlb_all();

		/* fix the TLB version if needed (we avoid version #0 so as to
		 * distinguish MMU_NO_CONTEXT) */
		if (!mc)
			*pmc = mc = MMU_CONTEXT_FIRST_VERSION;
	}
	mm_context(mm) = mc;
	return mc;
}

/*
 * get an MMU context if one is needed
 */
static inline unsigned long get_mmu_context(struct mm_struct *mm)
{
	unsigned long mc = MMU_NO_CONTEXT, cache;

	if (mm) {
		cache = mmu_context_cache[smp_processor_id()];
		mc = mm_context(mm);

		/* if we have an old version of the context, replace it */
		if ((mc ^ cache) & MMU_CONTEXT_VERSION_MASK)
			mc = allocate_mmu_context(mm);
	}
	return mc;
}

/*
 * initialise the context related info for a new mm_struct instance
 */
static inline int init_new_context(struct task_struct *tsk,
				   struct mm_struct *mm)
{
	int num_cpus = NR_CPUS, i;

	for (i = 0; i < num_cpus; i++)
		mm->context.tlbpid[i] = MMU_NO_CONTEXT;
	return 0;
}

/*
 * after we have set current->mm to a new value, this activates the context for
 * the new mm so we see the new mappings.
 */
static inline void activate_context(struct mm_struct *mm)
{
	PIDR = get_mmu_context(mm) & MMU_CONTEXT_TLBPID_MASK;
}
#else  /* CONFIG_MN10300_TLB_USE_PIDR */

#define init_new_context(tsk, mm)	(0)
#define activate_context(mm)		local_flush_tlb()

#endif /* CONFIG_MN10300_TLB_USE_PIDR */

/**
 * destroy_context - Destroy mm context information
 * @mm: The MM being destroyed.
 *
 * Destroy context related info for an mm_struct that is about to be put to
 * rest
 */
#define destroy_context(mm)	do {} while (0)

/**
 * switch_mm - Change between userspace virtual memory contexts
 * @prev: The outgoing MM context.
 * @next: The incoming MM context.
 * @tsk: The incoming task.
 */
static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
			     struct task_struct *tsk)
{
	int cpu = smp_processor_id();

	if (prev != next) {
#ifdef CONFIG_SMP
		per_cpu(cpu_tlbstate, cpu).active_mm = next;
#endif
		cpu_ran_vm(cpu, next);
		PTBR = (unsigned long) next->pgd;
		activate_context(next);
	}
}

#define deactivate_mm(tsk, mm)	do {} while (0)
#define activate_mm(prev, next)	switch_mm((prev), (next), NULL)

#endif /* _ASM_MMU_CONTEXT_H */
Commit	Line	Data
b920de1b DH	1	/* MN10300 MMU context management
	2	*
	3	* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
	4	* Modified by David Howells (dhowells@redhat.com)
	5	* - Derived from include/asm-m32r/mmu_context.h
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public Licence
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the Licence, or (at your option) any later version.
	11	*
	12	*
	13	* This implements an algorithm to provide TLB PID mappings to provide
	14	* selective access to the TLB for processes, thus reducing the number of TLB
	15	* flushes required.
	16	*
	17	* Note, however, that the M32R algorithm is technically broken as it does not
	18	* handle version wrap-around, and could, theoretically, have a problem with a
	19	* very long lived program that sleeps long enough for the version number to
	20	* wrap all the way around so that its TLB mappings appear valid once again.
	21	*/
	22	#ifndef _ASM_MMU_CONTEXT_H
	23	#define _ASM_MMU_CONTEXT_H
	24
60063497	25	#include <linux/atomic.h>
589ee628 IM	26	#include <linux/mm_types.h>
589ee628 IM	27
b920de1b DH	28	#include <asm/pgalloc.h>
	29	#include <asm/tlbflush.h>
	30	#include <asm-generic/mm_hooks.h>
	31
a9bc60eb	32	#define MMU_CONTEXT_TLBPID_NR 256
b920de1b DH	33	#define MMU_CONTEXT_TLBPID_MASK 0x000000ffUL
	34	#define MMU_CONTEXT_VERSION_MASK 0xffffff00UL
	35	#define MMU_CONTEXT_FIRST_VERSION 0x00000100UL
	36	#define MMU_NO_CONTEXT 0x00000000UL
a9bc60eb	37	#define MMU_CONTEXT_TLBPID_LOCK_NR 0
b920de1b DH	38
	39	#define enter_lazy_tlb(mm, tsk) do {} while (0)
	40
965ea4bb AT	41	static inline void cpu_ran_vm(int cpu, struct mm_struct *mm)
	42	{
	43	#ifdef CONFIG_SMP
	44	cpumask_set_cpu(cpu, mm_cpumask(mm));
	45	#endif
	46	}
	47
	48	static inline bool cpu_maybe_ran_vm(int cpu, struct mm_struct *mm)
	49	{
	50	#ifdef CONFIG_SMP
	51	return cpumask_test_and_set_cpu(cpu, mm_cpumask(mm));
	52	#else
	53	return true;
	54	#endif
	55	}
	56
a9bc60eb AT	57	#ifdef CONFIG_MN10300_TLB_USE_PIDR
	58	extern unsigned long mmu_context_cache[NR_CPUS];
	59	#define mm_context(mm) (mm->context.tlbpid[smp_processor_id()])
b920de1b	60
a9bc60eb AT	61	/**
	62	* allocate_mmu_context - Allocate storage for the arch-specific MMU data
	63	* @mm: The userspace VM context being set up
b920de1b DH	64	*/
	65	static inline unsigned long allocate_mmu_context(struct mm_struct *mm)
	66	{
	67	unsigned long *pmc = &mmu_context_cache[smp_processor_id()];
	68	unsigned long mc = ++(*pmc);
	69
	70	if (!(mc & MMU_CONTEXT_TLBPID_MASK)) {
	71	/* we exhausted the TLB PIDs of this version on this CPU, so we
	72	* flush this CPU's TLB in its entirety and start new cycle */
492e6751	73	local_flush_tlb_all();
b920de1b DH	74
b920de1b DH	75	/* fix the TLB version if needed (we avoid version #0 so as to
aa5e5dc2	76	* distinguish MMU_NO_CONTEXT) */
b920de1b DH	77	if (!mc)
	78	*pmc = mc = MMU_CONTEXT_FIRST_VERSION;
	79	}
	80	mm_context(mm) = mc;
	81	return mc;
	82	}
	83
	84	/*
	85	* get an MMU context if one is needed
	86	*/
	87	static inline unsigned long get_mmu_context(struct mm_struct *mm)
	88	{
	89	unsigned long mc = MMU_NO_CONTEXT, cache;
	90
	91	if (mm) {
	92	cache = mmu_context_cache[smp_processor_id()];
	93	mc = mm_context(mm);
	94
	95	/* if we have an old version of the context, replace it */
	96	if ((mc ^ cache) & MMU_CONTEXT_VERSION_MASK)
	97	mc = allocate_mmu_context(mm);
	98	}
	99	return mc;
	100	}
	101
	102	/*
	103	* initialise the context related info for a new mm_struct instance
	104	*/
	105	static inline int init_new_context(struct task_struct *tsk,
	106	struct mm_struct *mm)
	107	{
	108	int num_cpus = NR_CPUS, i;
	109
	110	for (i = 0; i < num_cpus; i++)
	111	mm->context.tlbpid[i] = MMU_NO_CONTEXT;
	112	return 0;
	113	}
	114
b920de1b DH	115	/*
	116	* after we have set current->mm to a new value, this activates the context for
	117	* the new mm so we see the new mappings.
	118	*/
a9bc60eb	119	static inline void activate_context(struct mm_struct *mm)
b920de1b DH	120	{
	121	PIDR = get_mmu_context(mm) & MMU_CONTEXT_TLBPID_MASK;
	122	}
a9bc60eb	123	#else /* CONFIG_MN10300_TLB_USE_PIDR */
b920de1b	124
a9bc60eb AT	125	#define init_new_context(tsk, mm) (0)
	126	#define activate_context(mm) local_flush_tlb()
	127
	128	#endif /* CONFIG_MN10300_TLB_USE_PIDR */
	129
	130	/**
	131	* destroy_context - Destroy mm context information
	132	* @mm: The MM being destroyed.
	133	*
	134	* Destroy context related info for an mm_struct that is about to be put to
	135	* rest
	136	*/
	137	#define destroy_context(mm) do {} while (0)
	138
	139	/**
	140	* switch_mm - Change between userspace virtual memory contexts
	141	* @prev: The outgoing MM context.
	142	* @next: The incoming MM context.
	143	* @tsk: The incoming task.
b920de1b DH	144	*/
	145	static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
	146	struct task_struct *tsk)
	147	{
965ea4bb AT	148	int cpu = smp_processor_id();
965ea4bb AT	149
b920de1b	150	if (prev != next) {
965ea4bb AT	151	#ifdef CONFIG_SMP
	152	per_cpu(cpu_tlbstate, cpu).active_mm = next;
	153	#endif
	154	cpu_ran_vm(cpu, next);
b920de1b	155	PTBR = (unsigned long) next->pgd;
a9bc60eb	156	activate_context(next);
b920de1b DH	157	}
	158	}
	159
	160	#define deactivate_mm(tsk, mm) do {} while (0)
	161	#define activate_mm(prev, next) switch_mm((prev), (next), NULL)
	162
	163	#endif /* _ASM_MMU_CONTEXT_H */