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368dd5ac AT |
1 | /* Cache specification |
2 | * | |
3 | * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * Modified by Matsushita Electric Industrial Co., Ltd. | |
7 | * Modifications: | |
8 | * 13-Nov-2006 MEI Add L1_CACHE_SHIFT_MAX definition. | |
9 | * 29-Jul-2008 MEI Add define for MN10300_HAS_AREAPURGE_REG. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | #ifndef _ASM_PROC_CACHE_H | |
17 | #define _ASM_PROC_CACHE_H | |
18 | ||
19 | /* | |
20 | * L1 cache | |
21 | */ | |
22 | #define L1_CACHE_NWAYS 4 /* number of ways in caches */ | |
23 | #define L1_CACHE_NENTRIES 128 /* number of entries in each way */ | |
24 | #define L1_CACHE_BYTES 32 /* bytes per entry */ | |
25 | #define L1_CACHE_SHIFT 5 /* shift for bytes per entry */ | |
26 | #define L1_CACHE_WAYDISP 0x1000 /* distance from one way to the next */ | |
27 | ||
28 | #define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */ | |
29 | #define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ | |
30 | #define L1_CACHE_TAG_ENTRY 0x00000fe0 /* cache tag entry address mask */ | |
31 | #define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ | |
7f386ac3 | 32 | #define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY) |
368dd5ac AT |
33 | |
34 | /* | |
35 | * specification of the interval between interrupt checking intervals whilst | |
36 | * managing the cache with the interrupts disabled | |
37 | */ | |
38 | #define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4 | |
39 | ||
40 | /* | |
41 | * The size of range at which it becomes more economical to just flush the | |
42 | * whole cache rather than trying to flush the specified range. | |
43 | */ | |
44 | #define MN10300_DCACHE_FLUSH_BORDER \ | |
45 | +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) | |
46 | #define MN10300_DCACHE_FLUSH_INV_BORDER \ | |
47 | +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES) | |
48 | ||
49 | #endif /* _ASM_PROC_CACHE_H */ |