projects / mirror_ubuntu-focal-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 368dd5ac AT |
1 | /* MN10300/AM33v2 Microcontroller SMP registers |
| 2 | * | |
| 3 | * Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd. | |
| 4 | * All Rights Reserved. | |
| 5 | * Created: | |
| 6 | * 13-Nov-2006 MEI Add extended cache and atomic operation register | |
| 7 | * for SMP support. | |
| 8 | * 23-Feb-2007 MEI Add define for gdbstub SMP. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License | |
| 12 | * as published by the Free Software Foundation; either version | |
| 13 | * 2 of the License, or (at your option) any later version. | |
| 14 | */ | |
| 15 | ||
| 16 | #ifndef _ASM_PROC_SMP_REGS_H | |
| 17 | #define _ASM_PROC_SMP_REGS_H | |
| 18 | ||
| 19 | #ifdef __KERNEL__ | |
| 20 | ||
| 21 | #ifndef __ASSEMBLY__ | |
| 22 | #include <linux/types.h> | |
| 23 | #endif | |
| 24 | #include <asm/cpu-regs.h> | |
| 25 | ||
| 26 | /* | |
| 27 | * Reference to the interrupt controllers of other CPUs | |
| 28 | */ | |
| 29 | #define CROSS_ICR_CPU_SHIFT 16 | |
| 30 | ||
| 31 | #define CROSS_GxICR(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \ | |
| 32 | ((X) >= 64 && (X) < 192) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u16) | |
| 33 | #define CROSS_GxICR_u8(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \ | |
| 34 | (((X) >= 64) && ((X) < 192)) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u8) | |
| 35 | ||
| 36 | /* CPU ID register */ | |
| 37 | #define CPUID __SYSREGC(0xc0000054, u32) | |
| 38 | #define CPUID_MASK 0x00000007 /* CPU ID mask */ | |
| 39 | ||
| 40 | /* extended cache control register */ | |
| 41 | #define ECHCTR __SYSREG(0xc0000c20, u32) | |
| 42 | #define ECHCTR_IBCM 0x00000001 /* instruction cache broad cast mask */ | |
| 43 | #define ECHCTR_DBCM 0x00000002 /* data cache broad cast mask */ | |
| 44 | #define ECHCTR_ISPM 0x00000004 /* instruction cache snoop mask */ | |
| 45 | #define ECHCTR_DSPM 0x00000008 /* data cache snoop mask */ | |
| 46 | ||
| 47 | #define NMIAGR __SYSREG(0xd400013c, u16) | |
| 48 | #define NMIAGR_GN 0x03fc | |
| 49 | ||
| 50 | #endif /* __KERNEL__ */ | |
| 51 | #endif /* _ASM_PROC_SMP_REGS_H */ |