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7f9ea6b7 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
e1d82de6 GH |
2 | // Copyright (C) 2005-2017 Andes Technology Corporation |
3 | ||
4 | #ifndef __NDS32_BITFIELD_H__ | |
5 | #define __NDS32_BITFIELD_H__ | |
6 | /****************************************************************************** | |
7 | * cr0: CPU_VER (CPU Version Register) | |
8 | *****************************************************************************/ | |
9 | #define CPU_VER_offCFGID 0 /* Minor configuration */ | |
10 | #define CPU_VER_offREV 16 /* Revision of the CPU version */ | |
11 | #define CPU_VER_offCPUID 24 /* Major CPU versions */ | |
12 | ||
13 | #define CPU_VER_mskCFGID ( 0xFFFF << CPU_VER_offCFGID ) | |
14 | #define CPU_VER_mskREV ( 0xFF << CPU_VER_offREV ) | |
15 | #define CPU_VER_mskCPUID ( 0xFF << CPU_VER_offCPUID ) | |
16 | ||
17 | /****************************************************************************** | |
18 | * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register) | |
19 | *****************************************************************************/ | |
20 | #define ICM_CFG_offISET 0 /* I-cache sets (# of cache lines) per way */ | |
21 | #define ICM_CFG_offIWAY 3 /* I-cache ways */ | |
22 | #define ICM_CFG_offISZ 6 /* I-cache line size */ | |
23 | #define ICM_CFG_offILCK 9 /* I-cache locking support */ | |
24 | #define ICM_CFG_offILMB 10 /* On-chip ILM banks */ | |
25 | #define ICM_CFG_offBSAV 13 /* ILM base register alignment version */ | |
26 | /* bit 15:31 reserved */ | |
27 | ||
28 | #define ICM_CFG_mskISET ( 0x7 << ICM_CFG_offISET ) | |
29 | #define ICM_CFG_mskIWAY ( 0x7 << ICM_CFG_offIWAY ) | |
30 | #define ICM_CFG_mskISZ ( 0x7 << ICM_CFG_offISZ ) | |
31 | #define ICM_CFG_mskILCK ( 0x1 << ICM_CFG_offILCK ) | |
32 | #define ICM_CFG_mskILMB ( 0x7 << ICM_CFG_offILMB ) | |
33 | #define ICM_CFG_mskBSAV ( 0x3 << ICM_CFG_offBSAV ) | |
34 | ||
35 | /****************************************************************************** | |
36 | * cr2: DCM_CFG (Data Cache/Memory Configuration Register) | |
37 | *****************************************************************************/ | |
38 | #define DCM_CFG_offDSET 0 /* D-cache sets (# of cache lines) per way */ | |
39 | #define DCM_CFG_offDWAY 3 /* D-cache ways */ | |
40 | #define DCM_CFG_offDSZ 6 /* D-cache line size */ | |
41 | #define DCM_CFG_offDLCK 9 /* D-cache locking support */ | |
42 | #define DCM_CFG_offDLMB 10 /* On-chip DLM banks */ | |
43 | #define DCM_CFG_offBSAV 13 /* DLM base register alignment version */ | |
44 | /* bit 15:31 reserved */ | |
45 | ||
46 | #define DCM_CFG_mskDSET ( 0x7 << DCM_CFG_offDSET ) | |
47 | #define DCM_CFG_mskDWAY ( 0x7 << DCM_CFG_offDWAY ) | |
48 | #define DCM_CFG_mskDSZ ( 0x7 << DCM_CFG_offDSZ ) | |
49 | #define DCM_CFG_mskDLCK ( 0x1 << DCM_CFG_offDLCK ) | |
50 | #define DCM_CFG_mskDLMB ( 0x7 << DCM_CFG_offDLMB ) | |
51 | #define DCM_CFG_mskBSAV ( 0x3 << DCM_CFG_offBSAV ) | |
52 | ||
53 | /****************************************************************************** | |
54 | * cr3: MMU_CFG (MMU Configuration Register) | |
55 | *****************************************************************************/ | |
56 | #define MMU_CFG_offMMPS 0 /* Memory management protection scheme */ | |
57 | #define MMU_CFG_offMMPV 2 /* Memory management protection version number */ | |
58 | #define MMU_CFG_offFATB 7 /* Fully-associative or non-fully-associative TLB */ | |
59 | ||
60 | #define MMU_CFG_offTBW 8 /* TLB ways(non-associative) TBS */ | |
61 | #define MMU_CFG_offTBS 11 /* TLB sets per way(non-associative) TBS */ | |
62 | /* bit 14:14 reserved */ | |
63 | ||
64 | #define MMU_CFG_offEP8MIN4 15 /* 8KB page supported while minimum page is 4KB */ | |
65 | #define MMU_CFG_offfEPSZ 16 /* Extra page size supported */ | |
66 | #define MMU_CFG_offTLBLCK 24 /* TLB locking support */ | |
67 | #define MMU_CFG_offHPTWK 25 /* Hardware Page Table Walker implemented */ | |
68 | #define MMU_CFG_offDE 26 /* Default endian */ | |
69 | #define MMU_CFG_offNTPT 27 /* Partitions for non-translated attributes */ | |
70 | #define MMU_CFG_offIVTB 28 /* Invisible TLB */ | |
71 | #define MMU_CFG_offVLPT 29 /* VLPT for fast TLB fill handling implemented */ | |
72 | #define MMU_CFG_offNTME 30 /* Non-translated VA to PA mapping */ | |
73 | /* bit 31 reserved */ | |
74 | ||
75 | #define MMU_CFG_mskMMPS ( 0x3 << MMU_CFG_offMMPS ) | |
76 | #define MMU_CFG_mskMMPV ( 0x1F << MMU_CFG_offMMPV ) | |
77 | #define MMU_CFG_mskFATB ( 0x1 << MMU_CFG_offFATB ) | |
78 | #define MMU_CFG_mskTBW ( 0x7 << MMU_CFG_offTBW ) | |
79 | #define MMU_CFG_mskTBS ( 0x7 << MMU_CFG_offTBS ) | |
80 | #define MMU_CFG_mskEP8MIN4 ( 0x1 << MMU_CFG_offEP8MIN4 ) | |
81 | #define MMU_CFG_mskfEPSZ ( 0xFF << MMU_CFG_offfEPSZ ) | |
82 | #define MMU_CFG_mskTLBLCK ( 0x1 << MMU_CFG_offTLBLCK ) | |
83 | #define MMU_CFG_mskHPTWK ( 0x1 << MMU_CFG_offHPTWK ) | |
84 | #define MMU_CFG_mskDE ( 0x1 << MMU_CFG_offDE ) | |
85 | #define MMU_CFG_mskNTPT ( 0x1 << MMU_CFG_offNTPT ) | |
86 | #define MMU_CFG_mskIVTB ( 0x1 << MMU_CFG_offIVTB ) | |
87 | #define MMU_CFG_mskVLPT ( 0x1 << MMU_CFG_offVLPT ) | |
88 | #define MMU_CFG_mskNTME ( 0x1 << MMU_CFG_offNTME ) | |
89 | ||
90 | /****************************************************************************** | |
91 | * cr4: MSC_CFG (Misc Configuration Register) | |
92 | *****************************************************************************/ | |
93 | #define MSC_CFG_offEDM 0 | |
94 | #define MSC_CFG_offLMDMA 1 | |
95 | #define MSC_CFG_offPFM 2 | |
96 | #define MSC_CFG_offHSMP 3 | |
97 | #define MSC_CFG_offTRACE 4 | |
98 | #define MSC_CFG_offDIV 5 | |
99 | #define MSC_CFG_offMAC 6 | |
100 | #define MSC_CFG_offAUDIO 7 | |
101 | #define MSC_CFG_offL2C 9 | |
102 | #define MSC_CFG_offRDREG 10 | |
103 | #define MSC_CFG_offADR24 11 | |
104 | #define MSC_CFG_offINTLC 12 | |
105 | #define MSC_CFG_offBASEV 13 | |
106 | #define MSC_CFG_offNOD 16 | |
107 | /* bit 13:31 reserved */ | |
108 | ||
109 | #define MSC_CFG_mskEDM ( 0x1 << MSC_CFG_offEDM ) | |
110 | #define MSC_CFG_mskLMDMA ( 0x1 << MSC_CFG_offLMDMA ) | |
111 | #define MSC_CFG_mskPFM ( 0x1 << MSC_CFG_offPFM ) | |
112 | #define MSC_CFG_mskHSMP ( 0x1 << MSC_CFG_offHSMP ) | |
113 | #define MSC_CFG_mskTRACE ( 0x1 << MSC_CFG_offTRACE ) | |
114 | #define MSC_CFG_mskDIV ( 0x1 << MSC_CFG_offDIV ) | |
115 | #define MSC_CFG_mskMAC ( 0x1 << MSC_CFG_offMAC ) | |
116 | #define MSC_CFG_mskAUDIO ( 0x3 << MSC_CFG_offAUDIO ) | |
117 | #define MSC_CFG_mskL2C ( 0x1 << MSC_CFG_offL2C ) | |
118 | #define MSC_CFG_mskRDREG ( 0x1 << MSC_CFG_offRDREG ) | |
119 | #define MSC_CFG_mskADR24 ( 0x1 << MSC_CFG_offADR24 ) | |
120 | #define MSC_CFG_mskINTLC ( 0x1 << MSC_CFG_offINTLC ) | |
121 | #define MSC_CFG_mskBASEV ( 0x7 << MSC_CFG_offBASEV ) | |
122 | #define MSC_CFG_mskNOD ( 0x1 << MSC_CFG_offNOD ) | |
123 | ||
124 | /****************************************************************************** | |
125 | * cr5: CORE_CFG (Core Identification Register) | |
126 | *****************************************************************************/ | |
127 | #define CORE_ID_offCOREID 0 | |
128 | /* bit 4:31 reserved */ | |
129 | ||
130 | #define CORE_ID_mskCOREID ( 0xF << CORE_ID_offCOREID ) | |
131 | ||
132 | /****************************************************************************** | |
133 | * cr6: FUCOP_EXIST (FPU and Coprocessor Existence Configuration Register) | |
134 | *****************************************************************************/ | |
135 | #define FUCOP_EXIST_offCP0EX 0 | |
136 | #define FUCOP_EXIST_offCP1EX 1 | |
137 | #define FUCOP_EXIST_offCP2EX 2 | |
138 | #define FUCOP_EXIST_offCP3EX 3 | |
139 | #define FUCOP_EXIST_offCP0ISFPU 31 | |
140 | ||
141 | #define FUCOP_EXIST_mskCP0EX ( 0x1 << FUCOP_EXIST_offCP0EX ) | |
142 | #define FUCOP_EXIST_mskCP1EX ( 0x1 << FUCOP_EXIST_offCP1EX ) | |
143 | #define FUCOP_EXIST_mskCP2EX ( 0x1 << FUCOP_EXIST_offCP2EX ) | |
144 | #define FUCOP_EXIST_mskCP3EX ( 0x1 << FUCOP_EXIST_offCP3EX ) | |
145 | #define FUCOP_EXIST_mskCP0ISFPU ( 0x1 << FUCOP_EXIST_offCP0ISFPU ) | |
146 | ||
147 | /****************************************************************************** | |
148 | * ir0: PSW (Processor Status Word Register) | |
149 | * ir1: IPSW (Interruption PSW Register) | |
150 | * ir2: P_IPSW (Previous IPSW Register) | |
151 | *****************************************************************************/ | |
152 | #define PSW_offGIE 0 /* Global Interrupt Enable */ | |
153 | #define PSW_offINTL 1 /* Interruption Stack Level */ | |
154 | #define PSW_offPOM 3 /* Processor Operation Mode, User/Superuser */ | |
155 | #define PSW_offBE 5 /* Endianness for data memory access, 1:MSB, 0:LSB */ | |
156 | #define PSW_offIT 6 /* Enable instruction address translation */ | |
157 | #define PSW_offDT 7 /* Enable data address translation */ | |
158 | #define PSW_offIME 8 /* Instruction Machine Error flag */ | |
159 | #define PSW_offDME 9 /* Data Machine Error flag */ | |
160 | #define PSW_offDEX 10 /* Debug Exception */ | |
161 | #define PSW_offHSS 11 /* Hardware Single Stepping */ | |
162 | #define PSW_offDRBE 12 /* Device Register Endian Mode */ | |
163 | #define PSW_offAEN 13 /* Audio ISA special feature */ | |
164 | #define PSW_offWBNA 14 /* Write Back Non-Allocate */ | |
165 | #define PSW_offIFCON 15 /* IFC On */ | |
166 | #define PSW_offCPL 16 /* Current Priority Level */ | |
167 | /* bit 19:31 reserved */ | |
168 | ||
169 | #define PSW_mskGIE ( 0x1 << PSW_offGIE ) | |
170 | #define PSW_mskINTL ( 0x3 << PSW_offINTL ) | |
171 | #define PSW_mskPOM ( 0x3 << PSW_offPOM ) | |
172 | #define PSW_mskBE ( 0x1 << PSW_offBE ) | |
173 | #define PSW_mskIT ( 0x1 << PSW_offIT ) | |
174 | #define PSW_mskDT ( 0x1 << PSW_offDT ) | |
175 | #define PSW_mskIME ( 0x1 << PSW_offIME ) | |
176 | #define PSW_mskDME ( 0x1 << PSW_offDME ) | |
177 | #define PSW_mskDEX ( 0x1 << PSW_offDEX ) | |
178 | #define PSW_mskHSS ( 0x1 << PSW_offHSS ) | |
179 | #define PSW_mskDRBE ( 0x1 << PSW_offDRBE ) | |
180 | #define PSW_mskAEN ( 0x1 << PSW_offAEN ) | |
181 | #define PSW_mskWBNA ( 0x1 << PSW_offWBNA ) | |
182 | #define PSW_mskIFCON ( 0x1 << PSW_offIFCON ) | |
183 | #define PSW_mskCPL ( 0x7 << PSW_offCPL ) | |
184 | ||
185 | #define PSW_SYSTEM ( 1 << PSW_offPOM ) | |
186 | #define PSW_INTL_1 ( 1 << PSW_offINTL ) | |
187 | #define PSW_CPL_NO ( 0 << PSW_offCPL ) | |
188 | #define PSW_CPL_ANY ( 7 << PSW_offCPL ) | |
189 | ||
190 | #define PSW_clr (PSW_mskGIE|PSW_mskINTL|PSW_mskPOM|PSW_mskIT|PSW_mskDT|PSW_mskIME|PSW_mskWBNA) | |
191 | #ifdef __NDS32_EB__ | |
192 | #ifdef CONFIG_WBNA | |
193 | #define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE) | |
194 | #else | |
195 | #define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE) | |
196 | #endif | |
197 | #else | |
198 | #ifdef CONFIG_WBNA | |
199 | #define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT) | |
200 | #else | |
201 | #define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT) | |
202 | #endif | |
203 | #endif | |
204 | /****************************************************************************** | |
205 | * ir3: IVB (Interruption Vector Base Register) | |
206 | *****************************************************************************/ | |
207 | /* bit 0:12 reserved */ | |
208 | #define IVB_offNIVIC 1 /* Number of input for IVIC Controller */ | |
209 | #define IVB_offIVIC_VER 11 /* IVIC Version */ | |
210 | #define IVB_offEVIC 13 /* External Vector Interrupt Controller mode */ | |
211 | #define IVB_offESZ 14 /* Size of each vector entry */ | |
212 | #define IVB_offIVBASE 16 /* BasePA of interrupt vector table */ | |
213 | ||
214 | #define IVB_mskNIVIC ( 0x7 << IVB_offNIVIC ) | |
215 | #define IVB_mskIVIC_VER ( 0x3 << IVB_offIVIC_VER ) | |
216 | #define IVB_mskEVIC ( 0x1 << IVB_offEVIC ) | |
217 | #define IVB_mskESZ ( 0x3 << IVB_offESZ ) | |
218 | #define IVB_mskIVBASE ( 0xFFFF << IVB_offIVBASE ) | |
219 | ||
220 | #define IVB_valESZ4 0 | |
221 | #define IVB_valESZ16 1 | |
222 | #define IVB_valESZ64 2 | |
223 | #define IVB_valESZ256 3 | |
224 | /****************************************************************************** | |
225 | * ir4: EVA (Exception Virtual Address Register) | |
226 | * ir5: P_EVA (Previous EVA Register) | |
227 | *****************************************************************************/ | |
228 | ||
229 | /* This register contains the VA that causes the exception */ | |
230 | ||
231 | /****************************************************************************** | |
232 | * ir6: ITYPE (Interruption Type Register) | |
233 | * ir7: P_ITYPE (Previous ITYPE Register) | |
234 | *****************************************************************************/ | |
235 | #define ITYPE_offETYPE 0 /* Exception Type */ | |
236 | #define ITYPE_offINST 4 /* Exception caused by insn fetch or data access */ | |
237 | /* bit 5:15 reserved */ | |
238 | #define ITYPE_offVECTOR 5 /* Vector */ | |
239 | #define ITYPE_offSWID 16 /* SWID of debugging exception */ | |
240 | /* bit 31:31 reserved */ | |
241 | ||
242 | #define ITYPE_mskETYPE ( 0xF << ITYPE_offETYPE ) | |
243 | #define ITYPE_mskINST ( 0x1 << ITYPE_offINST ) | |
244 | #define ITYPE_mskVECTOR ( 0x7F << ITYPE_offVECTOR ) | |
245 | #define ITYPE_mskSWID ( 0x7FFF << ITYPE_offSWID ) | |
246 | ||
247 | /* Additional definitions for ITYPE register */ | |
248 | #define ITYPE_offSTYPE 16 /* Arithmetic Sub Type */ | |
249 | #define ITYPE_offCPID 20 /* Co-Processor ID which generate the exception */ | |
250 | ||
251 | #define ITYPE_mskSTYPE ( 0xF << ITYPE_offSTYPE ) | |
252 | #define ITYPE_mskCPID ( 0x3 << ITYPE_offCPID ) | |
253 | ||
e46bf83c VC |
254 | /* Additional definitions of ITYPE register for FPU */ |
255 | #define FPU_DISABLE_EXCEPTION (0x1 << ITYPE_offSTYPE) | |
256 | #define FPU_EXCEPTION (0x2 << ITYPE_offSTYPE) | |
257 | #define FPU_CPID 0 /* FPU Co-Processor ID is 0 */ | |
258 | ||
e1d82de6 GH |
259 | #define NDS32_VECTOR_mskNONEXCEPTION 0x78 |
260 | #define NDS32_VECTOR_offEXCEPTION 8 | |
261 | #define NDS32_VECTOR_offINTERRUPT 9 | |
262 | ||
263 | /* Interrupt vector entry */ | |
264 | #define ENTRY_RESET_NMI 0 | |
265 | #define ENTRY_TLB_FILL 1 | |
266 | #define ENTRY_PTE_NOT_PRESENT 2 | |
267 | #define ENTRY_TLB_MISC 3 | |
268 | #define ENTRY_TLB_VLPT_MISS 4 | |
269 | #define ENTRY_MACHINE_ERROR 5 | |
270 | #define ENTRY_DEBUG_RELATED 6 | |
271 | #define ENTRY_GENERAL_EXCPETION 7 | |
272 | #define ENTRY_SYSCALL 8 | |
273 | ||
274 | /* PTE not present exception definition */ | |
275 | #define ETYPE_NON_LEAF_PTE_NOT_PRESENT 0 | |
276 | #define ETYPE_LEAF_PTE_NOT_PRESENT 1 | |
277 | ||
278 | /* General exception ETYPE definition */ | |
279 | #define ETYPE_ALIGNMENT_CHECK 0 | |
280 | #define ETYPE_RESERVED_INSTRUCTION 1 | |
281 | #define ETYPE_TRAP 2 | |
282 | #define ETYPE_ARITHMETIC 3 | |
283 | #define ETYPE_PRECISE_BUS_ERROR 4 | |
284 | #define ETYPE_IMPRECISE_BUS_ERROR 5 | |
285 | #define ETYPE_COPROCESSOR 6 | |
286 | #define ETYPE_RESERVED_VALUE 7 | |
287 | #define ETYPE_NONEXISTENT_MEM_ADDRESS 8 | |
288 | #define ETYPE_MPZIU_CONTROL 9 | |
289 | #define ETYPE_NEXT_PRECISE_STACK_OFL 10 | |
290 | ||
291 | /* Kerenl reserves software ID */ | |
292 | #define SWID_RAISE_INTERRUPT_LEVEL 0x1a /* SWID_RAISE_INTERRUPT_LEVEL is used to | |
293 | * raise interrupt level for debug exception | |
294 | */ | |
295 | ||
296 | /****************************************************************************** | |
297 | * ir8: MERR (Machine Error Log Register) | |
298 | *****************************************************************************/ | |
299 | /* bit 0:30 reserved */ | |
300 | #define MERR_offBUSERR 31 /* Bus error caused by a load insn */ | |
301 | ||
302 | #define MERR_mskBUSERR ( 0x1 << MERR_offBUSERR ) | |
303 | ||
304 | /****************************************************************************** | |
305 | * ir9: IPC (Interruption Program Counter Register) | |
306 | * ir10: P_IPC (Previous IPC Register) | |
307 | * ir11: OIPC (Overflow Interruption Program Counter Register) | |
308 | *****************************************************************************/ | |
309 | ||
310 | /* This is the shadow stack register of the Program Counter */ | |
311 | ||
312 | /****************************************************************************** | |
313 | * ir12: P_P0 (Previous P0 Register) | |
314 | * ir13: P_P1 (Previous P1 Register) | |
315 | *****************************************************************************/ | |
316 | ||
317 | /* These are shadow registers of $p0 and $p1 */ | |
318 | ||
319 | /****************************************************************************** | |
320 | * ir14: INT_MASK (Interruption Masking Register) | |
321 | *****************************************************************************/ | |
322 | #define INT_MASK_offH0IM 0 /* Hardware Interrupt 0 Mask bit */ | |
323 | #define INT_MASK_offH1IM 1 /* Hardware Interrupt 1 Mask bit */ | |
324 | #define INT_MASK_offH2IM 2 /* Hardware Interrupt 2 Mask bit */ | |
325 | #define INT_MASK_offH3IM 3 /* Hardware Interrupt 3 Mask bit */ | |
326 | #define INT_MASK_offH4IM 4 /* Hardware Interrupt 4 Mask bit */ | |
327 | #define INT_MASK_offH5IM 5 /* Hardware Interrupt 5 Mask bit */ | |
328 | /* bit 6:15 reserved */ | |
329 | #define INT_MASK_offSIM 16 /* Software Interrupt Mask bit */ | |
330 | /* bit 17:29 reserved */ | |
331 | #define INT_MASK_offIDIVZE 30 /* Enable detection for Divide-By-Zero */ | |
332 | #define INT_MASK_offDSSIM 31 /* Default Single Stepping Interruption Mask */ | |
333 | ||
334 | #define INT_MASK_mskH0IM ( 0x1 << INT_MASK_offH0IM ) | |
335 | #define INT_MASK_mskH1IM ( 0x1 << INT_MASK_offH1IM ) | |
336 | #define INT_MASK_mskH2IM ( 0x1 << INT_MASK_offH2IM ) | |
337 | #define INT_MASK_mskH3IM ( 0x1 << INT_MASK_offH3IM ) | |
338 | #define INT_MASK_mskH4IM ( 0x1 << INT_MASK_offH4IM ) | |
339 | #define INT_MASK_mskH5IM ( 0x1 << INT_MASK_offH5IM ) | |
340 | #define INT_MASK_mskSIM ( 0x1 << INT_MASK_offSIM ) | |
341 | #define INT_MASK_mskIDIVZE ( 0x1 << INT_MASK_offIDIVZE ) | |
342 | #define INT_MASK_mskDSSIM ( 0x1 << INT_MASK_offDSSIM ) | |
343 | ||
8769c223 | 344 | #define INT_MASK_INITAIAL_VAL (INT_MASK_mskDSSIM|INT_MASK_mskIDIVZE) |
e1d82de6 GH |
345 | |
346 | /****************************************************************************** | |
347 | * ir15: INT_PEND (Interrupt Pending Register) | |
348 | *****************************************************************************/ | |
349 | #define INT_PEND_offH0I 0 /* Hardware Interrupt 0 pending bit */ | |
350 | #define INT_PEND_offH1I 1 /* Hardware Interrupt 1 pending bit */ | |
351 | #define INT_PEND_offH2I 2 /* Hardware Interrupt 2 pending bit */ | |
352 | #define INT_PEND_offH3I 3 /* Hardware Interrupt 3 pending bit */ | |
353 | #define INT_PEND_offH4I 4 /* Hardware Interrupt 4 pending bit */ | |
354 | #define INT_PEND_offH5I 5 /* Hardware Interrupt 5 pending bit */ | |
355 | ||
356 | #define INT_PEND_offCIPL 0 /* Current Interrupt Priority Level */ | |
357 | ||
358 | /* bit 6:15 reserved */ | |
359 | #define INT_PEND_offSWI 16 /* Software Interrupt pending bit */ | |
360 | /* bit 17:31 reserved */ | |
361 | ||
362 | #define INT_PEND_mskH0I ( 0x1 << INT_PEND_offH0I ) | |
363 | #define INT_PEND_mskH1I ( 0x1 << INT_PEND_offH1I ) | |
364 | #define INT_PEND_mskH2I ( 0x1 << INT_PEND_offH2I ) | |
365 | #define INT_PEND_mskH3I ( 0x1 << INT_PEND_offH3I ) | |
366 | #define INT_PEND_mskH4I ( 0x1 << INT_PEND_offH4I ) | |
367 | #define INT_PEND_mskH5I ( 0x1 << INT_PEND_offH5I ) | |
368 | #define INT_PEND_mskCIPL ( 0x1 << INT_PEND_offCIPL ) | |
369 | #define INT_PEND_mskSWI ( 0x1 << INT_PEND_offSWI ) | |
370 | ||
371 | /****************************************************************************** | |
372 | * mr0: MMU_CTL (MMU Control Register) | |
373 | *****************************************************************************/ | |
374 | #define MMU_CTL_offD 0 /* Default minimum page size */ | |
375 | #define MMU_CTL_offNTC0 1 /* Non-Translated Cachebility of partition 0 */ | |
376 | #define MMU_CTL_offNTC1 3 /* Non-Translated Cachebility of partition 1 */ | |
377 | #define MMU_CTL_offNTC2 5 /* Non-Translated Cachebility of partition 2 */ | |
378 | #define MMU_CTL_offNTC3 7 /* Non-Translated Cachebility of partition 3 */ | |
379 | #define MMU_CTL_offTBALCK 9 /* TLB all-lock resolution scheme */ | |
380 | #define MMU_CTL_offMPZIU 10 /* Multiple Page Size In Use bit */ | |
381 | #define MMU_CTL_offNTM0 11 /* Non-Translated VA to PA of partition 0 */ | |
382 | #define MMU_CTL_offNTM1 13 /* Non-Translated VA to PA of partition 1 */ | |
383 | #define MMU_CTL_offNTM2 15 /* Non-Translated VA to PA of partition 2 */ | |
384 | #define MMU_CTL_offNTM3 17 /* Non-Translated VA to PA of partition 3 */ | |
385 | #define MMU_CTL_offUNA 23 /* Unaligned access */ | |
386 | /* bit 24:31 reserved */ | |
387 | ||
388 | #define MMU_CTL_mskD ( 0x1 << MMU_CTL_offD ) | |
389 | #define MMU_CTL_mskNTC0 ( 0x3 << MMU_CTL_offNTC0 ) | |
390 | #define MMU_CTL_mskNTC1 ( 0x3 << MMU_CTL_offNTC1 ) | |
391 | #define MMU_CTL_mskNTC2 ( 0x3 << MMU_CTL_offNTC2 ) | |
392 | #define MMU_CTL_mskNTC3 ( 0x3 << MMU_CTL_offNTC3 ) | |
393 | #define MMU_CTL_mskTBALCK ( 0x1 << MMU_CTL_offTBALCK ) | |
394 | #define MMU_CTL_mskMPZIU ( 0x1 << MMU_CTL_offMPZIU ) | |
395 | #define MMU_CTL_mskNTM0 ( 0x3 << MMU_CTL_offNTM0 ) | |
396 | #define MMU_CTL_mskNTM1 ( 0x3 << MMU_CTL_offNTM1 ) | |
397 | #define MMU_CTL_mskNTM2 ( 0x3 << MMU_CTL_offNTM2 ) | |
398 | #define MMU_CTL_mskNTM3 ( 0x3 << MMU_CTL_offNTM3 ) | |
399 | ||
400 | #define MMU_CTL_D4KB 0 | |
401 | #define MMU_CTL_D8KB 1 | |
402 | #define MMU_CTL_UNA ( 0x1 << MMU_CTL_offUNA ) | |
403 | ||
abb90a24 | 404 | #define MMU_CTL_CACHEABLE_NON 0 |
e1d82de6 GH |
405 | #define MMU_CTL_CACHEABLE_WB 2 |
406 | #define MMU_CTL_CACHEABLE_WT 3 | |
407 | ||
408 | /****************************************************************************** | |
409 | * mr1: L1_PPTB (L1 Physical Page Table Base Register) | |
410 | *****************************************************************************/ | |
411 | #define L1_PPTB_offNV 0 /* Enable Hardware Page Table Walker (HPTWK) */ | |
412 | /* bit 1:11 reserved */ | |
413 | #define L1_PPTB_offBASE 12 /* First level physical page table base address */ | |
414 | ||
415 | #define L1_PPTB_mskNV ( 0x1 << L1_PPTB_offNV ) | |
416 | #define L1_PPTB_mskBASE ( 0xFFFFF << L1_PPTB_offBASE ) | |
417 | ||
418 | /****************************************************************************** | |
419 | * mr2: TLB_VPN (TLB Access VPN Register) | |
420 | *****************************************************************************/ | |
421 | /* bit 0:11 reserved */ | |
422 | #define TLB_VPN_offVPN 12 /* Virtual Page Number */ | |
423 | ||
424 | #define TLB_VPN_mskVPN ( 0xFFFFF << TLB_VPN_offVPN ) | |
425 | ||
426 | /****************************************************************************** | |
427 | * mr3: TLB_DATA (TLB Access Data Register) | |
428 | *****************************************************************************/ | |
429 | #define TLB_DATA_offV 0 /* PTE is valid and present */ | |
430 | #define TLB_DATA_offM 1 /* Page read/write access privilege */ | |
431 | #define TLB_DATA_offD 4 /* Dirty bit */ | |
432 | #define TLB_DATA_offX 5 /* Executable bit */ | |
433 | #define TLB_DATA_offA 6 /* Access bit */ | |
434 | #define TLB_DATA_offG 7 /* Global page (shared across contexts) */ | |
435 | #define TLB_DATA_offC 8 /* Cacheability atribute */ | |
436 | /* bit 11:11 reserved */ | |
437 | #define TLB_DATA_offPPN 12 /* Phisical Page Number */ | |
438 | ||
439 | #define TLB_DATA_mskV ( 0x1 << TLB_DATA_offV ) | |
440 | #define TLB_DATA_mskM ( 0x7 << TLB_DATA_offM ) | |
441 | #define TLB_DATA_mskD ( 0x1 << TLB_DATA_offD ) | |
442 | #define TLB_DATA_mskX ( 0x1 << TLB_DATA_offX ) | |
443 | #define TLB_DATA_mskA ( 0x1 << TLB_DATA_offA ) | |
444 | #define TLB_DATA_mskG ( 0x1 << TLB_DATA_offG ) | |
445 | #define TLB_DATA_mskC ( 0x7 << TLB_DATA_offC ) | |
446 | #define TLB_DATA_mskPPN ( 0xFFFFF << TLB_DATA_offPPN ) | |
447 | ||
448 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
449 | #define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|TLB_DATA_mskC) | |
450 | #else | |
451 | #define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|(0x6 << TLB_DATA_offC)) | |
452 | #endif | |
453 | ||
454 | /****************************************************************************** | |
455 | * mr4: TLB_MISC (TLB Access Misc Register) | |
456 | *****************************************************************************/ | |
457 | #define TLB_MISC_offACC_PSZ 0 /* Page size of a PTE entry */ | |
458 | #define TLB_MISC_offCID 4 /* Context id */ | |
459 | /* bit 13:31 reserved */ | |
460 | ||
461 | #define TLB_MISC_mskACC_PSZ ( 0xF << TLB_MISC_offACC_PSZ ) | |
462 | #define TLB_MISC_mskCID ( 0x1FF << TLB_MISC_offCID ) | |
463 | ||
464 | /****************************************************************************** | |
465 | * mr5: VLPT_IDX (Virtual Linear Page Table Index Register) | |
466 | *****************************************************************************/ | |
467 | #define VLPT_IDX_offZERO 0 /* Always 0 */ | |
468 | #define VLPT_IDX_offEVPN 2 /* Exception Virtual Page Number */ | |
469 | #define VLPT_IDX_offVLPTB 22 /* Base VA of VLPT */ | |
470 | ||
471 | #define VLPT_IDX_mskZERO ( 0x3 << VLPT_IDX_offZERO ) | |
472 | #define VLPT_IDX_mskEVPN ( 0xFFFFF << VLPT_IDX_offEVPN ) | |
473 | #define VLPT_IDX_mskVLPTB ( 0x3FF << VLPT_IDX_offVLPTB ) | |
474 | ||
475 | /****************************************************************************** | |
476 | * mr6: ILMB (Instruction Local Memory Base Register) | |
477 | *****************************************************************************/ | |
478 | #define ILMB_offIEN 0 /* Enable ILM */ | |
479 | #define ILMB_offILMSZ 1 /* Size of ILM */ | |
480 | /* bit 5:19 reserved */ | |
481 | #define ILMB_offIBPA 20 /* Base PA of ILM */ | |
482 | ||
483 | #define ILMB_mskIEN ( 0x1 << ILMB_offIEN ) | |
484 | #define ILMB_mskILMSZ ( 0xF << ILMB_offILMSZ ) | |
485 | #define ILMB_mskIBPA ( 0xFFF << ILMB_offIBPA ) | |
486 | ||
487 | /****************************************************************************** | |
488 | * mr7: DLMB (Data Local Memory Base Register) | |
489 | *****************************************************************************/ | |
490 | #define DLMB_offDEN 0 /* Enable DLM */ | |
491 | #define DLMB_offDLMSZ 1 /* Size of DLM */ | |
492 | #define DLMB_offDBM 5 /* Enable Double-Buffer Mode for DLM */ | |
493 | #define DLMB_offDBB 6 /* Double-buffer bank which can be accessed by the processor */ | |
494 | /* bit 7:19 reserved */ | |
495 | #define DLMB_offDBPA 20 /* Base PA of DLM */ | |
496 | ||
497 | #define DLMB_mskDEN ( 0x1 << DLMB_offDEN ) | |
498 | #define DLMB_mskDLMSZ ( 0xF << DLMB_offDLMSZ ) | |
499 | #define DLMB_mskDBM ( 0x1 << DLMB_offDBM ) | |
500 | #define DLMB_mskDBB ( 0x1 << DLMB_offDBB ) | |
501 | #define DLMB_mskDBPA ( 0xFFF << DLMB_offDBPA ) | |
502 | ||
503 | /****************************************************************************** | |
504 | * mr8: CACHE_CTL (Cache Control Register) | |
505 | *****************************************************************************/ | |
506 | #define CACHE_CTL_offIC_EN 0 /* Enable I-cache */ | |
507 | #define CACHE_CTL_offDC_EN 1 /* Enable D-cache */ | |
508 | #define CACHE_CTL_offICALCK 2 /* I-cache all-lock resolution scheme */ | |
509 | #define CACHE_CTL_offDCALCK 3 /* D-cache all-lock resolution scheme */ | |
510 | #define CACHE_CTL_offDCCWF 4 /* Enable D-cache Critical Word Forwarding */ | |
511 | #define CACHE_CTL_offDCPMW 5 /* Enable D-cache concurrent miss and write-back processing */ | |
512 | /* bit 6:31 reserved */ | |
513 | ||
514 | #define CACHE_CTL_mskIC_EN ( 0x1 << CACHE_CTL_offIC_EN ) | |
515 | #define CACHE_CTL_mskDC_EN ( 0x1 << CACHE_CTL_offDC_EN ) | |
516 | #define CACHE_CTL_mskICALCK ( 0x1 << CACHE_CTL_offICALCK ) | |
517 | #define CACHE_CTL_mskDCALCK ( 0x1 << CACHE_CTL_offDCALCK ) | |
518 | #define CACHE_CTL_mskDCCWF ( 0x1 << CACHE_CTL_offDCCWF ) | |
519 | #define CACHE_CTL_mskDCPMW ( 0x1 << CACHE_CTL_offDCPMW ) | |
520 | ||
521 | /****************************************************************************** | |
522 | * mr9: HSMP_SADDR (High Speed Memory Port Starting Address) | |
523 | *****************************************************************************/ | |
524 | #define HSMP_SADDR_offEN 0 /* Enable control bit for the High Speed Memory port */ | |
525 | /* bit 1:19 reserved */ | |
526 | ||
527 | #define HSMP_SADDR_offRANGE 1 /* Denote the address range (only defined in HSMP v2 ) */ | |
528 | #define HSMP_SADDR_offSADDR 20 /* Starting base PA of the High Speed Memory Port region */ | |
529 | ||
530 | #define HSMP_SADDR_mskEN ( 0x1 << HSMP_SADDR_offEN ) | |
531 | #define HSMP_SADDR_mskRANGE ( 0xFFF << HSMP_SADDR_offRANGE ) | |
532 | #define HSMP_SADDR_mskSADDR ( 0xFFF << HSMP_SADDR_offSADDR ) | |
533 | ||
534 | /****************************************************************************** | |
535 | * mr10: HSMP_EADDR (High Speed Memory Port Ending Address) | |
536 | *****************************************************************************/ | |
537 | /* bit 0:19 reserved */ | |
538 | #define HSMP_EADDR_offEADDR 20 | |
539 | ||
540 | #define HSMP_EADDR_mskEADDR ( 0xFFF << HSMP_EADDR_offEADDR ) | |
541 | ||
542 | /****************************************************************************** | |
543 | * dr0+(n*5): BPCn (n=0-7) (Breakpoint Control Register) | |
544 | *****************************************************************************/ | |
545 | #define BPC_offWP 0 /* Configuration of BPAn */ | |
546 | #define BPC_offEL 1 /* Enable BPAn */ | |
547 | #define BPC_offS 2 /* Data address comparison for a store instruction */ | |
548 | #define BPC_offP 3 /* Compared data address is PA */ | |
549 | #define BPC_offC 4 /* CID value is compared with the BPCIDn register */ | |
550 | #define BPC_offBE0 5 /* Enable byte mask for the comparison with register */ | |
551 | #define BPC_offBE1 6 /* Enable byte mask for the comparison with register */ | |
552 | #define BPC_offBE2 7 /* Enable byte mask for the comparison with register */ | |
553 | #define BPC_offBE3 8 /* Enable byte mask for the comparison with register */ | |
554 | #define BPC_offT 9 /* Enable breakpoint Embedded Tracer triggering operation */ | |
555 | ||
556 | #define BPC_mskWP ( 0x1 << BPC_offWP ) | |
557 | #define BPC_mskEL ( 0x1 << BPC_offEL ) | |
558 | #define BPC_mskS ( 0x1 << BPC_offS ) | |
559 | #define BPC_mskP ( 0x1 << BPC_offP ) | |
560 | #define BPC_mskC ( 0x1 << BPC_offC ) | |
561 | #define BPC_mskBE0 ( 0x1 << BPC_offBE0 ) | |
562 | #define BPC_mskBE1 ( 0x1 << BPC_offBE1 ) | |
563 | #define BPC_mskBE2 ( 0x1 << BPC_offBE2 ) | |
564 | #define BPC_mskBE3 ( 0x1 << BPC_offBE3 ) | |
565 | #define BPC_mskT ( 0x1 << BPC_offT ) | |
566 | ||
567 | /****************************************************************************** | |
568 | * dr1+(n*5): BPAn (n=0-7) (Breakpoint Address Register) | |
569 | *****************************************************************************/ | |
570 | ||
571 | /* These registers contain break point address */ | |
572 | ||
573 | /****************************************************************************** | |
574 | * dr2+(n*5): BPAMn (n=0-7) (Breakpoint Address Mask Register) | |
575 | *****************************************************************************/ | |
576 | ||
577 | /* These registerd contain the address comparison mask for the BPAn register */ | |
578 | ||
579 | /****************************************************************************** | |
580 | * dr3+(n*5): BPVn (n=0-7) Breakpoint Data Value Register | |
581 | *****************************************************************************/ | |
582 | ||
583 | /* The BPVn register contains the data value that will be compared with the | |
584 | * incoming load/store data value */ | |
585 | ||
586 | /****************************************************************************** | |
587 | * dr4+(n*5): BPCIDn (n=0-7) (Breakpoint Context ID Register) | |
588 | *****************************************************************************/ | |
589 | #define BPCID_offCID 0 /* CID that will be compared with a process's CID */ | |
590 | /* bit 9:31 reserved */ | |
591 | ||
592 | #define BPCID_mskCID ( 0x1FF << BPCID_offCID ) | |
593 | ||
594 | /****************************************************************************** | |
595 | * dr40: EDM_CFG (EDM Configuration Register) | |
596 | *****************************************************************************/ | |
597 | #define EDM_CFG_offBC 0 /* Number of hardware breakpoint sets implemented */ | |
598 | #define EDM_CFG_offDIMU 3 /* Debug Instruction Memory Unit exists */ | |
599 | /* bit 4:15 reserved */ | |
600 | #define EDM_CFG_offVER 16 /* EDM version */ | |
601 | ||
602 | #define EDM_CFG_mskBC ( 0x7 << EDM_CFG_offBC ) | |
603 | #define EDM_CFG_mskDIMU ( 0x1 << EDM_CFG_offDIMU ) | |
604 | #define EDM_CFG_mskVER ( 0xFFFF << EDM_CFG_offVER ) | |
605 | ||
606 | /****************************************************************************** | |
607 | * dr41: EDMSW (EDM Status Word) | |
608 | *****************************************************************************/ | |
609 | #define EDMSW_offWV 0 /* Write Valid */ | |
610 | #define EDMSW_offRV 1 /* Read Valid */ | |
611 | #define EDMSW_offDE 2 /* Debug exception has occurred for this core */ | |
612 | /* bit 3:31 reserved */ | |
613 | ||
614 | #define EDMSW_mskWV ( 0x1 << EDMSW_offWV ) | |
615 | #define EDMSW_mskRV ( 0x1 << EDMSW_offRV ) | |
616 | #define EDMSW_mskDE ( 0x1 << EDMSW_offDE ) | |
617 | ||
618 | /****************************************************************************** | |
619 | * dr42: EDM_CTL (EDM Control Register) | |
620 | *****************************************************************************/ | |
621 | /* bit 0:30 reserved */ | |
622 | #define EDM_CTL_offV3_EDM_MODE 6 /* EDM compatibility control bit */ | |
623 | #define EDM_CTL_offDEH_SEL 31 /* Controls where debug exception is directed to */ | |
624 | ||
625 | #define EDM_CTL_mskV3_EDM_MODE ( 0x1 << EDM_CTL_offV3_EDM_MODE ) | |
626 | #define EDM_CTL_mskDEH_SEL ( 0x1 << EDM_CTL_offDEH_SEL ) | |
627 | ||
628 | /****************************************************************************** | |
629 | * dr43: EDM_DTR (EDM Data Transfer Register) | |
630 | *****************************************************************************/ | |
631 | ||
632 | /* This is used to exchange data between the embedded EDM logic | |
633 | * and the processor core */ | |
634 | ||
635 | /****************************************************************************** | |
636 | * dr44: BPMTC (Breakpoint Match Trigger Counter Register) | |
637 | *****************************************************************************/ | |
638 | #define BPMTC_offBPMTC 0 /* Breakpoint match trigger counter value */ | |
639 | /* bit 16:31 reserved */ | |
640 | ||
641 | #define BPMTC_mskBPMTC ( 0xFFFF << BPMTC_offBPMTC ) | |
642 | ||
643 | /****************************************************************************** | |
644 | * dr45: DIMBR (Debug Instruction Memory Base Register) | |
645 | *****************************************************************************/ | |
646 | /* bit 0:11 reserved */ | |
647 | #define DIMBR_offDIMB 12 /* Base address of the Debug Instruction Memory (DIM) */ | |
648 | #define DIMBR_mskDIMB ( 0xFFFFF << DIMBR_offDIMB ) | |
649 | ||
650 | /****************************************************************************** | |
651 | * dr46: TECR0(Trigger Event Control register 0) | |
652 | * dr47: TECR1 (Trigger Event Control register 1) | |
653 | *****************************************************************************/ | |
654 | #define TECR_offBP 0 /* Controld which BP is used as a trigger source */ | |
655 | #define TECR_offNMI 8 /* Use NMI as a trigger source */ | |
656 | #define TECR_offHWINT 9 /* Corresponding interrupt is used as a trigger source */ | |
657 | #define TECR_offEVIC 15 /* Enable HWINT as a trigger source in EVIC mode */ | |
658 | #define TECR_offSYS 16 /* Enable SYSCALL instruction as a trigger source */ | |
659 | #define TECR_offDBG 17 /* Enable debug exception as a trigger source */ | |
660 | #define TECR_offMRE 18 /* Enable MMU related exception as a trigger source */ | |
661 | #define TECR_offE 19 /* An exception is used as a trigger source */ | |
662 | /* bit 20:30 reserved */ | |
663 | #define TECR_offL 31 /* Link/Cascade TECR0 trigger event to TECR1 trigger event */ | |
664 | ||
665 | #define TECR_mskBP ( 0xFF << TECR_offBP ) | |
666 | #define TECR_mskNMI ( 0x1 << TECR_offBNMI ) | |
667 | #define TECR_mskHWINT ( 0x3F << TECR_offBHWINT ) | |
668 | #define TECR_mskEVIC ( 0x1 << TECR_offBEVIC ) | |
669 | #define TECR_mskSYS ( 0x1 << TECR_offBSYS ) | |
670 | #define TECR_mskDBG ( 0x1 << TECR_offBDBG ) | |
671 | #define TECR_mskMRE ( 0x1 << TECR_offBMRE ) | |
672 | #define TECR_mskE ( 0x1 << TECR_offE ) | |
673 | #define TECR_mskL ( 0x1 << TECR_offL ) | |
674 | ||
675 | /****************************************************************************** | |
676 | * pfr0-2: PFMC0-2 (Performance Counter Register 0-2) | |
677 | *****************************************************************************/ | |
678 | ||
679 | /* These registers contains performance event count */ | |
680 | ||
681 | /****************************************************************************** | |
682 | * pfr3: PFM_CTL (Performance Counter Control Register) | |
683 | *****************************************************************************/ | |
684 | #define PFM_CTL_offEN0 0 /* Enable PFMC0 */ | |
685 | #define PFM_CTL_offEN1 1 /* Enable PFMC1 */ | |
686 | #define PFM_CTL_offEN2 2 /* Enable PFMC2 */ | |
687 | #define PFM_CTL_offIE0 3 /* Enable interrupt for PFMC0 */ | |
688 | #define PFM_CTL_offIE1 4 /* Enable interrupt for PFMC1 */ | |
689 | #define PFM_CTL_offIE2 5 /* Enable interrupt for PFMC2 */ | |
690 | #define PFM_CTL_offOVF0 6 /* Overflow bit of PFMC0 */ | |
691 | #define PFM_CTL_offOVF1 7 /* Overflow bit of PFMC1 */ | |
692 | #define PFM_CTL_offOVF2 8 /* Overflow bit of PFMC2 */ | |
693 | #define PFM_CTL_offKS0 9 /* Enable superuser mode event counting for PFMC0 */ | |
694 | #define PFM_CTL_offKS1 10 /* Enable superuser mode event counting for PFMC1 */ | |
695 | #define PFM_CTL_offKS2 11 /* Enable superuser mode event counting for PFMC2 */ | |
696 | #define PFM_CTL_offKU0 12 /* Enable user mode event counting for PFMC0 */ | |
697 | #define PFM_CTL_offKU1 13 /* Enable user mode event counting for PFMC1 */ | |
698 | #define PFM_CTL_offKU2 14 /* Enable user mode event counting for PFMC2 */ | |
699 | #define PFM_CTL_offSEL0 15 /* The event selection for PFMC0 */ | |
9aaafac8 N |
700 | #define PFM_CTL_offSEL1 16 /* The event selection for PFMC1 */ |
701 | #define PFM_CTL_offSEL2 22 /* The event selection for PFMC2 */ | |
e1d82de6 GH |
702 | /* bit 28:31 reserved */ |
703 | ||
704 | #define PFM_CTL_mskEN0 ( 0x01 << PFM_CTL_offEN0 ) | |
705 | #define PFM_CTL_mskEN1 ( 0x01 << PFM_CTL_offEN1 ) | |
706 | #define PFM_CTL_mskEN2 ( 0x01 << PFM_CTL_offEN2 ) | |
707 | #define PFM_CTL_mskIE0 ( 0x01 << PFM_CTL_offIE0 ) | |
708 | #define PFM_CTL_mskIE1 ( 0x01 << PFM_CTL_offIE1 ) | |
709 | #define PFM_CTL_mskIE2 ( 0x01 << PFM_CTL_offIE2 ) | |
710 | #define PFM_CTL_mskOVF0 ( 0x01 << PFM_CTL_offOVF0 ) | |
711 | #define PFM_CTL_mskOVF1 ( 0x01 << PFM_CTL_offOVF1 ) | |
712 | #define PFM_CTL_mskOVF2 ( 0x01 << PFM_CTL_offOVF2 ) | |
713 | #define PFM_CTL_mskKS0 ( 0x01 << PFM_CTL_offKS0 ) | |
714 | #define PFM_CTL_mskKS1 ( 0x01 << PFM_CTL_offKS1 ) | |
715 | #define PFM_CTL_mskKS2 ( 0x01 << PFM_CTL_offKS2 ) | |
716 | #define PFM_CTL_mskKU0 ( 0x01 << PFM_CTL_offKU0 ) | |
717 | #define PFM_CTL_mskKU1 ( 0x01 << PFM_CTL_offKU1 ) | |
718 | #define PFM_CTL_mskKU2 ( 0x01 << PFM_CTL_offKU2 ) | |
719 | #define PFM_CTL_mskSEL0 ( 0x01 << PFM_CTL_offSEL0 ) | |
720 | #define PFM_CTL_mskSEL1 ( 0x3F << PFM_CTL_offSEL1 ) | |
721 | #define PFM_CTL_mskSEL2 ( 0x3F << PFM_CTL_offSEL2 ) | |
722 | ||
723 | /****************************************************************************** | |
724 | * SDZ_CTL (Structure Downsizing Control Register) | |
725 | *****************************************************************************/ | |
726 | #define SDZ_CTL_offICDZ 0 /* I-cache downsizing control */ | |
727 | #define SDZ_CTL_offDCDZ 3 /* D-cache downsizing control */ | |
728 | #define SDZ_CTL_offMTBDZ 6 /* MTLB downsizing control */ | |
729 | #define SDZ_CTL_offBTBDZ 9 /* Branch Target Table downsizing control */ | |
730 | /* bit 12:31 reserved */ | |
731 | #define SDZ_CTL_mskICDZ ( 0x07 << SDZ_CTL_offICDZ ) | |
732 | #define SDZ_CTL_mskDCDZ ( 0x07 << SDZ_CTL_offDCDZ ) | |
733 | #define SDZ_CTL_mskMTBDZ ( 0x07 << SDZ_CTL_offMTBDZ ) | |
734 | #define SDZ_CTL_mskBTBDZ ( 0x07 << SDZ_CTL_offBTBDZ ) | |
735 | ||
736 | /****************************************************************************** | |
737 | * N13MISC_CTL (N13 Miscellaneous Control Register) | |
738 | *****************************************************************************/ | |
739 | #define N13MISC_CTL_offBTB 0 /* Disable Branch Target Buffer */ | |
740 | #define N13MISC_CTL_offRTP 1 /* Disable Return Target Predictor */ | |
741 | #define N13MISC_CTL_offPTEPF 2 /* Disable HPTWK L2 PTE pefetch */ | |
742 | #define N13MISC_CTL_offSP_SHADOW_EN 4 /* Enable shadow stack pointers */ | |
e2f3f8b4 | 743 | #define MISC_CTL_offHWPRE 11 /* Enable HardWare PREFETCH */ |
e1d82de6 GH |
744 | /* bit 6, 9:31 reserved */ |
745 | ||
746 | #define N13MISC_CTL_makBTB ( 0x1 << N13MISC_CTL_offBTB ) | |
747 | #define N13MISC_CTL_makRTP ( 0x1 << N13MISC_CTL_offRTP ) | |
748 | #define N13MISC_CTL_makPTEPF ( 0x1 << N13MISC_CTL_offPTEPF ) | |
749 | #define N13MISC_CTL_makSP_SHADOW_EN ( 0x1 << N13MISC_CTL_offSP_SHADOW_EN ) | |
e2f3f8b4 | 750 | #define MISC_CTL_makHWPRE_EN ( 0x1 << MISC_CTL_offHWPRE ) |
e1d82de6 | 751 | |
e2f3f8b4 NC |
752 | #ifdef CONFIG_HW_PRE |
753 | #define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN|MISC_CTL_makHWPRE_EN) | |
754 | #else | |
e1d82de6 | 755 | #define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN) |
e2f3f8b4 | 756 | #endif |
e1d82de6 GH |
757 | |
758 | /****************************************************************************** | |
759 | * PRUSR_ACC_CTL (Privileged Resource User Access Control Registers) | |
760 | *****************************************************************************/ | |
761 | #define PRUSR_ACC_CTL_offDMA_EN 0 /* Allow user mode access of DMA registers */ | |
762 | #define PRUSR_ACC_CTL_offPFM_EN 1 /* Allow user mode access of PFM registers */ | |
763 | ||
764 | #define PRUSR_ACC_CTL_mskDMA_EN ( 0x1 << PRUSR_ACC_CTL_offDMA_EN ) | |
765 | #define PRUSR_ACC_CTL_mskPFM_EN ( 0x1 << PRUSR_ACC_CTL_offPFM_EN ) | |
766 | ||
767 | /****************************************************************************** | |
768 | * dmar0: DMA_CFG (DMA Configuration Register) | |
769 | *****************************************************************************/ | |
770 | #define DMA_CFG_offNCHN 0 /* The number of DMA channels implemented */ | |
771 | #define DMA_CFG_offUNEA 2 /* Un-aligned External Address transfer feature */ | |
772 | #define DMA_CFG_off2DET 3 /* 2-D Element Transfer feature */ | |
773 | /* bit 4:15 reserved */ | |
774 | #define DMA_CFG_offVER 16 /* DMA architecture and implementation version */ | |
775 | ||
776 | #define DMA_CFG_mskNCHN ( 0x3 << DMA_CFG_offNCHN ) | |
777 | #define DMA_CFG_mskUNEA ( 0x1 << DMA_CFG_offUNEA ) | |
778 | #define DMA_CFG_msk2DET ( 0x1 << DMA_CFG_off2DET ) | |
779 | #define DMA_CFG_mskVER ( 0xFFFF << DMA_CFG_offVER ) | |
780 | ||
781 | /****************************************************************************** | |
782 | * dmar1: DMA_GCSW (DMA Global Control and Status Word Register) | |
783 | *****************************************************************************/ | |
784 | #define DMA_GCSW_offC0STAT 0 /* DMA channel 0 state */ | |
785 | #define DMA_GCSW_offC1STAT 3 /* DMA channel 1 state */ | |
786 | /* bit 6:11 reserved */ | |
787 | #define DMA_GCSW_offC0INT 12 /* DMA channel 0 generate interrupt */ | |
788 | #define DMA_GCSW_offC1INT 13 /* DMA channel 1 generate interrupt */ | |
789 | /* bit 14:30 reserved */ | |
790 | #define DMA_GCSW_offEN 31 /* Enable DMA engine */ | |
791 | ||
792 | #define DMA_GCSW_mskC0STAT ( 0x7 << DMA_GCSW_offC0STAT ) | |
793 | #define DMA_GCSW_mskC1STAT ( 0x7 << DMA_GCSW_offC1STAT ) | |
794 | #define DMA_GCSW_mskC0INT ( 0x1 << DMA_GCSW_offC0INT ) | |
795 | #define DMA_GCSW_mskC1INT ( 0x1 << DMA_GCSW_offC1INT ) | |
796 | #define DMA_GCSW_mskEN ( 0x1 << DMA_GCSW_offEN ) | |
797 | ||
798 | /****************************************************************************** | |
799 | * dmar2: DMA_CHNSEL (DMA Channel Selection Register) | |
800 | *****************************************************************************/ | |
801 | #define DMA_CHNSEL_offCHAN 0 /* Selected channel number */ | |
802 | /* bit 2:31 reserved */ | |
803 | ||
804 | #define DMA_CHNSEL_mskCHAN ( 0x3 << DMA_CHNSEL_offCHAN ) | |
805 | ||
806 | /****************************************************************************** | |
807 | * dmar3: DMA_ACT (DMA Action Register) | |
808 | *****************************************************************************/ | |
809 | #define DMA_ACT_offACMD 0 /* DMA Action Command */ | |
810 | /* bit 2:31 reserved */ | |
811 | #define DMA_ACT_mskACMD ( 0x3 << DMA_ACT_offACMD ) | |
812 | ||
813 | /****************************************************************************** | |
814 | * dmar4: DMA_SETUP (DMA Setup Register) | |
815 | *****************************************************************************/ | |
816 | #define DMA_SETUP_offLM 0 /* Local Memory Selection */ | |
817 | #define DMA_SETUP_offTDIR 1 /* Transfer Direction */ | |
818 | #define DMA_SETUP_offTES 2 /* Transfer Element Size */ | |
819 | #define DMA_SETUP_offESTR 4 /* External memory transfer Stride */ | |
820 | #define DMA_SETUP_offCIE 16 /* Interrupt Enable on Completion */ | |
821 | #define DMA_SETUP_offSIE 17 /* Interrupt Enable on explicit Stop */ | |
822 | #define DMA_SETUP_offEIE 18 /* Interrupt Enable on Error */ | |
823 | #define DMA_SETUP_offUE 19 /* Enable the Un-aligned External Address */ | |
824 | #define DMA_SETUP_off2DE 20 /* Enable the 2-D External Transfer */ | |
825 | #define DMA_SETUP_offCOA 21 /* Transfer Coalescable */ | |
826 | /* bit 22:31 reserved */ | |
827 | ||
828 | #define DMA_SETUP_mskLM ( 0x1 << DMA_SETUP_offLM ) | |
829 | #define DMA_SETUP_mskTDIR ( 0x1 << DMA_SETUP_offTDIR ) | |
830 | #define DMA_SETUP_mskTES ( 0x3 << DMA_SETUP_offTES ) | |
831 | #define DMA_SETUP_mskESTR ( 0xFFF << DMA_SETUP_offESTR ) | |
832 | #define DMA_SETUP_mskCIE ( 0x1 << DMA_SETUP_offCIE ) | |
833 | #define DMA_SETUP_mskSIE ( 0x1 << DMA_SETUP_offSIE ) | |
834 | #define DMA_SETUP_mskEIE ( 0x1 << DMA_SETUP_offEIE ) | |
835 | #define DMA_SETUP_mskUE ( 0x1 << DMA_SETUP_offUE ) | |
836 | #define DMA_SETUP_msk2DE ( 0x1 << DMA_SETUP_off2DE ) | |
837 | #define DMA_SETUP_mskCOA ( 0x1 << DMA_SETUP_offCOA ) | |
838 | ||
839 | /****************************************************************************** | |
840 | * dmar5: DMA_ISADDR (DMA Internal Start Address Register) | |
841 | *****************************************************************************/ | |
842 | #define DMA_ISADDR_offISADDR 0 /* Internal Start Address */ | |
843 | /* bit 20:31 reserved */ | |
844 | #define DMA_ISADDR_mskISADDR ( 0xFFFFF << DMA_ISADDR_offISADDR ) | |
845 | ||
846 | /****************************************************************************** | |
847 | * dmar6: DMA_ESADDR (DMA External Start Address Register) | |
848 | *****************************************************************************/ | |
849 | /* This register holds External Start Address */ | |
850 | ||
851 | /****************************************************************************** | |
852 | * dmar7: DMA_TCNT (DMA Transfer Element Count Register) | |
853 | *****************************************************************************/ | |
854 | #define DMA_TCNT_offTCNT 0 /* DMA transfer element count */ | |
855 | /* bit 18:31 reserved */ | |
856 | #define DMA_TCNT_mskTCNT ( 0x3FFFF << DMA_TCNT_offTCNT ) | |
857 | ||
858 | /****************************************************************************** | |
859 | * dmar8: DMA_STATUS (DMA Status Register) | |
860 | *****************************************************************************/ | |
861 | #define DMA_STATUS_offSTAT 0 /* DMA channel state */ | |
862 | #define DMA_STATUS_offSTUNA 3 /* Un-aligned error on External Stride value */ | |
863 | #define DMA_STATUS_offDERR 4 /* DMA Transfer Disruption Error */ | |
864 | #define DMA_STATUS_offEUNA 5 /* Un-aligned error on the External address */ | |
865 | #define DMA_STATUS_offIUNA 6 /* Un-aligned error on the Internal address */ | |
866 | #define DMA_STATUS_offIOOR 7 /* Out-Of-Range error on the Internal address */ | |
867 | #define DMA_STATUS_offEBUS 8 /* Bus Error on an External DMA transfer */ | |
868 | #define DMA_STATUS_offESUP 9 /* DMA setup error */ | |
869 | /* bit 10:31 reserved */ | |
870 | ||
871 | #define DMA_STATUS_mskSTAT ( 0x7 << DMA_STATUS_offSTAT ) | |
872 | #define DMA_STATUS_mskSTUNA ( 0x1 << DMDMA_STATUS_offSTUNA ) | |
873 | #define DMA_STATUS_mskDERR ( 0x1 << DMDMA_STATUS_offDERR ) | |
874 | #define DMA_STATUS_mskEUNA ( 0x1 << DMDMA_STATUS_offEUNA ) | |
875 | #define DMA_STATUS_mskIUNA ( 0x1 << DMDMA_STATUS_offIUNA ) | |
876 | #define DMA_STATUS_mskIOOR ( 0x1 << DMDMA_STATUS_offIOOR ) | |
877 | #define DMA_STATUS_mskEBUS ( 0x1 << DMDMA_STATUS_offEBUS ) | |
878 | #define DMA_STATUS_mskESUP ( 0x1 << DMDMA_STATUS_offESUP ) | |
879 | ||
880 | /****************************************************************************** | |
881 | * dmar9: DMA_2DSET (DMA 2D Setup Register) | |
882 | *****************************************************************************/ | |
883 | #define DMA_2DSET_offWECNT 0 /* The Width Element Count for a 2-D region */ | |
884 | #define DMA_2DSET_offHTSTR 16 /* The Height Stride for a 2-D region */ | |
885 | ||
886 | #define DMA_2DSET_mskHTSTR ( 0xFFFF << DMA_2DSET_offHTSTR ) | |
887 | #define DMA_2DSET_mskWECNT ( 0xFFFF << DMA_2DSET_offWECNT ) | |
888 | ||
889 | /****************************************************************************** | |
890 | * dmar10: DMA_2DSCTL (DMA 2D Startup Control Register) | |
891 | *****************************************************************************/ | |
892 | #define DMA_2DSCTL_offSTWECNT 0 /* Startup Width Element Count for a 2-D region */ | |
893 | /* bit 16:31 reserved */ | |
894 | ||
895 | #define DMA_2DSCTL_mskSTWECNT ( 0xFFFF << DMA_2DSCTL_offSTWECNT ) | |
896 | ||
897 | /****************************************************************************** | |
898 | * fpcsr: FPCSR (Floating-Point Control Status Register) | |
899 | *****************************************************************************/ | |
900 | #define FPCSR_offRM 0 | |
901 | #define FPCSR_offIVO 2 | |
902 | #define FPCSR_offDBZ 3 | |
903 | #define FPCSR_offOVF 4 | |
904 | #define FPCSR_offUDF 5 | |
905 | #define FPCSR_offIEX 6 | |
906 | #define FPCSR_offIVOE 7 | |
907 | #define FPCSR_offDBZE 8 | |
908 | #define FPCSR_offOVFE 9 | |
909 | #define FPCSR_offUDFE 10 | |
910 | #define FPCSR_offIEXE 11 | |
911 | #define FPCSR_offDNZ 12 | |
912 | #define FPCSR_offIVOT 13 | |
913 | #define FPCSR_offDBZT 14 | |
914 | #define FPCSR_offOVFT 15 | |
915 | #define FPCSR_offUDFT 16 | |
916 | #define FPCSR_offIEXT 17 | |
917 | #define FPCSR_offDNIT 18 | |
918 | #define FPCSR_offRIT 19 | |
919 | ||
920 | #define FPCSR_mskRM ( 0x3 << FPCSR_offRM ) | |
921 | #define FPCSR_mskIVO ( 0x1 << FPCSR_offIVO ) | |
922 | #define FPCSR_mskDBZ ( 0x1 << FPCSR_offDBZ ) | |
923 | #define FPCSR_mskOVF ( 0x1 << FPCSR_offOVF ) | |
924 | #define FPCSR_mskUDF ( 0x1 << FPCSR_offUDF ) | |
925 | #define FPCSR_mskIEX ( 0x1 << FPCSR_offIEX ) | |
926 | #define FPCSR_mskIVOE ( 0x1 << FPCSR_offIVOE ) | |
927 | #define FPCSR_mskDBZE ( 0x1 << FPCSR_offDBZE ) | |
928 | #define FPCSR_mskOVFE ( 0x1 << FPCSR_offOVFE ) | |
929 | #define FPCSR_mskUDFE ( 0x1 << FPCSR_offUDFE ) | |
930 | #define FPCSR_mskIEXE ( 0x1 << FPCSR_offIEXE ) | |
931 | #define FPCSR_mskDNZ ( 0x1 << FPCSR_offDNZ ) | |
932 | #define FPCSR_mskIVOT ( 0x1 << FPCSR_offIVOT ) | |
933 | #define FPCSR_mskDBZT ( 0x1 << FPCSR_offDBZT ) | |
934 | #define FPCSR_mskOVFT ( 0x1 << FPCSR_offOVFT ) | |
935 | #define FPCSR_mskUDFT ( 0x1 << FPCSR_offUDFT ) | |
936 | #define FPCSR_mskIEXT ( 0x1 << FPCSR_offIEXT ) | |
937 | #define FPCSR_mskDNIT ( 0x1 << FPCSR_offDNIT ) | |
938 | #define FPCSR_mskRIT ( 0x1 << FPCSR_offRIT ) | |
939 | #define FPCSR_mskALL (FPCSR_mskIVO | FPCSR_mskDBZ | FPCSR_mskOVF | FPCSR_mskUDF | FPCSR_mskIEX) | |
ed32949e | 940 | #define FPCSR_mskALLE_NO_UDF_IEXE (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE) |
e1d82de6 GH |
941 | #define FPCSR_mskALLE (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE | FPCSR_mskUDFE | FPCSR_mskIEXE) |
942 | #define FPCSR_mskALLT (FPCSR_mskIVOT | FPCSR_mskDBZT | FPCSR_mskOVFT | FPCSR_mskUDFT | FPCSR_mskIEXT |FPCSR_mskDNIT | FPCSR_mskRIT) | |
943 | ||
944 | /****************************************************************************** | |
945 | * fpcfg: FPCFG (Floating-Point Configuration Register) | |
946 | *****************************************************************************/ | |
947 | #define FPCFG_offSP 0 | |
948 | #define FPCFG_offDP 1 | |
949 | #define FPCFG_offFREG 2 | |
950 | #define FPCFG_offFMA 4 | |
951 | #define FPCFG_offIMVER 22 | |
952 | #define FPCFG_offAVER 27 | |
953 | ||
954 | #define FPCFG_mskSP ( 0x1 << FPCFG_offSP ) | |
955 | #define FPCFG_mskDP ( 0x1 << FPCFG_offDP ) | |
956 | #define FPCFG_mskFREG ( 0x3 << FPCFG_offFREG ) | |
957 | #define FPCFG_mskFMA ( 0x1 << FPCFG_offFMA ) | |
958 | #define FPCFG_mskIMVER ( 0x1F << FPCFG_offIMVER ) | |
959 | #define FPCFG_mskAVER ( 0x1F << FPCFG_offAVER ) | |
960 | ||
e46bf83c VC |
961 | /* 8 Single precision or 4 double precision registers are available */ |
962 | #define SP8_DP4_reg 0 | |
963 | /* 16 Single precision or 8 double precision registers are available */ | |
964 | #define SP16_DP8_reg 1 | |
965 | /* 32 Single precision or 16 double precision registers are available */ | |
966 | #define SP32_DP16_reg 2 | |
967 | /* 32 Single precision or 32 double precision registers are available */ | |
968 | #define SP32_DP32_reg 3 | |
969 | ||
e1d82de6 GH |
970 | /****************************************************************************** |
971 | * fucpr: FUCOP_CTL (FPU and Coprocessor Enable Control Register) | |
972 | *****************************************************************************/ | |
973 | #define FUCOP_CTL_offCP0EN 0 | |
974 | #define FUCOP_CTL_offCP1EN 1 | |
975 | #define FUCOP_CTL_offCP2EN 2 | |
976 | #define FUCOP_CTL_offCP3EN 3 | |
977 | #define FUCOP_CTL_offAUEN 31 | |
978 | ||
979 | #define FUCOP_CTL_mskCP0EN ( 0x1 << FUCOP_CTL_offCP0EN ) | |
980 | #define FUCOP_CTL_mskCP1EN ( 0x1 << FUCOP_CTL_offCP1EN ) | |
981 | #define FUCOP_CTL_mskCP2EN ( 0x1 << FUCOP_CTL_offCP2EN ) | |
982 | #define FUCOP_CTL_mskCP3EN ( 0x1 << FUCOP_CTL_offCP3EN ) | |
983 | #define FUCOP_CTL_mskAUEN ( 0x1 << FUCOP_CTL_offAUEN ) | |
984 | ||
985 | #endif /* __NDS32_BITFIELD_H__ */ |