[mirror_ubuntu-zesty-kernel.git] / arch / nios2 / kernel / time.c

/*
 * Copyright (C) 2013-2014 Altera Corporation
 * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
 * Copyright (C) 2004 Microtronix Datacom Ltd.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/slab.h>

#define ALTR_TIMER_COMPATIBLE		"altr,timer-1.0"

#define ALTERA_TIMER_STATUS_REG	0
#define ALTERA_TIMER_CONTROL_REG	4
#define ALTERA_TIMER_PERIODL_REG	8
#define ALTERA_TIMER_PERIODH_REG	12
#define ALTERA_TIMER_SNAPL_REG		16
#define ALTERA_TIMER_SNAPH_REG		20

#define ALTERA_TIMER_CONTROL_ITO_MSK	(0x1)
#define ALTERA_TIMER_CONTROL_CONT_MSK	(0x2)
#define ALTERA_TIMER_CONTROL_START_MSK	(0x4)
#define ALTERA_TIMER_CONTROL_STOP_MSK	(0x8)

struct nios2_timer {
	void __iomem *base;
	unsigned long freq;
};

struct nios2_clockevent_dev {
	struct nios2_timer timer;
	struct clock_event_device ced;
};

struct nios2_clocksource {
	struct nios2_timer timer;
	struct clocksource cs;
};

static inline struct nios2_clockevent_dev *
	to_nios2_clkevent(struct clock_event_device *evt)
{
	return container_of(evt, struct nios2_clockevent_dev, ced);
}

static inline struct nios2_clocksource *
	to_nios2_clksource(struct clocksource *cs)
{
	return container_of(cs, struct nios2_clocksource, cs);
}

static u16 timer_readw(struct nios2_timer *timer, u32 offs)
{
	return readw(timer->base + offs);
}

static void timer_writew(struct nios2_timer *timer, u16 val, u32 offs)
{
	writew(val, timer->base + offs);
}

static inline unsigned long read_timersnapshot(struct nios2_timer *timer)
{
	unsigned long count;

	timer_writew(timer, 0, ALTERA_TIMER_SNAPL_REG);
	count = timer_readw(timer, ALTERA_TIMER_SNAPH_REG) << 16 |
		timer_readw(timer, ALTERA_TIMER_SNAPL_REG);

	return count;
}

static cycle_t nios2_timer_read(struct clocksource *cs)
{
	struct nios2_clocksource *nios2_cs = to_nios2_clksource(cs);
	unsigned long flags;
	u32 count;

	local_irq_save(flags);
	count = read_timersnapshot(&nios2_cs->timer);
	local_irq_restore(flags);

	/* Counter is counting down */
	return ~count;
}

static struct nios2_clocksource nios2_cs = {
	.cs = {
		.name	= "nios2-clksrc",
		.rating	= 250,
		.read	= nios2_timer_read,
		.mask	= CLOCKSOURCE_MASK(32),
		.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
	},
};

cycles_t get_cycles(void)
{
	return nios2_timer_read(&nios2_cs.cs);
}
EXPORT_SYMBOL(get_cycles);

static void nios2_timer_start(struct nios2_timer *timer)
{
	u16 ctrl;

	ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
	ctrl |= ALTERA_TIMER_CONTROL_START_MSK;
	timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
}

static void nios2_timer_stop(struct nios2_timer *timer)
{
	u16 ctrl;

	ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
	ctrl |= ALTERA_TIMER_CONTROL_STOP_MSK;
	timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
}

static void nios2_timer_config(struct nios2_timer *timer, unsigned long period,
			       bool periodic)
{
	u16 ctrl;

	/* The timer's actual period is one cycle greater than the value
	 * stored in the period register. */
	 period--;

	ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
	/* stop counter */
	timer_writew(timer, ctrl | ALTERA_TIMER_CONTROL_STOP_MSK,
		ALTERA_TIMER_CONTROL_REG);

	/* write new count */
	timer_writew(timer, period, ALTERA_TIMER_PERIODL_REG);
	timer_writew(timer, period >> 16, ALTERA_TIMER_PERIODH_REG);

	ctrl |= ALTERA_TIMER_CONTROL_START_MSK | ALTERA_TIMER_CONTROL_ITO_MSK;
	if (periodic)
		ctrl |= ALTERA_TIMER_CONTROL_CONT_MSK;
	else
		ctrl &= ~ALTERA_TIMER_CONTROL_CONT_MSK;
	timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
}

static int nios2_timer_set_next_event(unsigned long delta,
	struct clock_event_device *evt)
{
	struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);

	nios2_timer_config(&nios2_ced->timer, delta, false);

	return 0;
}

static int nios2_timer_shutdown(struct clock_event_device *evt)
{
	struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
	struct nios2_timer *timer = &nios2_ced->timer;

	nios2_timer_stop(timer);
	return 0;
}

static int nios2_timer_set_periodic(struct clock_event_device *evt)
{
	unsigned long period;
	struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
	struct nios2_timer *timer = &nios2_ced->timer;

	period = DIV_ROUND_UP(timer->freq, HZ);
	nios2_timer_config(timer, period, true);
	return 0;
}

static int nios2_timer_resume(struct clock_event_device *evt)
{
	struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
	struct nios2_timer *timer = &nios2_ced->timer;

	nios2_timer_start(timer);
	return 0;
}

irqreturn_t timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *) dev_id;
	struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);

	/* Clear the interrupt condition */
	timer_writew(&nios2_ced->timer, 0, ALTERA_TIMER_STATUS_REG);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void __init nios2_timer_get_base_and_freq(struct device_node *np,
				void __iomem **base, u32 *freq)
{
	*base = of_iomap(np, 0);
	if (!*base)
		panic("Unable to map reg for %s\n", np->name);

	if (of_property_read_u32(np, "clock-frequency", freq))
		panic("Unable to get %s clock frequency\n", np->name);
}

static struct nios2_clockevent_dev nios2_ce = {
	.ced = {
		.name = "nios2-clkevent",
		.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
		.rating = 250,
		.shift = 32,
		.set_next_event = nios2_timer_set_next_event,
		.set_state_shutdown = nios2_timer_shutdown,
		.set_state_periodic = nios2_timer_set_periodic,
		.set_state_oneshot = nios2_timer_shutdown,
		.tick_resume = nios2_timer_resume,
	},
};

static __init void nios2_clockevent_init(struct device_node *timer)
{
	void __iomem *iobase;
	u32 freq;
	int irq;

	nios2_timer_get_base_and_freq(timer, &iobase, &freq);

	irq = irq_of_parse_and_map(timer, 0);
	if (!irq)
		panic("Unable to parse timer irq\n");

	nios2_ce.timer.base = iobase;
	nios2_ce.timer.freq = freq;

	nios2_ce.ced.cpumask = cpumask_of(0);
	nios2_ce.ced.irq = irq;

	nios2_timer_stop(&nios2_ce.timer);
	/* clear pending interrupt */
	timer_writew(&nios2_ce.timer, 0, ALTERA_TIMER_STATUS_REG);

	if (request_irq(irq, timer_interrupt, IRQF_TIMER, timer->name,
		&nios2_ce.ced))
		panic("Unable to setup timer irq\n");

	clockevents_config_and_register(&nios2_ce.ced, freq, 1, ULONG_MAX);
}

static __init void nios2_clocksource_init(struct device_node *timer)
{
	unsigned int ctrl;
	void __iomem *iobase;
	u32 freq;

	nios2_timer_get_base_and_freq(timer, &iobase, &freq);

	nios2_cs.timer.base = iobase;
	nios2_cs.timer.freq = freq;

	clocksource_register_hz(&nios2_cs.cs, freq);

	timer_writew(&nios2_cs.timer, USHRT_MAX, ALTERA_TIMER_PERIODL_REG);
	timer_writew(&nios2_cs.timer, USHRT_MAX, ALTERA_TIMER_PERIODH_REG);

	/* interrupt disable + continuous + start */
	ctrl = ALTERA_TIMER_CONTROL_CONT_MSK | ALTERA_TIMER_CONTROL_START_MSK;
	timer_writew(&nios2_cs.timer, ctrl, ALTERA_TIMER_CONTROL_REG);

	/* Calibrate the delay loop directly */
	lpj_fine = freq / HZ;
}

/*
 * The first timer instance will use as a clockevent. If there are two or
 * more instances, the second one gets used as clocksource and all
 * others are unused.
*/
static void __init nios2_time_init(struct device_node *timer)
{
	static int num_called;

	switch (num_called) {
	case 0:
		nios2_clockevent_init(timer);
		break;
	case 1:
		nios2_clocksource_init(timer);
		break;
	default:
		break;
	}

	num_called++;
}

void read_persistent_clock(struct timespec *ts)
{
	ts->tv_sec = mktime(2007, 1, 1, 0, 0, 0);
	ts->tv_nsec = 0;
}

void __init time_init(void)
{
	struct device_node *np;
	int count = 0;

	for_each_compatible_node(np, NULL,  ALTR_TIMER_COMPATIBLE)
		count++;

	if (count < 2)
		panic("%d timer is found, it needs 2 timers in system\n", count);

	clocksource_probe();
}

CLOCKSOURCE_OF_DECLARE(nios2_timer, ALTR_TIMER_COMPATIBLE, nios2_time_init);
Commit	Line	Data
4182de9e LFT	1	/*
	2	* Copyright (C) 2013-2014 Altera Corporation
	3	* Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
	4	* Copyright (C) 2004 Microtronix Datacom Ltd.
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
05dee9c7	11	#include <linux/export.h>
4182de9e LFT	12	#include <linux/interrupt.h>
	13	#include <linux/clockchips.h>
	14	#include <linux/clocksource.h>
	15	#include <linux/delay.h>
	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/io.h>
	20	#include <linux/slab.h>
	21
a8955cc3 LFT	22	#define ALTR_TIMER_COMPATIBLE "altr,timer-1.0"
	23
	24	#define ALTERA_TIMER_STATUS_REG 0
4182de9e LFT	25	#define ALTERA_TIMER_CONTROL_REG 4
	26	#define ALTERA_TIMER_PERIODL_REG 8
	27	#define ALTERA_TIMER_PERIODH_REG 12
	28	#define ALTERA_TIMER_SNAPL_REG 16
	29	#define ALTERA_TIMER_SNAPH_REG 20
	30
	31	#define ALTERA_TIMER_CONTROL_ITO_MSK (0x1)
	32	#define ALTERA_TIMER_CONTROL_CONT_MSK (0x2)
	33	#define ALTERA_TIMER_CONTROL_START_MSK (0x4)
	34	#define ALTERA_TIMER_CONTROL_STOP_MSK (0x8)
	35
	36	struct nios2_timer {
	37	void __iomem *base;
	38	unsigned long freq;
4182de9e LFT	39	};
	40
	41	struct nios2_clockevent_dev {
	42	struct nios2_timer timer;
	43	struct clock_event_device ced;
	44	};
	45
	46	struct nios2_clocksource {
	47	struct nios2_timer timer;
	48	struct clocksource cs;
	49	};
	50
	51	static inline struct nios2_clockevent_dev *
	52	to_nios2_clkevent(struct clock_event_device *evt)
	53	{
	54	return container_of(evt, struct nios2_clockevent_dev, ced);
	55	}
	56
	57	static inline struct nios2_clocksource *
	58	to_nios2_clksource(struct clocksource *cs)
	59	{
	60	return container_of(cs, struct nios2_clocksource, cs);
	61	}
	62
	63	static u16 timer_readw(struct nios2_timer *timer, u32 offs)
	64	{
	65	return readw(timer->base + offs);
	66	}
	67
	68	static void timer_writew(struct nios2_timer *timer, u16 val, u32 offs)
	69	{
	70	writew(val, timer->base + offs);
	71	}
	72
	73	static inline unsigned long read_timersnapshot(struct nios2_timer *timer)
	74	{
	75	unsigned long count;
	76
	77	timer_writew(timer, 0, ALTERA_TIMER_SNAPL_REG);
	78	count = timer_readw(timer, ALTERA_TIMER_SNAPH_REG) << 16 \|
	79	timer_readw(timer, ALTERA_TIMER_SNAPL_REG);
	80
	81	return count;
	82	}
	83
	84	static cycle_t nios2_timer_read(struct clocksource *cs)
	85	{
	86	struct nios2_clocksource *nios2_cs = to_nios2_clksource(cs);
	87	unsigned long flags;
	88	u32 count;
	89
	90	local_irq_save(flags);
	91	count = read_timersnapshot(&nios2_cs->timer);
	92	local_irq_restore(flags);
	93
	94	/* Counter is counting down */
	95	return ~count;
	96	}
	97
	98	static struct nios2_clocksource nios2_cs = {
	99	.cs = {
	100	.name = "nios2-clksrc",
	101	.rating = 250,
	102	.read = nios2_timer_read,
103	.mask = CLOCKSOURCE_MASK(32),
104	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
105	},
106	};
107
108	cycles_t get_cycles(void)
109	{
110	return nios2_timer_read(&nios2_cs.cs);
111	}
05dee9c7	112	EXPORT_SYMBOL(get_cycles);
4182de9e LFT	113
	114	static void nios2_timer_start(struct nios2_timer *timer)
	115	{
	116	u16 ctrl;
	117
	118	ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
	119	ctrl \|= ALTERA_TIMER_CONTROL_START_MSK;
	120	timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
	121	}
	122
	123	static void nios2_timer_stop(struct nios2_timer *timer)
	124	{
	125	u16 ctrl;
	126
	127	ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
	128	ctrl \|= ALTERA_TIMER_CONTROL_STOP_MSK;
	129	timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
	130	}
	131
	132	static void nios2_timer_config(struct nios2_timer *timer, unsigned long period,
549a14c1	133	bool periodic)
4182de9e LFT	134	{
	135	u16 ctrl;
	136
	137	/* The timer's actual period is one cycle greater than the value
	138	* stored in the period register. */
	139	period--;
	140
	141	ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
	142	/* stop counter */
	143	timer_writew(timer, ctrl \| ALTERA_TIMER_CONTROL_STOP_MSK,
	144	ALTERA_TIMER_CONTROL_REG);
	145
	146	/* write new count */
	147	timer_writew(timer, period, ALTERA_TIMER_PERIODL_REG);
	148	timer_writew(timer, period >> 16, ALTERA_TIMER_PERIODH_REG);
	149
	150	ctrl \|= ALTERA_TIMER_CONTROL_START_MSK \| ALTERA_TIMER_CONTROL_ITO_MSK;
549a14c1	151	if (periodic)
4182de9e LFT	152	ctrl \|= ALTERA_TIMER_CONTROL_CONT_MSK;
	153	else
	154	ctrl &= ~ALTERA_TIMER_CONTROL_CONT_MSK;
	155	timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
	156	}
	157
	158	static int nios2_timer_set_next_event(unsigned long delta,
	159	struct clock_event_device *evt)
	160	{
	161	struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
	162
549a14c1	163	nios2_timer_config(&nios2_ced->timer, delta, false);
4182de9e LFT	164
	165	return 0;
	166	}
	167
549a14c1 VK	168	static int nios2_timer_shutdown(struct clock_event_device *evt)
	169	{
	170	struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
	171	struct nios2_timer *timer = &nios2_ced->timer;
	172
	173	nios2_timer_stop(timer);
	174	return 0;
	175	}
	176
	177	static int nios2_timer_set_periodic(struct clock_event_device *evt)
4182de9e LFT	178	{
	179	unsigned long period;
	180	struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
	181	struct nios2_timer *timer = &nios2_ced->timer;
	182
549a14c1 VK	183	period = DIV_ROUND_UP(timer->freq, HZ);
	184	nios2_timer_config(timer, period, true);
	185	return 0;
	186	}
	187
	188	static int nios2_timer_resume(struct clock_event_device *evt)
	189	{
	190	struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
	191	struct nios2_timer *timer = &nios2_ced->timer;
	192
	193	nios2_timer_start(timer);
	194	return 0;
4182de9e LFT	195	}
	196
	197	irqreturn_t timer_interrupt(int irq, void *dev_id)
	198	{
	199	struct clock_event_device evt = (struct clock_event_device ) dev_id;
	200	struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
	201
	202	/* Clear the interrupt condition */
	203	timer_writew(&nios2_ced->timer, 0, ALTERA_TIMER_STATUS_REG);
	204	evt->event_handler(evt);
	205
	206	return IRQ_HANDLED;
	207	}
	208
	209	static void __init nios2_timer_get_base_and_freq(struct device_node *np,
	210	void __iomem *base, u32 freq)
	211	{
	212	*base = of_iomap(np, 0);
	213	if (!*base)
	214	panic("Unable to map reg for %s\n", np->name);
	215
	216	if (of_property_read_u32(np, "clock-frequency", freq))
	217	panic("Unable to get %s clock frequency\n", np->name);
	218	}
	219
	220	static struct nios2_clockevent_dev nios2_ce = {
	221	.ced = {
	222	.name = "nios2-clkevent",
	223	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	224	.rating = 250,
	225	.shift = 32,
	226	.set_next_event = nios2_timer_set_next_event,
549a14c1 VK	227	.set_state_shutdown = nios2_timer_shutdown,
	228	.set_state_periodic = nios2_timer_set_periodic,
	229	.set_state_oneshot = nios2_timer_shutdown,
	230	.tick_resume = nios2_timer_resume,
4182de9e LFT	231	},
	232	};
	233
	234	static __init void nios2_clockevent_init(struct device_node *timer)
	235	{
	236	void __iomem *iobase;
	237	u32 freq;
	238	int irq;
	239
	240	nios2_timer_get_base_and_freq(timer, &iobase, &freq);
	241
	242	irq = irq_of_parse_and_map(timer, 0);
b29438f2	243	if (!irq)
4182de9e LFT	244	panic("Unable to parse timer irq\n");
	245
	246	nios2_ce.timer.base = iobase;
4182de9e LFT	247	nios2_ce.timer.freq = freq;
	248
	249	nios2_ce.ced.cpumask = cpumask_of(0);
	250	nios2_ce.ced.irq = irq;
	251
	252	nios2_timer_stop(&nios2_ce.timer);
	253	/* clear pending interrupt */
	254	timer_writew(&nios2_ce.timer, 0, ALTERA_TIMER_STATUS_REG);
	255
	256	if (request_irq(irq, timer_interrupt, IRQF_TIMER, timer->name,
	257	&nios2_ce.ced))
	258	panic("Unable to setup timer irq\n");
	259
	260	clockevents_config_and_register(&nios2_ce.ced, freq, 1, ULONG_MAX);
	261	}
	262
	263	static __init void nios2_clocksource_init(struct device_node *timer)
	264	{
	265	unsigned int ctrl;
	266	void __iomem *iobase;
	267	u32 freq;
	268
	269	nios2_timer_get_base_and_freq(timer, &iobase, &freq);
	270
	271	nios2_cs.timer.base = iobase;
	272	nios2_cs.timer.freq = freq;
	273
	274	clocksource_register_hz(&nios2_cs.cs, freq);
	275
	276	timer_writew(&nios2_cs.timer, USHRT_MAX, ALTERA_TIMER_PERIODL_REG);
	277	timer_writew(&nios2_cs.timer, USHRT_MAX, ALTERA_TIMER_PERIODH_REG);
	278
	279	/* interrupt disable + continuous + start */
	280	ctrl = ALTERA_TIMER_CONTROL_CONT_MSK \| ALTERA_TIMER_CONTROL_START_MSK;
	281	timer_writew(&nios2_cs.timer, ctrl, ALTERA_TIMER_CONTROL_REG);
	282
	283	/* Calibrate the delay loop directly */
	284	lpj_fine = freq / HZ;
	285	}
	286
	287	/*
	288	* The first timer instance will use as a clockevent. If there are two or
	289	* more instances, the second one gets used as clocksource and all
	290	* others are unused.
	291	*/
	292	static void __init nios2_time_init(struct device_node *timer)
	293	{
	294	static int num_called;
	295
	296	switch (num_called) {
	297	case 0:
	298	nios2_clockevent_init(timer);
	299	break;
	300	case 1:
	301	nios2_clocksource_init(timer);
	302	break;
	303	default:
	304	break;
	305	}
	306
	307	num_called++;
	308	}
	309
	310	void read_persistent_clock(struct timespec *ts)
311	{
312	ts->tv_sec = mktime(2007, 1, 1, 0, 0, 0);
313	ts->tv_nsec = 0;
314	}
315
316	void __init time_init(void)
317	{
a8955cc3 LFT	318	struct device_node *np;
	319	int count = 0;
	320
	321	for_each_compatible_node(np, NULL, ALTR_TIMER_COMPATIBLE)
	322	count++;
	323
	324	if (count < 2)
	325	panic("%d timer is found, it needs 2 timers in system\n", count);
	326
3722ed23	327	clocksource_probe();
4182de9e LFT	328	}
4182de9e LFT	329
a8955cc3	330	CLOCKSOURCE_OF_DECLARE(nios2_timer, ALTR_TIMER_COMPATIBLE, nios2_time_init);