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4182de9e LFT |
1 | /* |
2 | * Copyright (C) 2013-2014 Altera Corporation | |
3 | * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch> | |
4 | * Copyright (C) 2004 Microtronix Datacom Ltd. | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
05dee9c7 | 11 | #include <linux/export.h> |
4182de9e LFT |
12 | #include <linux/interrupt.h> |
13 | #include <linux/clockchips.h> | |
14 | #include <linux/clocksource.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
18 | #include <linux/of_irq.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/slab.h> | |
21 | ||
a8955cc3 LFT |
22 | #define ALTR_TIMER_COMPATIBLE "altr,timer-1.0" |
23 | ||
24 | #define ALTERA_TIMER_STATUS_REG 0 | |
4182de9e LFT |
25 | #define ALTERA_TIMER_CONTROL_REG 4 |
26 | #define ALTERA_TIMER_PERIODL_REG 8 | |
27 | #define ALTERA_TIMER_PERIODH_REG 12 | |
28 | #define ALTERA_TIMER_SNAPL_REG 16 | |
29 | #define ALTERA_TIMER_SNAPH_REG 20 | |
30 | ||
31 | #define ALTERA_TIMER_CONTROL_ITO_MSK (0x1) | |
32 | #define ALTERA_TIMER_CONTROL_CONT_MSK (0x2) | |
33 | #define ALTERA_TIMER_CONTROL_START_MSK (0x4) | |
34 | #define ALTERA_TIMER_CONTROL_STOP_MSK (0x8) | |
35 | ||
36 | struct nios2_timer { | |
37 | void __iomem *base; | |
38 | unsigned long freq; | |
4182de9e LFT |
39 | }; |
40 | ||
41 | struct nios2_clockevent_dev { | |
42 | struct nios2_timer timer; | |
43 | struct clock_event_device ced; | |
44 | }; | |
45 | ||
46 | struct nios2_clocksource { | |
47 | struct nios2_timer timer; | |
48 | struct clocksource cs; | |
49 | }; | |
50 | ||
51 | static inline struct nios2_clockevent_dev * | |
52 | to_nios2_clkevent(struct clock_event_device *evt) | |
53 | { | |
54 | return container_of(evt, struct nios2_clockevent_dev, ced); | |
55 | } | |
56 | ||
57 | static inline struct nios2_clocksource * | |
58 | to_nios2_clksource(struct clocksource *cs) | |
59 | { | |
60 | return container_of(cs, struct nios2_clocksource, cs); | |
61 | } | |
62 | ||
63 | static u16 timer_readw(struct nios2_timer *timer, u32 offs) | |
64 | { | |
65 | return readw(timer->base + offs); | |
66 | } | |
67 | ||
68 | static void timer_writew(struct nios2_timer *timer, u16 val, u32 offs) | |
69 | { | |
70 | writew(val, timer->base + offs); | |
71 | } | |
72 | ||
73 | static inline unsigned long read_timersnapshot(struct nios2_timer *timer) | |
74 | { | |
75 | unsigned long count; | |
76 | ||
77 | timer_writew(timer, 0, ALTERA_TIMER_SNAPL_REG); | |
78 | count = timer_readw(timer, ALTERA_TIMER_SNAPH_REG) << 16 | | |
79 | timer_readw(timer, ALTERA_TIMER_SNAPL_REG); | |
80 | ||
81 | return count; | |
82 | } | |
83 | ||
84 | static cycle_t nios2_timer_read(struct clocksource *cs) | |
85 | { | |
86 | struct nios2_clocksource *nios2_cs = to_nios2_clksource(cs); | |
87 | unsigned long flags; | |
88 | u32 count; | |
89 | ||
90 | local_irq_save(flags); | |
91 | count = read_timersnapshot(&nios2_cs->timer); | |
92 | local_irq_restore(flags); | |
93 | ||
94 | /* Counter is counting down */ | |
95 | return ~count; | |
96 | } | |
97 | ||
98 | static struct nios2_clocksource nios2_cs = { | |
99 | .cs = { | |
100 | .name = "nios2-clksrc", | |
101 | .rating = 250, | |
102 | .read = nios2_timer_read, | |
103 | .mask = CLOCKSOURCE_MASK(32), | |
104 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
105 | }, | |
106 | }; | |
107 | ||
108 | cycles_t get_cycles(void) | |
109 | { | |
110 | return nios2_timer_read(&nios2_cs.cs); | |
111 | } | |
05dee9c7 | 112 | EXPORT_SYMBOL(get_cycles); |
4182de9e LFT |
113 | |
114 | static void nios2_timer_start(struct nios2_timer *timer) | |
115 | { | |
116 | u16 ctrl; | |
117 | ||
118 | ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG); | |
119 | ctrl |= ALTERA_TIMER_CONTROL_START_MSK; | |
120 | timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG); | |
121 | } | |
122 | ||
123 | static void nios2_timer_stop(struct nios2_timer *timer) | |
124 | { | |
125 | u16 ctrl; | |
126 | ||
127 | ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG); | |
128 | ctrl |= ALTERA_TIMER_CONTROL_STOP_MSK; | |
129 | timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG); | |
130 | } | |
131 | ||
132 | static void nios2_timer_config(struct nios2_timer *timer, unsigned long period, | |
133 | enum clock_event_mode mode) | |
134 | { | |
135 | u16 ctrl; | |
136 | ||
137 | /* The timer's actual period is one cycle greater than the value | |
138 | * stored in the period register. */ | |
139 | period--; | |
140 | ||
141 | ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG); | |
142 | /* stop counter */ | |
143 | timer_writew(timer, ctrl | ALTERA_TIMER_CONTROL_STOP_MSK, | |
144 | ALTERA_TIMER_CONTROL_REG); | |
145 | ||
146 | /* write new count */ | |
147 | timer_writew(timer, period, ALTERA_TIMER_PERIODL_REG); | |
148 | timer_writew(timer, period >> 16, ALTERA_TIMER_PERIODH_REG); | |
149 | ||
150 | ctrl |= ALTERA_TIMER_CONTROL_START_MSK | ALTERA_TIMER_CONTROL_ITO_MSK; | |
151 | if (mode == CLOCK_EVT_MODE_PERIODIC) | |
152 | ctrl |= ALTERA_TIMER_CONTROL_CONT_MSK; | |
153 | else | |
154 | ctrl &= ~ALTERA_TIMER_CONTROL_CONT_MSK; | |
155 | timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG); | |
156 | } | |
157 | ||
158 | static int nios2_timer_set_next_event(unsigned long delta, | |
159 | struct clock_event_device *evt) | |
160 | { | |
161 | struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt); | |
162 | ||
163 | nios2_timer_config(&nios2_ced->timer, delta, evt->mode); | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
168 | static void nios2_timer_set_mode(enum clock_event_mode mode, | |
169 | struct clock_event_device *evt) | |
170 | { | |
171 | unsigned long period; | |
172 | struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt); | |
173 | struct nios2_timer *timer = &nios2_ced->timer; | |
174 | ||
175 | switch (mode) { | |
176 | case CLOCK_EVT_MODE_PERIODIC: | |
177 | period = DIV_ROUND_UP(timer->freq, HZ); | |
178 | nios2_timer_config(timer, period, CLOCK_EVT_MODE_PERIODIC); | |
179 | break; | |
180 | case CLOCK_EVT_MODE_ONESHOT: | |
181 | case CLOCK_EVT_MODE_UNUSED: | |
182 | case CLOCK_EVT_MODE_SHUTDOWN: | |
183 | nios2_timer_stop(timer); | |
184 | break; | |
185 | case CLOCK_EVT_MODE_RESUME: | |
186 | nios2_timer_start(timer); | |
187 | break; | |
188 | } | |
189 | } | |
190 | ||
191 | irqreturn_t timer_interrupt(int irq, void *dev_id) | |
192 | { | |
193 | struct clock_event_device *evt = (struct clock_event_device *) dev_id; | |
194 | struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt); | |
195 | ||
196 | /* Clear the interrupt condition */ | |
197 | timer_writew(&nios2_ced->timer, 0, ALTERA_TIMER_STATUS_REG); | |
198 | evt->event_handler(evt); | |
199 | ||
200 | return IRQ_HANDLED; | |
201 | } | |
202 | ||
203 | static void __init nios2_timer_get_base_and_freq(struct device_node *np, | |
204 | void __iomem **base, u32 *freq) | |
205 | { | |
206 | *base = of_iomap(np, 0); | |
207 | if (!*base) | |
208 | panic("Unable to map reg for %s\n", np->name); | |
209 | ||
210 | if (of_property_read_u32(np, "clock-frequency", freq)) | |
211 | panic("Unable to get %s clock frequency\n", np->name); | |
212 | } | |
213 | ||
214 | static struct nios2_clockevent_dev nios2_ce = { | |
215 | .ced = { | |
216 | .name = "nios2-clkevent", | |
217 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
218 | .rating = 250, | |
219 | .shift = 32, | |
220 | .set_next_event = nios2_timer_set_next_event, | |
221 | .set_mode = nios2_timer_set_mode, | |
222 | }, | |
223 | }; | |
224 | ||
225 | static __init void nios2_clockevent_init(struct device_node *timer) | |
226 | { | |
227 | void __iomem *iobase; | |
228 | u32 freq; | |
229 | int irq; | |
230 | ||
231 | nios2_timer_get_base_and_freq(timer, &iobase, &freq); | |
232 | ||
233 | irq = irq_of_parse_and_map(timer, 0); | |
b29438f2 | 234 | if (!irq) |
4182de9e LFT |
235 | panic("Unable to parse timer irq\n"); |
236 | ||
237 | nios2_ce.timer.base = iobase; | |
4182de9e LFT |
238 | nios2_ce.timer.freq = freq; |
239 | ||
240 | nios2_ce.ced.cpumask = cpumask_of(0); | |
241 | nios2_ce.ced.irq = irq; | |
242 | ||
243 | nios2_timer_stop(&nios2_ce.timer); | |
244 | /* clear pending interrupt */ | |
245 | timer_writew(&nios2_ce.timer, 0, ALTERA_TIMER_STATUS_REG); | |
246 | ||
247 | if (request_irq(irq, timer_interrupt, IRQF_TIMER, timer->name, | |
248 | &nios2_ce.ced)) | |
249 | panic("Unable to setup timer irq\n"); | |
250 | ||
251 | clockevents_config_and_register(&nios2_ce.ced, freq, 1, ULONG_MAX); | |
252 | } | |
253 | ||
254 | static __init void nios2_clocksource_init(struct device_node *timer) | |
255 | { | |
256 | unsigned int ctrl; | |
257 | void __iomem *iobase; | |
258 | u32 freq; | |
259 | ||
260 | nios2_timer_get_base_and_freq(timer, &iobase, &freq); | |
261 | ||
262 | nios2_cs.timer.base = iobase; | |
263 | nios2_cs.timer.freq = freq; | |
264 | ||
265 | clocksource_register_hz(&nios2_cs.cs, freq); | |
266 | ||
267 | timer_writew(&nios2_cs.timer, USHRT_MAX, ALTERA_TIMER_PERIODL_REG); | |
268 | timer_writew(&nios2_cs.timer, USHRT_MAX, ALTERA_TIMER_PERIODH_REG); | |
269 | ||
270 | /* interrupt disable + continuous + start */ | |
271 | ctrl = ALTERA_TIMER_CONTROL_CONT_MSK | ALTERA_TIMER_CONTROL_START_MSK; | |
272 | timer_writew(&nios2_cs.timer, ctrl, ALTERA_TIMER_CONTROL_REG); | |
273 | ||
274 | /* Calibrate the delay loop directly */ | |
275 | lpj_fine = freq / HZ; | |
276 | } | |
277 | ||
278 | /* | |
279 | * The first timer instance will use as a clockevent. If there are two or | |
280 | * more instances, the second one gets used as clocksource and all | |
281 | * others are unused. | |
282 | */ | |
283 | static void __init nios2_time_init(struct device_node *timer) | |
284 | { | |
285 | static int num_called; | |
286 | ||
287 | switch (num_called) { | |
288 | case 0: | |
289 | nios2_clockevent_init(timer); | |
290 | break; | |
291 | case 1: | |
292 | nios2_clocksource_init(timer); | |
293 | break; | |
294 | default: | |
295 | break; | |
296 | } | |
297 | ||
298 | num_called++; | |
299 | } | |
300 | ||
301 | void read_persistent_clock(struct timespec *ts) | |
302 | { | |
303 | ts->tv_sec = mktime(2007, 1, 1, 0, 0, 0); | |
304 | ts->tv_nsec = 0; | |
305 | } | |
306 | ||
307 | void __init time_init(void) | |
308 | { | |
a8955cc3 LFT |
309 | struct device_node *np; |
310 | int count = 0; | |
311 | ||
312 | for_each_compatible_node(np, NULL, ALTR_TIMER_COMPATIBLE) | |
313 | count++; | |
314 | ||
315 | if (count < 2) | |
316 | panic("%d timer is found, it needs 2 timers in system\n", count); | |
317 | ||
4182de9e LFT |
318 | clocksource_of_init(); |
319 | } | |
320 | ||
a8955cc3 | 321 | CLOCKSOURCE_OF_DECLARE(nios2_timer, ALTR_TIMER_COMPATIBLE, nios2_time_init); |