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f8c4a270 JB |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
395cf969 | 3 | # see Documentation/kbuild/kconfig-language.txt. |
f8c4a270 JB |
4 | # |
5 | ||
6 | config OPENRISC | |
7 | def_bool y | |
8 | select OF | |
9 | select OF_EARLY_FLATTREE | |
b4c4c6ee | 10 | select IRQ_DOMAIN |
d1f6f28f | 11 | select HANDLE_DOMAIN_IRQ |
f8c4a270 | 12 | select HAVE_MEMBLOCK |
8636f344 | 13 | select GPIOLIB |
f8c4a270 | 14 | select HAVE_ARCH_TRACEHOOK |
c0fcaf55 | 15 | select SPARSE_IRQ |
f8c4a270 JB |
16 | select GENERIC_IRQ_CHIP |
17 | select GENERIC_IRQ_PROBE | |
18 | select GENERIC_IRQ_SHOW | |
19 | select GENERIC_IOMAP | |
9f13a1fd | 20 | select GENERIC_CPU_DEVICES |
04ea1e91 | 21 | select HAVE_UID16 |
0662d33a | 22 | select GENERIC_ATOMIC64 |
5bf8f6bf | 23 | select GENERIC_CLOCKEVENTS |
8e6d08e0 | 24 | select GENERIC_CLOCKEVENTS_BROADCAST |
603d6637 | 25 | select GENERIC_STRNCPY_FROM_USER |
b48b2c3e | 26 | select GENERIC_STRNLEN_USER |
8e6d08e0 | 27 | select GENERIC_SMP_IDLE_THREAD |
786d35d4 | 28 | select MODULES_USE_ELF_RELA |
d1a1dc0b | 29 | select HAVE_DEBUG_STACKOVERFLOW |
4db8e6d2 | 30 | select OR1K_PIC |
fff7fb0b | 31 | select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 |
266c7fad | 32 | select NO_BOOTMEM |
b5f82176 SH |
33 | select ARCH_USE_QUEUED_SPINLOCKS |
34 | select ARCH_USE_QUEUED_RWLOCKS | |
9b54470a | 35 | select OMPIC if SMP |
eecac38b | 36 | select ARCH_WANT_FRAME_POINTERS |
f8c4a270 | 37 | |
4c97a0c8 BM |
38 | config CPU_BIG_ENDIAN |
39 | def_bool y | |
40 | ||
f8c4a270 JB |
41 | config MMU |
42 | def_bool y | |
43 | ||
f8c4a270 JB |
44 | config RWSEM_GENERIC_SPINLOCK |
45 | def_bool y | |
46 | ||
47 | config RWSEM_XCHGADD_ALGORITHM | |
48 | def_bool n | |
49 | ||
50 | config GENERIC_HWEIGHT | |
51 | def_bool y | |
52 | ||
ce816fa8 | 53 | config NO_IOPORT_MAP |
f8c4a270 JB |
54 | def_bool y |
55 | ||
f8c4a270 JB |
56 | config TRACE_IRQFLAGS_SUPPORT |
57 | def_bool y | |
58 | ||
59 | # For now, use generic checksum functions | |
60 | #These can be reimplemented in assembly later if so inclined | |
61 | config GENERIC_CSUM | |
62 | def_bool y | |
63 | ||
eecac38b SH |
64 | config STACKTRACE_SUPPORT |
65 | def_bool y | |
66 | ||
f8c4a270 JB |
67 | source "init/Kconfig" |
68 | ||
57a1a197 | 69 | source "kernel/Kconfig.freezer" |
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70 | |
71 | menu "Processor type and features" | |
72 | ||
73 | choice | |
74 | prompt "Subarchitecture" | |
75 | default OR1K_1200 | |
76 | ||
77 | config OR1K_1200 | |
78 | bool "OR1200" | |
79 | help | |
80 | Generic OpenRISC 1200 architecture | |
81 | ||
82 | endchoice | |
83 | ||
4ee93d80 JHW |
84 | config DCACHE_WRITETHROUGH |
85 | bool "Have write through data caches" | |
86 | default n | |
87 | help | |
88 | Select this if your implementation features write through data caches. | |
89 | Selecting 'N' here will allow the kernel to force flushing of data | |
90 | caches at relevant times. Most OpenRISC implementations support write- | |
91 | through data caches. | |
92 | ||
93 | If unsure say N here | |
94 | ||
f8c4a270 JB |
95 | config OPENRISC_BUILTIN_DTB |
96 | string "Builtin DTB" | |
97 | default "" | |
98 | ||
99 | menu "Class II Instructions" | |
100 | ||
101 | config OPENRISC_HAVE_INST_FF1 | |
102 | bool "Have instruction l.ff1" | |
103 | default y | |
104 | help | |
105 | Select this if your implementation has the Class II instruction l.ff1 | |
106 | ||
107 | config OPENRISC_HAVE_INST_FL1 | |
108 | bool "Have instruction l.fl1" | |
109 | default y | |
110 | help | |
111 | Select this if your implementation has the Class II instruction l.fl1 | |
112 | ||
113 | config OPENRISC_HAVE_INST_MUL | |
114 | bool "Have instruction l.mul for hardware multiply" | |
115 | default y | |
116 | help | |
117 | Select this if your implementation has a hardware multiply instruction | |
118 | ||
119 | config OPENRISC_HAVE_INST_DIV | |
120 | bool "Have instruction l.div for hardware divide" | |
121 | default y | |
122 | help | |
123 | Select this if your implementation has a hardware divide instruction | |
124 | endmenu | |
125 | ||
34bbdcdc | 126 | config NR_CPUS |
8e6d08e0 SK |
127 | int "Maximum number of CPUs (2-32)" |
128 | range 2 32 | |
129 | depends on SMP | |
130 | default "2" | |
131 | ||
132 | config SMP | |
133 | bool "Symmetric Multi-Processing support" | |
134 | help | |
135 | This enables support for systems with more than one CPU. If you have | |
136 | a system with only one CPU, say N. If you have a system with more | |
137 | than one CPU, say Y. | |
138 | ||
139 | If you don't know what to do here, say N. | |
f8c4a270 | 140 | |
f8c4a270 JB |
141 | source kernel/Kconfig.hz |
142 | source kernel/Kconfig.preempt | |
143 | source "mm/Kconfig" | |
144 | ||
145 | config OPENRISC_NO_SPR_SR_DSX | |
146 | bool "use SPR_SR_DSX software emulation" if OR1K_1200 | |
147 | default y | |
148 | help | |
149 | SPR_SR_DSX bit is status register bit indicating whether | |
150 | the last exception has happened in delay slot. | |
151 | ||
152 | OpenRISC architecture makes it optional to have it implemented | |
153 | in hardware and the OR1200 does not have it. | |
154 | ||
155 | Say N here if you know that your OpenRISC processor has | |
156 | SPR_SR_DSX bit implemented. Say Y if you are unsure. | |
157 | ||
91993c8c SK |
158 | config OPENRISC_HAVE_SHADOW_GPRS |
159 | bool "Support for shadow gpr files" if !SMP | |
160 | default y if SMP | |
161 | help | |
162 | Say Y here if your OpenRISC processor features shadowed | |
163 | register files. They will in such case be used as a | |
164 | scratch reg storage on exception entry. | |
165 | ||
166 | On SMP systems, this feature is mandatory. | |
167 | On a unicore system it's safe to say N here if you are unsure. | |
168 | ||
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169 | config CMDLINE |
170 | string "Default kernel command string" | |
171 | default "" | |
172 | help | |
173 | On some architectures there is currently no way for the boot loader | |
174 | to pass arguments to the kernel. For these architectures, you should | |
175 | supply some command-line options at build time by entering them | |
176 | here. | |
177 | ||
178 | menu "Debugging options" | |
179 | ||
f8c4a270 JB |
180 | config JUMP_UPON_UNHANDLED_EXCEPTION |
181 | bool "Try to die gracefully" | |
182 | default y | |
183 | help | |
184 | Now this puts kernel into infinite loop after first oops. Till | |
185 | your kernel crashes this doesn't have any influence. | |
186 | ||
187 | Say Y if you are unsure. | |
188 | ||
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189 | config OPENRISC_ESR_EXCEPTION_BUG_CHECK |
190 | bool "Check for possible ESR exception bug" | |
191 | default n | |
192 | help | |
193 | This option enables some checks that might expose some problems | |
194 | in kernel. | |
195 | ||
196 | Say N if you are unsure. | |
197 | ||
198 | endmenu | |
199 | ||
200 | endmenu | |
201 | ||
202 | menu "Executable file formats" | |
203 | ||
204 | source "fs/Kconfig.binfmt" | |
205 | ||
206 | endmenu | |
207 | ||
208 | source "net/Kconfig" | |
209 | ||
210 | source "drivers/Kconfig" | |
211 | ||
212 | source "fs/Kconfig" | |
213 | ||
214 | source "security/Kconfig" | |
215 | ||
216 | source "crypto/Kconfig" | |
217 | ||
218 | source "lib/Kconfig" | |
219 | ||
220 | menu "Kernel hacking" | |
221 | ||
222 | source "lib/Kconfig.debug" | |
223 | ||
224 | endmenu |