projects / mirror_ubuntu-focal-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 1da177e4 LT |
2 | /* |
| 3 | * include/asm-parisc/cache.h | |
| 4 | */ | |
| 5 | ||
| 6 | #ifndef __ARCH_PARISC_CACHE_H | |
| 7 | #define __ARCH_PARISC_CACHE_H | |
| 8 | ||
| 3847dab7 | 9 | #include <asm/alternative.h> |
| 1da177e4 LT |
10 | |
| 11 | /* | |
| a01fece2 JDA |
12 | * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors |
| 13 | * have 32-byte cachelines. The L1 length appears to be 16 bytes but this | |
| 14 | * is not clearly documented. | |
| 1da177e4 | 15 | */ |
| a01fece2 JDA |
16 | #define L1_CACHE_BYTES 16 |
| 17 | #define L1_CACHE_SHIFT 4 | |
| 1da177e4 LT |
18 | |
| 19 | #ifndef __ASSEMBLY__ | |
| 20 | ||
| 1da177e4 | 21 | #define SMP_CACHE_BYTES L1_CACHE_BYTES |
| 1da177e4 | 22 | |
| 7896bfa4 FT |
23 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES |
| 24 | ||
| 0703ad21 | 25 | #define __read_mostly __section(.data..read_mostly) |
| 804f1594 | 26 | |
| d6ce8626 RC |
27 | void parisc_cache_init(void); /* initializes cache-flushing */ |
| 28 | void disable_sr_hashing_asm(int); /* low level support for above */ | |
| 29 | void disable_sr_hashing(void); /* turns off space register hashing */ | |
| 30 | void free_sid(unsigned long); | |
| 1da177e4 | 31 | unsigned long alloc_sid(void); |
| 1da177e4 LT |
32 | |
| 33 | struct seq_file; | |
| 34 | extern void show_cache_info(struct seq_file *m); | |
| 35 | ||
| 36 | extern int split_tlb; | |
| 37 | extern int dcache_stride; | |
| 38 | extern int icache_stride; | |
| 39 | extern struct pdc_cache_info cache_info; | |
| d6ce8626 | 40 | void parisc_setup_cache_timing(void); |
| 1da177e4 | 41 | |
| 3847dab7 HD |
42 | #define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" \ |
| 43 | ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ | |
| 44224bdb | 44 | : : "r" (addr) : "memory") |
| 3847dab7 HD |
45 | #define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" \ |
| 46 | ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ | |
| 47 | ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \ | |
| 44224bdb | 48 | : : "r" (addr) : "memory") |
| 3847dab7 HD |
49 | #define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" \ |
| 50 | ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ | |
| 44224bdb | 51 | : : "r" (addr) : "memory") |
| 3847dab7 HD |
52 | |
| 53 | #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \ | |
| 54 | ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \ | |
| 55 | ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \ | |
| 2d94a832 | 56 | : : "r" (addr) : "memory") |
| 3847dab7 HD |
57 | #define asm_io_sync() asm volatile("sync" \ |
| 58 | ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \ | |
| 2d94a832 | 59 | ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory") |
| 1da177e4 LT |
60 | |
| 61 | #endif /* ! __ASSEMBLY__ */ | |
| 62 | ||
| 63 | /* Classes of processor wrt: disabling space register hashing */ | |
| 64 | ||
| 65 | #define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */ | |
| 66 | #define SRHASH_PCXL 1 /* pcxl */ | |
| 67 | #define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */ | |
| 68 | ||
| 69 | #endif |