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342a0497 CD |
1 | #ifndef _ASM_PARISC_FUTEX_H |
2 | #define _ASM_PARISC_FUTEX_H | |
4732efbe | 3 | |
342a0497 | 4 | #ifdef __KERNEL__ |
4732efbe | 5 | |
342a0497 | 6 | #include <linux/futex.h> |
730f412c | 7 | #include <linux/uaccess.h> |
d9ba5fe7 | 8 | #include <asm/atomic.h> |
342a0497 | 9 | #include <asm/errno.h> |
342a0497 | 10 | |
8b232816 JDA |
11 | /* The following has to match the LWS code in syscall.S. We have |
12 | sixteen four-word locks. */ | |
13 | ||
14 | static inline void | |
15 | _futex_spin_lock_irqsave(u32 __user *uaddr, unsigned long int *flags) | |
16 | { | |
17 | extern u32 lws_lock_start[]; | |
18 | long index = ((long)uaddr & 0xf0) >> 2; | |
19 | arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index]; | |
20 | local_irq_save(*flags); | |
21 | arch_spin_lock(s); | |
22 | } | |
23 | ||
24 | static inline void | |
25 | _futex_spin_unlock_irqrestore(u32 __user *uaddr, unsigned long int *flags) | |
26 | { | |
27 | extern u32 lws_lock_start[]; | |
28 | long index = ((long)uaddr & 0xf0) >> 2; | |
29 | arch_spinlock_t *s = (arch_spinlock_t *)&lws_lock_start[index]; | |
30 | arch_spin_unlock(s); | |
31 | local_irq_restore(*flags); | |
32 | } | |
33 | ||
342a0497 | 34 | static inline int |
8d7718aa | 35 | futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) |
342a0497 | 36 | { |
d9ba5fe7 | 37 | unsigned long int flags; |
342a0497 CD |
38 | int op = (encoded_op >> 28) & 7; |
39 | int cmp = (encoded_op >> 24) & 15; | |
40 | int oparg = (encoded_op << 8) >> 20; | |
41 | int cmparg = (encoded_op << 20) >> 20; | |
99aed91a JDA |
42 | int oldval, ret; |
43 | u32 tmp; | |
44 | ||
342a0497 CD |
45 | if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) |
46 | oparg = 1 << oparg; | |
47 | ||
d9ba5fe7 | 48 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(*uaddr))) |
342a0497 CD |
49 | return -EFAULT; |
50 | ||
99aed91a | 51 | _futex_spin_lock_irqsave(uaddr, &flags); |
a866374a | 52 | pagefault_disable(); |
342a0497 | 53 | |
99aed91a JDA |
54 | ret = -EFAULT; |
55 | if (unlikely(get_user(oldval, uaddr) != 0)) | |
56 | goto out_pagefault_enable; | |
57 | ||
58 | ret = 0; | |
59 | tmp = oldval; | |
d9ba5fe7 | 60 | |
342a0497 CD |
61 | switch (op) { |
62 | case FUTEX_OP_SET: | |
99aed91a | 63 | tmp = oparg; |
d9ba5fe7 | 64 | break; |
342a0497 | 65 | case FUTEX_OP_ADD: |
99aed91a | 66 | tmp += oparg; |
d9ba5fe7 | 67 | break; |
342a0497 | 68 | case FUTEX_OP_OR: |
99aed91a | 69 | tmp |= oparg; |
d9ba5fe7 | 70 | break; |
342a0497 | 71 | case FUTEX_OP_ANDN: |
99aed91a | 72 | tmp &= ~oparg; |
d9ba5fe7 | 73 | break; |
342a0497 | 74 | case FUTEX_OP_XOR: |
99aed91a | 75 | tmp ^= oparg; |
d9ba5fe7 | 76 | break; |
342a0497 CD |
77 | default: |
78 | ret = -ENOSYS; | |
79 | } | |
80 | ||
99aed91a JDA |
81 | if (ret == 0 && unlikely(put_user(tmp, uaddr) != 0)) |
82 | ret = -EFAULT; | |
d9ba5fe7 | 83 | |
99aed91a | 84 | out_pagefault_enable: |
a866374a | 85 | pagefault_enable(); |
99aed91a | 86 | _futex_spin_unlock_irqrestore(uaddr, &flags); |
342a0497 | 87 | |
99aed91a | 88 | if (ret == 0) { |
342a0497 CD |
89 | switch (cmp) { |
90 | case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break; | |
91 | case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break; | |
92 | case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break; | |
93 | case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break; | |
94 | case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break; | |
95 | case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break; | |
96 | default: ret = -ENOSYS; | |
97 | } | |
98 | } | |
99 | return ret; | |
100 | } | |
101 | ||
342a0497 | 102 | static inline int |
8d7718aa ML |
103 | futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, |
104 | u32 oldval, u32 newval) | |
342a0497 | 105 | { |
8d7718aa | 106 | u32 val; |
d9ba5fe7 | 107 | unsigned long flags; |
342a0497 | 108 | |
c20a84c9 KM |
109 | /* futex.c wants to do a cmpxchg_inatomic on kernel NULL, which is |
110 | * our gateway page, and causes no end of trouble... | |
111 | */ | |
112 | if (segment_eq(KERNEL_DS, get_fs()) && !uaddr) | |
113 | return -EFAULT; | |
114 | ||
8d7718aa | 115 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
342a0497 CD |
116 | return -EFAULT; |
117 | ||
d9ba5fe7 CD |
118 | /* HPPA has no cmpxchg in hardware and therefore the |
119 | * best we can do here is use an array of locks. The | |
120 | * lock selected is based on a hash of the userspace | |
121 | * address. This should scale to a couple of CPUs. | |
122 | */ | |
123 | ||
8b232816 | 124 | _futex_spin_lock_irqsave(uaddr, &flags); |
99aed91a JDA |
125 | if (unlikely(get_user(val, uaddr) != 0)) { |
126 | _futex_spin_unlock_irqrestore(uaddr, &flags); | |
127 | return -EFAULT; | |
128 | } | |
d9ba5fe7 | 129 | |
99aed91a JDA |
130 | if (val == oldval && unlikely(put_user(newval, uaddr) != 0)) { |
131 | _futex_spin_unlock_irqrestore(uaddr, &flags); | |
132 | return -EFAULT; | |
133 | } | |
d9ba5fe7 | 134 | |
37a9d912 | 135 | *uval = val; |
8b232816 | 136 | _futex_spin_unlock_irqrestore(uaddr, &flags); |
d9ba5fe7 | 137 | |
99aed91a | 138 | return 0; |
342a0497 CD |
139 | } |
140 | ||
c20a84c9 KM |
141 | #endif /*__KERNEL__*/ |
142 | #endif /*_ASM_PARISC_FUTEX_H*/ |