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1da177e4 LT |
1 | /* This file is subject to the terms and conditions of the GNU General Public |
2 | * License. See the file "COPYING" in the main directory of this archive | |
3 | * for more details. | |
4 | * | |
8e9e9844 | 5 | * Copyright (C) 1999-2007 by Helge Deller <deller@gmx.de> |
1da177e4 LT |
6 | * Copyright 1999 SuSE GmbH (Philipp Rumpf) |
7 | * Copyright 1999 Philipp Rumpf (prumpf@tux.org) | |
8 | * Copyright 2000 Hewlett Packard (Paul Bame, bame@puffin.external.hp.com) | |
9 | * Copyright (C) 2001 Grant Grundler (Hewlett Packard) | |
10 | * Copyright (C) 2004 Kyle McMartin <kyle@debian.org> | |
11 | * | |
12 | * Initial Version 04-23-1999 by Helge Deller <deller@gmx.de> | |
13 | */ | |
14 | ||
0013a854 | 15 | #include <asm/asm-offsets.h> |
1da177e4 LT |
16 | #include <asm/psw.h> |
17 | #include <asm/pdc.h> | |
18 | ||
19 | #include <asm/assembly.h> | |
20 | #include <asm/pgtable.h> | |
21 | ||
8e9e9844 | 22 | #include <linux/linkage.h> |
0c634cc6 | 23 | #include <linux/init.h> |
8e9e9844 | 24 | |
1da177e4 LT |
25 | .level LEVEL |
26 | ||
0c634cc6 | 27 | __INITDATA |
8e9e9844 | 28 | ENTRY(boot_args) |
1da177e4 LT |
29 | .word 0 /* arg0 */ |
30 | .word 0 /* arg1 */ | |
31 | .word 0 /* arg2 */ | |
32 | .word 0 /* arg3 */ | |
8e9e9844 | 33 | END(boot_args) |
1da177e4 | 34 | |
1138a72c KM |
35 | __HEAD |
36 | ||
1da177e4 LT |
37 | .align 4 |
38 | .import init_thread_union,data | |
39 | .import fault_vector_20,code /* IVA parisc 2.0 32 bit */ | |
413059f2 | 40 | #ifndef CONFIG_64BIT |
1da177e4 LT |
41 | .import fault_vector_11,code /* IVA parisc 1.1 32 bit */ |
42 | .import $global$ /* forward declaration */ | |
413059f2 | 43 | #endif /*!CONFIG_64BIT*/ |
161bd3bf | 44 | ENTRY(parisc_kernel_start) |
1da177e4 LT |
45 | .proc |
46 | .callinfo | |
47 | ||
48 | /* Make sure sr4-sr7 are set to zero for the kernel address space */ | |
49 | mtsp %r0,%sr4 | |
50 | mtsp %r0,%sr5 | |
51 | mtsp %r0,%sr6 | |
52 | mtsp %r0,%sr7 | |
53 | ||
54 | /* Clear BSS (shouldn't the boot loader do this?) */ | |
55 | ||
56 | .import __bss_start,data | |
57 | .import __bss_stop,data | |
58 | ||
59 | load32 PA(__bss_start),%r3 | |
60 | load32 PA(__bss_stop),%r4 | |
61 | $bss_loop: | |
62 | cmpb,<<,n %r3,%r4,$bss_loop | |
63 | stw,ma %r0,4(%r3) | |
64 | ||
65 | /* Save away the arguments the boot loader passed in (32 bit args) */ | |
66 | load32 PA(boot_args),%r1 | |
67 | stw,ma %arg0,4(%r1) | |
68 | stw,ma %arg1,4(%r1) | |
69 | stw,ma %arg2,4(%r1) | |
70 | stw,ma %arg3,4(%r1) | |
71 | ||
332b42e4 | 72 | /* Initialize startup VM. Just map first 16/32 MB of memory */ |
1da177e4 LT |
73 | load32 PA(swapper_pg_dir),%r4 |
74 | mtctl %r4,%cr24 /* Initialize kernel root pointer */ | |
75 | mtctl %r4,%cr25 /* Initialize user root pointer */ | |
76 | ||
f24ffde4 | 77 | #if CONFIG_PGTABLE_LEVELS == 3 |
1da177e4 LT |
78 | /* Set pmd in pgd */ |
79 | load32 PA(pmd0),%r5 | |
80 | shrd %r5,PxD_VALUE_SHIFT,%r3 | |
2fd83038 | 81 | ldo (PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3 |
1da177e4 LT |
82 | stw %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4) |
83 | ldo ASM_PMD_ENTRY*ASM_PMD_ENTRY_SIZE(%r5),%r4 | |
84 | #else | |
85 | /* 2-level page table, so pmd == pgd */ | |
2fd83038 | 86 | ldo ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4),%r4 |
1da177e4 LT |
87 | #endif |
88 | ||
89 | /* Fill in pmd with enough pte directories */ | |
90 | load32 PA(pg0),%r1 | |
91 | SHRREG %r1,PxD_VALUE_SHIFT,%r3 | |
92 | ldo (PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3 | |
93 | ||
94 | ldi ASM_PT_INITIAL,%r1 | |
95 | ||
96 | 1: | |
97 | stw %r3,0(%r4) | |
80af0876 | 98 | ldo (PAGE_SIZE >> PxD_VALUE_SHIFT)(%r3),%r3 |
1da177e4 | 99 | addib,> -1,%r1,1b |
f24ffde4 | 100 | #if CONFIG_PGTABLE_LEVELS == 3 |
1da177e4 LT |
101 | ldo ASM_PMD_ENTRY_SIZE(%r4),%r4 |
102 | #else | |
103 | ldo ASM_PGD_ENTRY_SIZE(%r4),%r4 | |
104 | #endif | |
105 | ||
106 | ||
d7dd2ff1 JB |
107 | /* Now initialize the PTEs themselves. We use RWX for |
108 | * everything ... it will get remapped correctly later */ | |
109 | ldo 0+_PAGE_KERNEL_RWX(%r0),%r3 /* Hardwired 0 phys addr start */ | |
332b42e4 | 110 | load32 (1<<(KERNEL_INITIAL_ORDER-PAGE_SHIFT)),%r11 /* PFN count */ |
1da177e4 LT |
111 | load32 PA(pg0),%r1 |
112 | ||
113 | $pgt_fill_loop: | |
114 | STREGM %r3,ASM_PTE_ENTRY_SIZE(%r1) | |
2fd83038 HD |
115 | ldo (1<<PFN_PTE_SHIFT)(%r3),%r3 /* add one PFN */ |
116 | addib,> -1,%r11,$pgt_fill_loop | |
1da177e4 LT |
117 | nop |
118 | ||
119 | /* Load the return address...er...crash 'n burn */ | |
120 | copy %r0,%r2 | |
121 | ||
122 | /* And the RFI Target address too */ | |
089d5528 | 123 | load32 start_parisc,%r11 |
1da177e4 LT |
124 | |
125 | /* And the initial task pointer */ | |
126 | load32 init_thread_union,%r6 | |
127 | mtctl %r6,%cr30 | |
128 | ||
129 | /* And the stack pointer too */ | |
130 | ldo THREAD_SZ_ALGN(%r6),%sp | |
131 | ||
366dd4ea HD |
132 | #if defined(CONFIG_64BIT) && defined(CONFIG_FUNCTION_TRACER) |
133 | .import _mcount,data | |
134 | /* initialize mcount FPTR */ | |
135 | /* Get the global data pointer */ | |
136 | loadgp | |
137 | load32 PA(_mcount), %r10 | |
138 | std %dp,0x18(%r10) | |
139 | #endif | |
140 | ||
1da177e4 | 141 | #ifdef CONFIG_SMP |
25985edc | 142 | /* Set the smp rendezvous address into page zero. |
1da177e4 LT |
143 | ** It would be safer to do this in init_smp_config() but |
144 | ** it's just way easier to deal with here because | |
145 | ** of 64-bit function ptrs and the address is local to this file. | |
146 | */ | |
147 | load32 PA(smp_slave_stext),%r10 | |
148 | stw %r10,0x10(%r0) /* MEM_RENDEZ */ | |
149 | stw %r0,0x28(%r0) /* MEM_RENDEZ_HI - assume addr < 4GB */ | |
150 | ||
151 | /* FALLTHROUGH */ | |
152 | .procend | |
153 | ||
154 | /* | |
155 | ** Code Common to both Monarch and Slave processors. | |
156 | ** Entry: | |
157 | ** | |
158 | ** 1.1: | |
159 | ** %r11 must contain RFI target address. | |
160 | ** %r25/%r26 args to pass to target function | |
161 | ** %r2 in case rfi target decides it didn't like something | |
162 | ** | |
163 | ** 2.0w: | |
164 | ** %r3 PDCE_PROC address | |
165 | ** %r11 RFI target address | |
166 | ** | |
167 | ** Caller must init: SR4-7, %sp, %r10, %cr24/25, | |
168 | */ | |
169 | common_stext: | |
170 | .proc | |
171 | .callinfo | |
172 | #else | |
173 | /* Clear PDC entry point - we won't use it */ | |
174 | stw %r0,0x10(%r0) /* MEM_RENDEZ */ | |
175 | stw %r0,0x28(%r0) /* MEM_RENDEZ_HI */ | |
176 | #endif /*CONFIG_SMP*/ | |
177 | ||
413059f2 | 178 | #ifdef CONFIG_64BIT |
1da177e4 LT |
179 | tophys_r1 %sp |
180 | ||
181 | /* Save the rfi target address */ | |
182 | ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10 | |
183 | tophys_r1 %r10 | |
184 | std %r11, TASK_PT_GR11(%r10) | |
185 | /* Switch to wide mode Superdome doesn't support narrow PDC | |
186 | ** calls. | |
187 | */ | |
188 | 1: mfia %rp /* clear upper part of pcoq */ | |
189 | ldo 2f-1b(%rp),%rp | |
190 | depdi 0,31,32,%rp | |
191 | bv (%rp) | |
192 | ssm PSW_SM_W,%r0 | |
193 | ||
194 | /* Set Wide mode as the "Default" (eg for traps) | |
195 | ** First trap occurs *right* after (or part of) rfi for slave CPUs. | |
196 | ** Someday, palo might not do this for the Monarch either. | |
197 | */ | |
198 | 2: | |
199 | #define MEM_PDC_LO 0x388 | |
200 | #define MEM_PDC_HI 0x35C | |
201 | ldw MEM_PDC_LO(%r0),%r3 | |
202 | ldw MEM_PDC_HI(%r0),%r6 | |
203 | depd %r6, 31, 32, %r3 /* move to upper word */ | |
204 | ||
54e181e0 HD |
205 | mfctl %cr30,%r6 /* PCX-W2 firmware bug */ |
206 | ||
1da177e4 LT |
207 | ldo PDC_PSW(%r0),%arg0 /* 21 */ |
208 | ldo PDC_PSW_SET_DEFAULTS(%r0),%arg1 /* 2 */ | |
209 | ldo PDC_PSW_WIDE_BIT(%r0),%arg2 /* 2 */ | |
210 | load32 PA(stext_pdc_ret), %rp | |
211 | bv (%r3) | |
212 | copy %r0,%arg3 | |
213 | ||
214 | stext_pdc_ret: | |
54e181e0 HD |
215 | mtctl %r6,%cr30 /* restore task thread info */ |
216 | ||
1da177e4 LT |
217 | /* restore rfi target address*/ |
218 | ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10 | |
219 | tophys_r1 %r10 | |
220 | ldd TASK_PT_GR11(%r10), %r11 | |
221 | tovirt_r1 %sp | |
222 | #endif | |
223 | ||
224 | /* PARANOID: clear user scratch/user space SR's */ | |
225 | mtsp %r0,%sr0 | |
226 | mtsp %r0,%sr1 | |
227 | mtsp %r0,%sr2 | |
228 | mtsp %r0,%sr3 | |
229 | ||
230 | /* Initialize Protection Registers */ | |
231 | mtctl %r0,%cr8 | |
232 | mtctl %r0,%cr9 | |
233 | mtctl %r0,%cr12 | |
234 | mtctl %r0,%cr13 | |
235 | ||
1da177e4 LT |
236 | /* Initialize the global data pointer */ |
237 | loadgp | |
238 | ||
239 | /* Set up our interrupt table. HPMCs might not work after this! | |
240 | * | |
241 | * We need to install the correct iva for PA1.1 or PA2.0. The | |
242 | * following short sequence of instructions can determine this | |
243 | * (without being illegal on a PA1.1 machine). | |
244 | */ | |
413059f2 | 245 | #ifndef CONFIG_64BIT |
1da177e4 LT |
246 | ldi 32,%r10 |
247 | mtctl %r10,%cr11 | |
248 | .level 2.0 | |
249 | mfctl,w %cr11,%r10 | |
250 | .level 1.1 | |
251 | comib,<>,n 0,%r10,$is_pa20 | |
252 | ldil L%PA(fault_vector_11),%r10 | |
253 | b $install_iva | |
254 | ldo R%PA(fault_vector_11)(%r10),%r10 | |
255 | ||
256 | $is_pa20: | |
257 | .level LEVEL /* restore 1.1 || 2.0w */ | |
413059f2 | 258 | #endif /*!CONFIG_64BIT*/ |
1da177e4 LT |
259 | load32 PA(fault_vector_20),%r10 |
260 | ||
261 | $install_iva: | |
262 | mtctl %r10,%cr14 | |
263 | ||
896a3756 | 264 | b aligned_rfi /* Prepare to RFI! Man all the cannons! */ |
1da177e4 LT |
265 | nop |
266 | ||
896a3756 | 267 | .align 128 |
1da177e4 | 268 | aligned_rfi: |
896a3756 | 269 | pcxt_ssm_bug |
1da177e4 | 270 | |
896a3756 GG |
271 | rsm PSW_SM_QUIET,%r0 /* off troublesome PSW bits */ |
272 | /* Don't need NOPs, have 8 compliant insn before rfi */ | |
1da177e4 | 273 | |
1da177e4 LT |
274 | mtctl %r0,%cr17 /* Clear IIASQ tail */ |
275 | mtctl %r0,%cr17 /* Clear IIASQ head */ | |
276 | ||
277 | /* Load RFI target into PC queue */ | |
278 | mtctl %r11,%cr18 /* IIAOQ head */ | |
279 | ldo 4(%r11),%r11 | |
280 | mtctl %r11,%cr18 /* IIAOQ tail */ | |
896a3756 GG |
281 | |
282 | load32 KERNEL_PSW,%r10 | |
283 | mtctl %r10,%ipsw | |
1da177e4 | 284 | |
896a3756 | 285 | /* Jump through hyperspace to Virt Mode */ |
1da177e4 LT |
286 | rfi |
287 | nop | |
288 | ||
289 | .procend | |
290 | ||
291 | #ifdef CONFIG_SMP | |
292 | ||
293 | .import smp_init_current_idle_task,data | |
294 | .import smp_callin,code | |
295 | ||
413059f2 | 296 | #ifndef CONFIG_64BIT |
1da177e4 LT |
297 | smp_callin_rtn: |
298 | .proc | |
299 | .callinfo | |
300 | break 1,1 /* Break if returned from start_secondary */ | |
301 | nop | |
302 | nop | |
303 | .procend | |
413059f2 | 304 | #endif /*!CONFIG_64BIT*/ |
1da177e4 LT |
305 | |
306 | /*************************************************************************** | |
307 | * smp_slave_stext is executed by all non-monarch Processors when the Monarch | |
308 | * pokes the slave CPUs in smp.c:smp_boot_cpus(). | |
309 | * | |
310 | * Once here, registers values are initialized in order to branch to virtual | |
311 | * mode. Once all available/eligible CPUs are in virtual mode, all are | |
312 | * released and start out by executing their own idle task. | |
313 | *****************************************************************************/ | |
314 | smp_slave_stext: | |
315 | .proc | |
316 | .callinfo | |
317 | ||
318 | /* | |
319 | ** Initialize Space registers | |
320 | */ | |
321 | mtsp %r0,%sr4 | |
322 | mtsp %r0,%sr5 | |
323 | mtsp %r0,%sr6 | |
324 | mtsp %r0,%sr7 | |
325 | ||
326 | /* Initialize the SP - monarch sets up smp_init_current_idle_task */ | |
327 | load32 PA(smp_init_current_idle_task),%sp | |
328 | LDREG 0(%sp),%sp /* load task address */ | |
329 | tophys_r1 %sp | |
330 | LDREG TASK_THREAD_INFO(%sp),%sp | |
331 | mtctl %sp,%cr30 /* store in cr30 */ | |
332 | ldo THREAD_SZ_ALGN(%sp),%sp | |
333 | ||
334 | /* point CPU to kernel page tables */ | |
335 | load32 PA(swapper_pg_dir),%r4 | |
336 | mtctl %r4,%cr24 /* Initialize kernel root pointer */ | |
337 | mtctl %r4,%cr25 /* Initialize user root pointer */ | |
338 | ||
413059f2 | 339 | #ifdef CONFIG_64BIT |
1da177e4 LT |
340 | /* Setup PDCE_PROC entry */ |
341 | copy %arg0,%r3 | |
342 | #else | |
343 | /* Load RFI *return* address in case smp_callin bails */ | |
344 | load32 smp_callin_rtn,%r2 | |
345 | #endif | |
346 | ||
347 | /* Load RFI target address. */ | |
348 | load32 smp_callin,%r11 | |
349 | ||
350 | /* ok...common code can handle the rest */ | |
351 | b common_stext | |
352 | nop | |
353 | ||
354 | .procend | |
355 | #endif /* CONFIG_SMP */ | |
8e9e9844 | 356 | |
161bd3bf | 357 | ENDPROC(parisc_kernel_start) |
8e9e9844 | 358 | |
413059f2 | 359 | #ifndef CONFIG_64BIT |
54cb27a7 | 360 | .section .data..read_mostly |
1da177e4 LT |
361 | |
362 | .align 4 | |
363 | .export $global$,data | |
364 | ||
365 | .type $global$,@object | |
366 | .size $global$,4 | |
367 | $global$: | |
368 | .word 0 | |
413059f2 | 369 | #endif /*!CONFIG_64BIT*/ |