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1da177e4 LT |
1 | /* |
2 | * Parisc performance counters | |
3 | * Copyright (C) 2001 Randolph Chung <tausq@debian.org> | |
4 | * | |
5 | * This code is derived, with permission, from HP/UX sources. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2, or (at your option) | |
10 | * any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * Edited comment from original sources: | |
24 | * | |
25 | * This driver programs the PCX-U/PCX-W performance counters | |
26 | * on the PA-RISC 2.0 chips. The driver keeps all images now | |
06fe9fb4 | 27 | * internally to the kernel to hopefully eliminate the possibility |
1da177e4 LT |
28 | * of a bad image halting the CPU. Also, there are different |
29 | * images for the PCX-W and later chips vs the PCX-U chips. | |
30 | * | |
31 | * Only 1 process is allowed to access the driver at any time, | |
32 | * so the only protection that is needed is at open and close. | |
33 | * A variable "perf_enabled" is used to hold the state of the | |
34 | * driver. The spinlock "perf_lock" is used to protect the | |
35 | * modification of the state during open/close operations so | |
36 | * multiple processes don't get into the driver simultaneously. | |
37 | * | |
38 | * This driver accesses the processor directly vs going through | |
39 | * the PDC INTRIGUE calls. This is done to eliminate bugs introduced | |
40 | * in various PDC revisions. The code is much more maintainable | |
41 | * and reliable this way vs having to debug on every version of PDC | |
74e3f6e6 | 42 | * on every box. |
1da177e4 LT |
43 | */ |
44 | ||
a9415644 | 45 | #include <linux/capability.h> |
1da177e4 LT |
46 | #include <linux/init.h> |
47 | #include <linux/proc_fs.h> | |
48 | #include <linux/miscdevice.h> | |
49 | #include <linux/spinlock.h> | |
50 | ||
7c0f6ba6 | 51 | #include <linux/uaccess.h> |
1da177e4 LT |
52 | #include <asm/perf.h> |
53 | #include <asm/parisc-device.h> | |
54 | #include <asm/processor.h> | |
55 | #include <asm/runway.h> | |
56 | #include <asm/io.h> /* for __raw_read() */ | |
57 | ||
58 | #include "perf_images.h" | |
59 | ||
60 | #define MAX_RDR_WORDS 24 | |
61 | #define PERF_VERSION 2 /* derived from hpux's PI v2 interface */ | |
62 | ||
63 | /* definition of RDR regs */ | |
64 | struct rdr_tbl_ent { | |
65 | uint16_t width; | |
66 | uint8_t num_words; | |
67 | uint8_t write_control; | |
68 | }; | |
69 | ||
8039de10 | 70 | static int perf_processor_interface __read_mostly = UNKNOWN_INTF; |
cb6fc18e | 71 | static int perf_enabled __read_mostly; |
1da177e4 | 72 | static spinlock_t perf_lock; |
cb6fc18e | 73 | struct parisc_device *cpu_device __read_mostly; |
1da177e4 LT |
74 | |
75 | /* RDRs to write for PCX-W */ | |
cb6fc18e | 76 | static const int perf_rdrs_W[] = |
1da177e4 LT |
77 | { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 }; |
78 | ||
79 | /* RDRs to write for PCX-U */ | |
cb6fc18e | 80 | static const int perf_rdrs_U[] = |
1da177e4 LT |
81 | { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 }; |
82 | ||
83 | /* RDR register descriptions for PCX-W */ | |
cb6fc18e | 84 | static const struct rdr_tbl_ent perf_rdr_tbl_W[] = { |
1da177e4 LT |
85 | { 19, 1, 8 }, /* RDR 0 */ |
86 | { 16, 1, 16 }, /* RDR 1 */ | |
87 | { 72, 2, 0 }, /* RDR 2 */ | |
88 | { 81, 2, 0 }, /* RDR 3 */ | |
89 | { 328, 6, 0 }, /* RDR 4 */ | |
90 | { 160, 3, 0 }, /* RDR 5 */ | |
91 | { 336, 6, 0 }, /* RDR 6 */ | |
92 | { 164, 3, 0 }, /* RDR 7 */ | |
93 | { 0, 0, 0 }, /* RDR 8 */ | |
94 | { 35, 1, 0 }, /* RDR 9 */ | |
95 | { 6, 1, 0 }, /* RDR 10 */ | |
96 | { 18, 1, 0 }, /* RDR 11 */ | |
97 | { 13, 1, 0 }, /* RDR 12 */ | |
98 | { 8, 1, 0 }, /* RDR 13 */ | |
99 | { 8, 1, 0 }, /* RDR 14 */ | |
100 | { 8, 1, 0 }, /* RDR 15 */ | |
101 | { 1530, 24, 0 }, /* RDR 16 */ | |
102 | { 16, 1, 0 }, /* RDR 17 */ | |
103 | { 4, 1, 0 }, /* RDR 18 */ | |
104 | { 0, 0, 0 }, /* RDR 19 */ | |
105 | { 152, 3, 24 }, /* RDR 20 */ | |
106 | { 152, 3, 24 }, /* RDR 21 */ | |
107 | { 233, 4, 48 }, /* RDR 22 */ | |
108 | { 233, 4, 48 }, /* RDR 23 */ | |
109 | { 71, 2, 0 }, /* RDR 24 */ | |
110 | { 71, 2, 0 }, /* RDR 25 */ | |
111 | { 11, 1, 0 }, /* RDR 26 */ | |
112 | { 18, 1, 0 }, /* RDR 27 */ | |
113 | { 128, 2, 0 }, /* RDR 28 */ | |
114 | { 0, 0, 0 }, /* RDR 29 */ | |
115 | { 16, 1, 0 }, /* RDR 30 */ | |
116 | { 16, 1, 0 }, /* RDR 31 */ | |
117 | }; | |
118 | ||
119 | /* RDR register descriptions for PCX-U */ | |
cb6fc18e | 120 | static const struct rdr_tbl_ent perf_rdr_tbl_U[] = { |
1da177e4 LT |
121 | { 19, 1, 8 }, /* RDR 0 */ |
122 | { 32, 1, 16 }, /* RDR 1 */ | |
123 | { 20, 1, 0 }, /* RDR 2 */ | |
124 | { 0, 0, 0 }, /* RDR 3 */ | |
125 | { 344, 6, 0 }, /* RDR 4 */ | |
126 | { 176, 3, 0 }, /* RDR 5 */ | |
127 | { 336, 6, 0 }, /* RDR 6 */ | |
128 | { 0, 0, 0 }, /* RDR 7 */ | |
129 | { 0, 0, 0 }, /* RDR 8 */ | |
130 | { 0, 0, 0 }, /* RDR 9 */ | |
131 | { 28, 1, 0 }, /* RDR 10 */ | |
132 | { 33, 1, 0 }, /* RDR 11 */ | |
133 | { 0, 0, 0 }, /* RDR 12 */ | |
134 | { 230, 4, 0 }, /* RDR 13 */ | |
135 | { 32, 1, 0 }, /* RDR 14 */ | |
136 | { 128, 2, 0 }, /* RDR 15 */ | |
137 | { 1494, 24, 0 }, /* RDR 16 */ | |
138 | { 18, 1, 0 }, /* RDR 17 */ | |
139 | { 4, 1, 0 }, /* RDR 18 */ | |
140 | { 0, 0, 0 }, /* RDR 19 */ | |
141 | { 158, 3, 24 }, /* RDR 20 */ | |
142 | { 158, 3, 24 }, /* RDR 21 */ | |
143 | { 194, 4, 48 }, /* RDR 22 */ | |
144 | { 194, 4, 48 }, /* RDR 23 */ | |
145 | { 71, 2, 0 }, /* RDR 24 */ | |
146 | { 71, 2, 0 }, /* RDR 25 */ | |
147 | { 28, 1, 0 }, /* RDR 26 */ | |
148 | { 33, 1, 0 }, /* RDR 27 */ | |
149 | { 88, 2, 0 }, /* RDR 28 */ | |
150 | { 32, 1, 0 }, /* RDR 29 */ | |
151 | { 24, 1, 0 }, /* RDR 30 */ | |
152 | { 16, 1, 0 }, /* RDR 31 */ | |
153 | }; | |
154 | ||
155 | /* | |
156 | * A non-zero write_control in the above tables is a byte offset into | |
157 | * this array. | |
158 | */ | |
cb6fc18e | 159 | static const uint64_t perf_bitmasks[] = { |
1da177e4 LT |
160 | 0x0000000000000000ul, /* first dbl word must be zero */ |
161 | 0xfdffe00000000000ul, /* RDR0 bitmask */ | |
162 | 0x003f000000000000ul, /* RDR1 bitmask */ | |
163 | 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */ | |
164 | 0xfffffffffffffffful, | |
165 | 0xfffffffc00000000ul, | |
166 | 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */ | |
167 | 0xfffffffffffffffful, | |
168 | 0xfffffffffffffffcul, | |
169 | 0xff00000000000000ul | |
170 | }; | |
171 | ||
172 | /* | |
173 | * Write control bitmasks for Pa-8700 processor given | |
7022672e | 174 | * some things have changed slightly. |
1da177e4 | 175 | */ |
cb6fc18e | 176 | static const uint64_t perf_bitmasks_piranha[] = { |
1da177e4 LT |
177 | 0x0000000000000000ul, /* first dbl word must be zero */ |
178 | 0xfdffe00000000000ul, /* RDR0 bitmask */ | |
179 | 0x003f000000000000ul, /* RDR1 bitmask */ | |
180 | 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */ | |
181 | 0xfffffffffffffffful, | |
182 | 0xfffffffc00000000ul, | |
183 | 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */ | |
184 | 0xfffffffffffffffful, | |
185 | 0xfffffffffffffffful, | |
186 | 0xfffc000000000000ul | |
187 | }; | |
188 | ||
cb6fc18e | 189 | static const uint64_t *bitmask_array; /* array of bitmasks to use */ |
1da177e4 LT |
190 | |
191 | /****************************************************************************** | |
192 | * Function Prototypes | |
193 | *****************************************************************************/ | |
194 | static int perf_config(uint32_t *image_ptr); | |
195 | static int perf_release(struct inode *inode, struct file *file); | |
196 | static int perf_open(struct inode *inode, struct file *file); | |
197 | static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos); | |
74e3f6e6 AY |
198 | static ssize_t perf_write(struct file *file, const char __user *buf, |
199 | size_t count, loff_t *ppos); | |
ad7dd338 | 200 | static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg); |
1da177e4 LT |
201 | static void perf_start_counters(void); |
202 | static int perf_stop_counters(uint32_t *raddr); | |
cb6fc18e | 203 | static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num); |
1da177e4 LT |
204 | static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer); |
205 | static int perf_rdr_clear(uint32_t rdr_num); | |
206 | static int perf_write_image(uint64_t *memaddr); | |
207 | static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer); | |
208 | ||
209 | /* External Assembly Routines */ | |
210 | extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width); | |
211 | extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width); | |
212 | extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer); | |
213 | extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer); | |
214 | extern void perf_intrigue_enable_perf_counters (void); | |
215 | extern void perf_intrigue_disable_perf_counters (void); | |
216 | ||
217 | /****************************************************************************** | |
218 | * Function Definitions | |
219 | *****************************************************************************/ | |
220 | ||
221 | ||
222 | /* | |
223 | * configure: | |
224 | * | |
74e3f6e6 | 225 | * Configure the cpu with a given data image. First turn off the counters, |
1da177e4 LT |
226 | * then download the image, then turn the counters back on. |
227 | */ | |
228 | static int perf_config(uint32_t *image_ptr) | |
229 | { | |
230 | long error; | |
231 | uint32_t raddr[4]; | |
232 | ||
233 | /* Stop the counters*/ | |
234 | error = perf_stop_counters(raddr); | |
235 | if (error != 0) { | |
236 | printk("perf_config: perf_stop_counters = %ld\n", error); | |
74e3f6e6 | 237 | return -EINVAL; |
1da177e4 LT |
238 | } |
239 | ||
240 | printk("Preparing to write image\n"); | |
241 | /* Write the image to the chip */ | |
242 | error = perf_write_image((uint64_t *)image_ptr); | |
243 | if (error != 0) { | |
244 | printk("perf_config: DOWNLOAD = %ld\n", error); | |
74e3f6e6 | 245 | return -EINVAL; |
1da177e4 LT |
246 | } |
247 | ||
248 | printk("Preparing to start counters\n"); | |
249 | ||
250 | /* Start the counters */ | |
251 | perf_start_counters(); | |
252 | ||
253 | return sizeof(uint32_t); | |
254 | } | |
255 | ||
256 | /* | |
74e3f6e6 | 257 | * Open the device and initialize all of its memory. The device is only |
1da177e4 LT |
258 | * opened once, but can be "queried" by multiple processes that know its |
259 | * file descriptor. | |
260 | */ | |
261 | static int perf_open(struct inode *inode, struct file *file) | |
262 | { | |
263 | spin_lock(&perf_lock); | |
264 | if (perf_enabled) { | |
265 | spin_unlock(&perf_lock); | |
266 | return -EBUSY; | |
267 | } | |
268 | perf_enabled = 1; | |
269 | spin_unlock(&perf_lock); | |
270 | ||
271 | return 0; | |
272 | } | |
273 | ||
274 | /* | |
275 | * Close the device. | |
276 | */ | |
277 | static int perf_release(struct inode *inode, struct file *file) | |
278 | { | |
279 | spin_lock(&perf_lock); | |
280 | perf_enabled = 0; | |
281 | spin_unlock(&perf_lock); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | /* | |
287 | * Read does nothing for this driver | |
288 | */ | |
289 | static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos) | |
290 | { | |
291 | return 0; | |
292 | } | |
293 | ||
294 | /* | |
295 | * write: | |
296 | * | |
297 | * This routine downloads the image to the chip. It must be | |
298 | * called on the processor that the download should happen | |
299 | * on. | |
300 | */ | |
74e3f6e6 AY |
301 | static ssize_t perf_write(struct file *file, const char __user *buf, |
302 | size_t count, loff_t *ppos) | |
1da177e4 | 303 | { |
1da177e4 LT |
304 | size_t image_size; |
305 | uint32_t image_type; | |
306 | uint32_t interface_type; | |
307 | uint32_t test; | |
308 | ||
74e3f6e6 | 309 | if (perf_processor_interface == ONYX_INTF) |
1da177e4 | 310 | image_size = PCXU_IMAGE_SIZE; |
74e3f6e6 | 311 | else if (perf_processor_interface == CUDA_INTF) |
1da177e4 | 312 | image_size = PCXW_IMAGE_SIZE; |
74e3f6e6 | 313 | else |
1da177e4 LT |
314 | return -EFAULT; |
315 | ||
316 | if (!capable(CAP_SYS_ADMIN)) | |
317 | return -EACCES; | |
318 | ||
319 | if (count != sizeof(uint32_t)) | |
320 | return -EIO; | |
321 | ||
82cbd568 DC |
322 | if (copy_from_user(&image_type, buf, sizeof(uint32_t))) |
323 | return -EFAULT; | |
1da177e4 LT |
324 | |
325 | /* Get the interface type and test type */ | |
326 | interface_type = (image_type >> 16) & 0xffff; | |
327 | test = (image_type & 0xffff); | |
328 | ||
329 | /* Make sure everything makes sense */ | |
330 | ||
331 | /* First check the machine type is correct for | |
332 | the requested image */ | |
74e3f6e6 AY |
333 | if (((perf_processor_interface == CUDA_INTF) && |
334 | (interface_type != CUDA_INTF)) || | |
335 | ((perf_processor_interface == ONYX_INTF) && | |
336 | (interface_type != ONYX_INTF))) | |
1da177e4 LT |
337 | return -EINVAL; |
338 | ||
339 | /* Next check to make sure the requested image | |
340 | is valid */ | |
74e3f6e6 | 341 | if (((interface_type == CUDA_INTF) && |
1da177e4 | 342 | (test >= MAX_CUDA_IMAGES)) || |
74e3f6e6 AY |
343 | ((interface_type == ONYX_INTF) && |
344 | (test >= MAX_ONYX_IMAGES))) | |
1da177e4 LT |
345 | return -EINVAL; |
346 | ||
347 | /* Copy the image into the processor */ | |
74e3f6e6 | 348 | if (interface_type == CUDA_INTF) |
1da177e4 LT |
349 | return perf_config(cuda_images[test]); |
350 | else | |
351 | return perf_config(onyx_images[test]); | |
352 | ||
353 | return count; | |
354 | } | |
355 | ||
356 | /* | |
357 | * Patch the images that need to know the IVA addresses. | |
358 | */ | |
359 | static void perf_patch_images(void) | |
360 | { | |
361 | #if 0 /* FIXME!! */ | |
74e3f6e6 | 362 | /* |
1da177e4 LT |
363 | * NOTE: this routine is VERY specific to the current TLB image. |
364 | * If the image is changed, this routine might also need to be changed. | |
365 | */ | |
366 | extern void $i_itlb_miss_2_0(); | |
367 | extern void $i_dtlb_miss_2_0(); | |
368 | extern void PA2_0_iva(); | |
369 | ||
74e3f6e6 | 370 | /* |
1da177e4 | 371 | * We can only use the lower 32-bits, the upper 32-bits should be 0 |
74e3f6e6 | 372 | * anyway given this is in the kernel |
1da177e4 LT |
373 | */ |
374 | uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0); | |
375 | uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0); | |
376 | uint32_t IVAaddress = (uint32_t)&PA2_0_iva; | |
377 | ||
378 | if (perf_processor_interface == ONYX_INTF) { | |
379 | /* clear last 2 bytes */ | |
74e3f6e6 | 380 | onyx_images[TLBMISS][15] &= 0xffffff00; |
1da177e4 LT |
381 | /* set 2 bytes */ |
382 | onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); | |
383 | onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00; | |
384 | onyx_images[TLBMISS][17] = itlb_addr; | |
385 | ||
386 | /* clear last 2 bytes */ | |
74e3f6e6 | 387 | onyx_images[TLBHANDMISS][15] &= 0xffffff00; |
1da177e4 LT |
388 | /* set 2 bytes */ |
389 | onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); | |
390 | onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00; | |
391 | onyx_images[TLBHANDMISS][17] = itlb_addr; | |
392 | ||
393 | /* clear last 2 bytes */ | |
74e3f6e6 | 394 | onyx_images[BIG_CPI][15] &= 0xffffff00; |
1da177e4 LT |
395 | /* set 2 bytes */ |
396 | onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24)); | |
397 | onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00; | |
398 | onyx_images[BIG_CPI][17] = itlb_addr; | |
399 | ||
400 | onyx_images[PANIC][15] &= 0xffffff00; /* clear last 2 bytes */ | |
401 | onyx_images[PANIC][15] |= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */ | |
402 | onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00; | |
403 | ||
404 | ||
405 | } else if (perf_processor_interface == CUDA_INTF) { | |
406 | /* Cuda interface */ | |
74e3f6e6 | 407 | cuda_images[TLBMISS][16] = |
1da177e4 LT |
408 | (cuda_images[TLBMISS][16]&0xffff0000) | |
409 | ((dtlb_addr >> 8)&0x0000ffff); | |
74e3f6e6 | 410 | cuda_images[TLBMISS][17] = |
1da177e4 LT |
411 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); |
412 | cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000; | |
413 | ||
74e3f6e6 | 414 | cuda_images[TLBHANDMISS][16] = |
1da177e4 LT |
415 | (cuda_images[TLBHANDMISS][16]&0xffff0000) | |
416 | ((dtlb_addr >> 8)&0x0000ffff); | |
74e3f6e6 | 417 | cuda_images[TLBHANDMISS][17] = |
1da177e4 LT |
418 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); |
419 | cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000; | |
420 | ||
74e3f6e6 | 421 | cuda_images[BIG_CPI][16] = |
1da177e4 LT |
422 | (cuda_images[BIG_CPI][16]&0xffff0000) | |
423 | ((dtlb_addr >> 8)&0x0000ffff); | |
74e3f6e6 | 424 | cuda_images[BIG_CPI][17] = |
1da177e4 LT |
425 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); |
426 | cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000; | |
427 | } else { | |
428 | /* Unknown type */ | |
429 | } | |
430 | #endif | |
431 | } | |
432 | ||
433 | ||
434 | /* | |
435 | * ioctl routine | |
74e3f6e6 | 436 | * All routines effect the processor that they are executed on. Thus you |
1da177e4 LT |
437 | * must be running on the processor that you wish to change. |
438 | */ | |
439 | ||
ad7dd338 | 440 | static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
441 | { |
442 | long error_start; | |
ad7dd338 CH |
443 | uint32_t raddr[4]; |
444 | int error = 0; | |
1da177e4 LT |
445 | |
446 | switch (cmd) { | |
447 | ||
448 | case PA_PERF_ON: | |
449 | /* Start the counters */ | |
450 | perf_start_counters(); | |
ad7dd338 | 451 | break; |
1da177e4 LT |
452 | |
453 | case PA_PERF_OFF: | |
454 | error_start = perf_stop_counters(raddr); | |
455 | if (error_start != 0) { | |
456 | printk(KERN_ERR "perf_off: perf_stop_counters = %ld\n", error_start); | |
ad7dd338 CH |
457 | error = -EFAULT; |
458 | break; | |
1da177e4 LT |
459 | } |
460 | ||
461 | /* copy out the Counters */ | |
74e3f6e6 | 462 | if (copy_to_user((void __user *)arg, raddr, |
1da177e4 | 463 | sizeof (raddr)) != 0) { |
ad7dd338 CH |
464 | error = -EFAULT; |
465 | break; | |
1da177e4 | 466 | } |
ad7dd338 | 467 | break; |
1da177e4 LT |
468 | |
469 | case PA_PERF_VERSION: | |
470 | /* Return the version # */ | |
ad7dd338 CH |
471 | error = put_user(PERF_VERSION, (int *)arg); |
472 | break; | |
1da177e4 LT |
473 | |
474 | default: | |
ad7dd338 | 475 | error = -ENOTTY; |
1da177e4 | 476 | } |
ad7dd338 | 477 | |
ad7dd338 | 478 | return error; |
1da177e4 LT |
479 | } |
480 | ||
5dfe4c96 | 481 | static const struct file_operations perf_fops = { |
1da177e4 LT |
482 | .llseek = no_llseek, |
483 | .read = perf_read, | |
484 | .write = perf_write, | |
ad7dd338 CH |
485 | .unlocked_ioctl = perf_ioctl, |
486 | .compat_ioctl = perf_ioctl, | |
1da177e4 LT |
487 | .open = perf_open, |
488 | .release = perf_release | |
489 | }; | |
74e3f6e6 | 490 | |
1da177e4 LT |
491 | static struct miscdevice perf_dev = { |
492 | MISC_DYNAMIC_MINOR, | |
493 | PA_PERF_DEV, | |
494 | &perf_fops | |
495 | }; | |
496 | ||
497 | /* | |
498 | * Initialize the module | |
499 | */ | |
500 | static int __init perf_init(void) | |
501 | { | |
502 | int ret; | |
503 | ||
504 | /* Determine correct processor interface to use */ | |
505 | bitmask_array = perf_bitmasks; | |
506 | ||
507 | if (boot_cpu_data.cpu_type == pcxu || | |
508 | boot_cpu_data.cpu_type == pcxu_) { | |
509 | perf_processor_interface = ONYX_INTF; | |
510 | } else if (boot_cpu_data.cpu_type == pcxw || | |
511 | boot_cpu_data.cpu_type == pcxw_ || | |
512 | boot_cpu_data.cpu_type == pcxw2 || | |
2cbd42db KM |
513 | boot_cpu_data.cpu_type == mako || |
514 | boot_cpu_data.cpu_type == mako2) { | |
1da177e4 LT |
515 | perf_processor_interface = CUDA_INTF; |
516 | if (boot_cpu_data.cpu_type == pcxw2 || | |
2cbd42db KM |
517 | boot_cpu_data.cpu_type == mako || |
518 | boot_cpu_data.cpu_type == mako2) | |
1da177e4 LT |
519 | bitmask_array = perf_bitmasks_piranha; |
520 | } else { | |
521 | perf_processor_interface = UNKNOWN_INTF; | |
522 | printk("Performance monitoring counters not supported on this processor\n"); | |
523 | return -ENODEV; | |
524 | } | |
525 | ||
526 | ret = misc_register(&perf_dev); | |
527 | if (ret) { | |
528 | printk(KERN_ERR "Performance monitoring counters: " | |
529 | "cannot register misc device.\n"); | |
530 | return ret; | |
531 | } | |
532 | ||
533 | /* Patch the images to match the system */ | |
534 | perf_patch_images(); | |
535 | ||
536 | spin_lock_init(&perf_lock); | |
537 | ||
538 | /* TODO: this only lets us access the first cpu.. what to do for SMP? */ | |
ef017beb | 539 | cpu_device = per_cpu(cpu_data, 0).dev; |
1da177e4 | 540 | printk("Performance monitoring counters enabled for %s\n", |
ef017beb | 541 | per_cpu(cpu_data, 0).dev->name); |
1da177e4 LT |
542 | |
543 | return 0; | |
544 | } | |
15becabd | 545 | device_initcall(perf_init); |
1da177e4 LT |
546 | |
547 | /* | |
548 | * perf_start_counters(void) | |
549 | * | |
550 | * Start the counters. | |
551 | */ | |
552 | static void perf_start_counters(void) | |
553 | { | |
554 | /* Enable performance monitor counters */ | |
555 | perf_intrigue_enable_perf_counters(); | |
556 | } | |
557 | ||
558 | /* | |
559 | * perf_stop_counters | |
560 | * | |
561 | * Stop the performance counters and save counts | |
562 | * in a per_processor array. | |
563 | */ | |
564 | static int perf_stop_counters(uint32_t *raddr) | |
565 | { | |
566 | uint64_t userbuf[MAX_RDR_WORDS]; | |
567 | ||
568 | /* Disable performance counters */ | |
569 | perf_intrigue_disable_perf_counters(); | |
570 | ||
571 | if (perf_processor_interface == ONYX_INTF) { | |
572 | uint64_t tmp64; | |
573 | /* | |
574 | * Read the counters | |
575 | */ | |
576 | if (!perf_rdr_read_ubuf(16, userbuf)) | |
577 | return -13; | |
578 | ||
7022672e | 579 | /* Counter0 is bits 1398 to 1429 */ |
1da177e4 LT |
580 | tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000; |
581 | tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff; | |
582 | /* OR sticky0 (bit 1430) to counter0 bit 32 */ | |
583 | tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000; | |
584 | raddr[0] = (uint32_t)tmp64; | |
585 | ||
7022672e | 586 | /* Counter1 is bits 1431 to 1462 */ |
1da177e4 LT |
587 | tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff; |
588 | /* OR sticky1 (bit 1463) to counter1 bit 32 */ | |
589 | tmp64 |= (userbuf[22] << 23) & 0x0000000080000000; | |
590 | raddr[1] = (uint32_t)tmp64; | |
591 | ||
7022672e | 592 | /* Counter2 is bits 1464 to 1495 */ |
1da177e4 LT |
593 | tmp64 = (userbuf[22] << 24) & 0x00000000ff000000; |
594 | tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff; | |
595 | /* OR sticky2 (bit 1496) to counter2 bit 32 */ | |
596 | tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000; | |
597 | raddr[2] = (uint32_t)tmp64; | |
74e3f6e6 | 598 | |
7022672e | 599 | /* Counter3 is bits 1497 to 1528 */ |
1da177e4 LT |
600 | tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff; |
601 | /* OR sticky3 (bit 1529) to counter3 bit 32 */ | |
602 | tmp64 |= (userbuf[23] << 25) & 0x0000000080000000; | |
603 | raddr[3] = (uint32_t)tmp64; | |
604 | ||
605 | /* | |
606 | * Zero out the counters | |
607 | */ | |
608 | ||
609 | /* | |
610 | * The counters and sticky-bits comprise the last 132 bits | |
611 | * (1398 - 1529) of RDR16 on a U chip. We'll zero these | |
612 | * out the easy way: zero out last 10 bits of dword 21, | |
613 | * all of dword 22 and 58 bits (plus 6 don't care bits) of | |
614 | * dword 23. | |
615 | */ | |
616 | userbuf[21] &= 0xfffffffffffffc00ul; /* 0 to last 10 bits */ | |
617 | userbuf[22] = 0; | |
618 | userbuf[23] = 0; | |
619 | ||
74e3f6e6 | 620 | /* |
7022672e | 621 | * Write back the zeroed bytes + the image given |
1da177e4 LT |
622 | * the read was destructive. |
623 | */ | |
624 | perf_rdr_write(16, userbuf); | |
625 | } else { | |
626 | ||
627 | /* | |
74e3f6e6 | 628 | * Read RDR-15 which contains the counters and sticky bits |
1da177e4 LT |
629 | */ |
630 | if (!perf_rdr_read_ubuf(15, userbuf)) { | |
631 | return -13; | |
632 | } | |
633 | ||
74e3f6e6 | 634 | /* |
1da177e4 LT |
635 | * Clear out the counters |
636 | */ | |
637 | perf_rdr_clear(15); | |
638 | ||
639 | /* | |
640 | * Copy the counters | |
641 | */ | |
642 | raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL); | |
643 | raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL); | |
644 | raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL); | |
645 | raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL); | |
646 | } | |
74e3f6e6 | 647 | |
1da177e4 LT |
648 | return 0; |
649 | } | |
650 | ||
651 | /* | |
652 | * perf_rdr_get_entry | |
653 | * | |
654 | * Retrieve a pointer to the description of what this | |
655 | * RDR contains. | |
656 | */ | |
cb6fc18e | 657 | static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num) |
1da177e4 LT |
658 | { |
659 | if (perf_processor_interface == ONYX_INTF) { | |
660 | return &perf_rdr_tbl_U[rdr_num]; | |
661 | } else { | |
662 | return &perf_rdr_tbl_W[rdr_num]; | |
663 | } | |
664 | } | |
665 | ||
666 | /* | |
667 | * perf_rdr_read_ubuf | |
668 | * | |
669 | * Read the RDR value into the buffer specified. | |
670 | */ | |
671 | static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer) | |
672 | { | |
673 | uint64_t data, data_mask = 0; | |
674 | uint32_t width, xbits, i; | |
cb6fc18e | 675 | const struct rdr_tbl_ent *tentry; |
1da177e4 LT |
676 | |
677 | tentry = perf_rdr_get_entry(rdr_num); | |
678 | if ((width = tentry->width) == 0) | |
679 | return 0; | |
680 | ||
681 | /* Clear out buffer */ | |
682 | i = tentry->num_words; | |
683 | while (i--) { | |
684 | buffer[i] = 0; | |
74e3f6e6 | 685 | } |
1da177e4 LT |
686 | |
687 | /* Check for bits an even number of 64 */ | |
688 | if ((xbits = width & 0x03f) != 0) { | |
689 | data_mask = 1; | |
690 | data_mask <<= (64 - xbits); | |
691 | data_mask--; | |
692 | } | |
693 | ||
694 | /* Grab all of the data */ | |
695 | i = tentry->num_words; | |
696 | while (i--) { | |
697 | ||
698 | if (perf_processor_interface == ONYX_INTF) { | |
699 | data = perf_rdr_shift_in_U(rdr_num, width); | |
700 | } else { | |
701 | data = perf_rdr_shift_in_W(rdr_num, width); | |
702 | } | |
703 | if (xbits) { | |
704 | buffer[i] |= (data << (64 - xbits)); | |
705 | if (i) { | |
706 | buffer[i-1] |= ((data >> xbits) & data_mask); | |
707 | } | |
708 | } else { | |
709 | buffer[i] = data; | |
710 | } | |
711 | } | |
712 | ||
713 | return 1; | |
714 | } | |
715 | ||
716 | /* | |
717 | * perf_rdr_clear | |
718 | * | |
719 | * Zero out the given RDR register | |
720 | */ | |
721 | static int perf_rdr_clear(uint32_t rdr_num) | |
722 | { | |
cb6fc18e | 723 | const struct rdr_tbl_ent *tentry; |
1da177e4 LT |
724 | int32_t i; |
725 | ||
726 | tentry = perf_rdr_get_entry(rdr_num); | |
727 | ||
728 | if (tentry->width == 0) { | |
729 | return -1; | |
730 | } | |
731 | ||
732 | i = tentry->num_words; | |
733 | while (i--) { | |
734 | if (perf_processor_interface == ONYX_INTF) { | |
735 | perf_rdr_shift_out_U(rdr_num, 0UL); | |
736 | } else { | |
737 | perf_rdr_shift_out_W(rdr_num, 0UL); | |
738 | } | |
739 | } | |
740 | ||
741 | return 0; | |
742 | } | |
743 | ||
744 | ||
745 | /* | |
746 | * perf_write_image | |
747 | * | |
748 | * Write the given image out to the processor | |
749 | */ | |
750 | static int perf_write_image(uint64_t *memaddr) | |
751 | { | |
752 | uint64_t buffer[MAX_RDR_WORDS]; | |
753 | uint64_t *bptr; | |
754 | uint32_t dwords; | |
cb6fc18e HD |
755 | const uint32_t *intrigue_rdr; |
756 | const uint64_t *intrigue_bitmask; | |
757 | uint64_t tmp64; | |
53f01bba | 758 | void __iomem *runway; |
cb6fc18e | 759 | const struct rdr_tbl_ent *tentry; |
1da177e4 LT |
760 | int i; |
761 | ||
762 | /* Clear out counters */ | |
763 | if (perf_processor_interface == ONYX_INTF) { | |
764 | ||
765 | perf_rdr_clear(16); | |
766 | ||
767 | /* Toggle performance monitor */ | |
768 | perf_intrigue_enable_perf_counters(); | |
769 | perf_intrigue_disable_perf_counters(); | |
770 | ||
771 | intrigue_rdr = perf_rdrs_U; | |
772 | } else { | |
773 | perf_rdr_clear(15); | |
774 | intrigue_rdr = perf_rdrs_W; | |
775 | } | |
776 | ||
777 | /* Write all RDRs */ | |
778 | while (*intrigue_rdr != -1) { | |
779 | tentry = perf_rdr_get_entry(*intrigue_rdr); | |
780 | perf_rdr_read_ubuf(*intrigue_rdr, buffer); | |
781 | bptr = &buffer[0]; | |
782 | dwords = tentry->num_words; | |
783 | if (tentry->write_control) { | |
784 | intrigue_bitmask = &bitmask_array[tentry->write_control >> 3]; | |
785 | while (dwords--) { | |
786 | tmp64 = *intrigue_bitmask & *memaddr++; | |
787 | tmp64 |= (~(*intrigue_bitmask++)) & *bptr; | |
788 | *bptr++ = tmp64; | |
789 | } | |
790 | } else { | |
791 | while (dwords--) { | |
792 | *bptr++ = *memaddr++; | |
793 | } | |
794 | } | |
795 | ||
796 | perf_rdr_write(*intrigue_rdr, buffer); | |
797 | intrigue_rdr++; | |
798 | } | |
799 | ||
800 | /* | |
801 | * Now copy out the Runway stuff which is not in RDRs | |
802 | */ | |
803 | ||
804 | if (cpu_device == NULL) | |
805 | { | |
806 | printk(KERN_ERR "write_image: cpu_device not yet initialized!\n"); | |
807 | return -1; | |
808 | } | |
809 | ||
5076c158 | 810 | runway = ioremap_nocache(cpu_device->hpa.start, 4096); |
74e3f6e6 AY |
811 | if (!runway) { |
812 | pr_err("perf_write_image: ioremap failed!\n"); | |
813 | return -ENOMEM; | |
814 | } | |
1da177e4 LT |
815 | |
816 | /* Merge intrigue bits into Runway STATUS 0 */ | |
53f01bba | 817 | tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful; |
74e3f6e6 | 818 | __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul), |
53f01bba | 819 | runway + RUNWAY_STATUS); |
74e3f6e6 | 820 | |
1da177e4 LT |
821 | /* Write RUNWAY DEBUG registers */ |
822 | for (i = 0; i < 8; i++) { | |
53f01bba | 823 | __raw_writeq(*memaddr++, runway + RUNWAY_DEBUG); |
1da177e4 LT |
824 | } |
825 | ||
74e3f6e6 | 826 | return 0; |
1da177e4 LT |
827 | } |
828 | ||
829 | /* | |
830 | * perf_rdr_write | |
831 | * | |
832 | * Write the given RDR register with the contents | |
833 | * of the given buffer. | |
834 | */ | |
835 | static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer) | |
836 | { | |
cb6fc18e | 837 | const struct rdr_tbl_ent *tentry; |
1da177e4 LT |
838 | int32_t i; |
839 | ||
840 | printk("perf_rdr_write\n"); | |
841 | tentry = perf_rdr_get_entry(rdr_num); | |
842 | if (tentry->width == 0) { return; } | |
843 | ||
844 | i = tentry->num_words; | |
845 | while (i--) { | |
846 | if (perf_processor_interface == ONYX_INTF) { | |
847 | perf_rdr_shift_out_U(rdr_num, buffer[i]); | |
848 | } else { | |
849 | perf_rdr_shift_out_W(rdr_num, buffer[i]); | |
74e3f6e6 | 850 | } |
1da177e4 LT |
851 | } |
852 | printk("perf_rdr_write done\n"); | |
853 | } |