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1da177e4 LT |
1 | /* |
2 | * Parisc performance counters | |
3 | * Copyright (C) 2001 Randolph Chung <tausq@debian.org> | |
4 | * | |
5 | * This code is derived, with permission, from HP/UX sources. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2, or (at your option) | |
10 | * any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * Edited comment from original sources: | |
24 | * | |
25 | * This driver programs the PCX-U/PCX-W performance counters | |
26 | * on the PA-RISC 2.0 chips. The driver keeps all images now | |
27 | * internally to the kernel to hopefully eliminate the possiblity | |
28 | * of a bad image halting the CPU. Also, there are different | |
29 | * images for the PCX-W and later chips vs the PCX-U chips. | |
30 | * | |
31 | * Only 1 process is allowed to access the driver at any time, | |
32 | * so the only protection that is needed is at open and close. | |
33 | * A variable "perf_enabled" is used to hold the state of the | |
34 | * driver. The spinlock "perf_lock" is used to protect the | |
35 | * modification of the state during open/close operations so | |
36 | * multiple processes don't get into the driver simultaneously. | |
37 | * | |
38 | * This driver accesses the processor directly vs going through | |
39 | * the PDC INTRIGUE calls. This is done to eliminate bugs introduced | |
40 | * in various PDC revisions. The code is much more maintainable | |
41 | * and reliable this way vs having to debug on every version of PDC | |
42 | * on every box. | |
43 | */ | |
44 | ||
a9415644 | 45 | #include <linux/capability.h> |
1da177e4 LT |
46 | #include <linux/init.h> |
47 | #include <linux/proc_fs.h> | |
48 | #include <linux/miscdevice.h> | |
49 | #include <linux/spinlock.h> | |
50 | ||
51 | #include <asm/uaccess.h> | |
52 | #include <asm/perf.h> | |
53 | #include <asm/parisc-device.h> | |
54 | #include <asm/processor.h> | |
55 | #include <asm/runway.h> | |
56 | #include <asm/io.h> /* for __raw_read() */ | |
57 | ||
58 | #include "perf_images.h" | |
59 | ||
60 | #define MAX_RDR_WORDS 24 | |
61 | #define PERF_VERSION 2 /* derived from hpux's PI v2 interface */ | |
62 | ||
63 | /* definition of RDR regs */ | |
64 | struct rdr_tbl_ent { | |
65 | uint16_t width; | |
66 | uint8_t num_words; | |
67 | uint8_t write_control; | |
68 | }; | |
69 | ||
8039de10 | 70 | static int perf_processor_interface __read_mostly = UNKNOWN_INTF; |
cb6fc18e | 71 | static int perf_enabled __read_mostly; |
1da177e4 | 72 | static spinlock_t perf_lock; |
cb6fc18e | 73 | struct parisc_device *cpu_device __read_mostly; |
1da177e4 LT |
74 | |
75 | /* RDRs to write for PCX-W */ | |
cb6fc18e | 76 | static const int perf_rdrs_W[] = |
1da177e4 LT |
77 | { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 }; |
78 | ||
79 | /* RDRs to write for PCX-U */ | |
cb6fc18e | 80 | static const int perf_rdrs_U[] = |
1da177e4 LT |
81 | { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 }; |
82 | ||
83 | /* RDR register descriptions for PCX-W */ | |
cb6fc18e | 84 | static const struct rdr_tbl_ent perf_rdr_tbl_W[] = { |
1da177e4 LT |
85 | { 19, 1, 8 }, /* RDR 0 */ |
86 | { 16, 1, 16 }, /* RDR 1 */ | |
87 | { 72, 2, 0 }, /* RDR 2 */ | |
88 | { 81, 2, 0 }, /* RDR 3 */ | |
89 | { 328, 6, 0 }, /* RDR 4 */ | |
90 | { 160, 3, 0 }, /* RDR 5 */ | |
91 | { 336, 6, 0 }, /* RDR 6 */ | |
92 | { 164, 3, 0 }, /* RDR 7 */ | |
93 | { 0, 0, 0 }, /* RDR 8 */ | |
94 | { 35, 1, 0 }, /* RDR 9 */ | |
95 | { 6, 1, 0 }, /* RDR 10 */ | |
96 | { 18, 1, 0 }, /* RDR 11 */ | |
97 | { 13, 1, 0 }, /* RDR 12 */ | |
98 | { 8, 1, 0 }, /* RDR 13 */ | |
99 | { 8, 1, 0 }, /* RDR 14 */ | |
100 | { 8, 1, 0 }, /* RDR 15 */ | |
101 | { 1530, 24, 0 }, /* RDR 16 */ | |
102 | { 16, 1, 0 }, /* RDR 17 */ | |
103 | { 4, 1, 0 }, /* RDR 18 */ | |
104 | { 0, 0, 0 }, /* RDR 19 */ | |
105 | { 152, 3, 24 }, /* RDR 20 */ | |
106 | { 152, 3, 24 }, /* RDR 21 */ | |
107 | { 233, 4, 48 }, /* RDR 22 */ | |
108 | { 233, 4, 48 }, /* RDR 23 */ | |
109 | { 71, 2, 0 }, /* RDR 24 */ | |
110 | { 71, 2, 0 }, /* RDR 25 */ | |
111 | { 11, 1, 0 }, /* RDR 26 */ | |
112 | { 18, 1, 0 }, /* RDR 27 */ | |
113 | { 128, 2, 0 }, /* RDR 28 */ | |
114 | { 0, 0, 0 }, /* RDR 29 */ | |
115 | { 16, 1, 0 }, /* RDR 30 */ | |
116 | { 16, 1, 0 }, /* RDR 31 */ | |
117 | }; | |
118 | ||
119 | /* RDR register descriptions for PCX-U */ | |
cb6fc18e | 120 | static const struct rdr_tbl_ent perf_rdr_tbl_U[] = { |
1da177e4 LT |
121 | { 19, 1, 8 }, /* RDR 0 */ |
122 | { 32, 1, 16 }, /* RDR 1 */ | |
123 | { 20, 1, 0 }, /* RDR 2 */ | |
124 | { 0, 0, 0 }, /* RDR 3 */ | |
125 | { 344, 6, 0 }, /* RDR 4 */ | |
126 | { 176, 3, 0 }, /* RDR 5 */ | |
127 | { 336, 6, 0 }, /* RDR 6 */ | |
128 | { 0, 0, 0 }, /* RDR 7 */ | |
129 | { 0, 0, 0 }, /* RDR 8 */ | |
130 | { 0, 0, 0 }, /* RDR 9 */ | |
131 | { 28, 1, 0 }, /* RDR 10 */ | |
132 | { 33, 1, 0 }, /* RDR 11 */ | |
133 | { 0, 0, 0 }, /* RDR 12 */ | |
134 | { 230, 4, 0 }, /* RDR 13 */ | |
135 | { 32, 1, 0 }, /* RDR 14 */ | |
136 | { 128, 2, 0 }, /* RDR 15 */ | |
137 | { 1494, 24, 0 }, /* RDR 16 */ | |
138 | { 18, 1, 0 }, /* RDR 17 */ | |
139 | { 4, 1, 0 }, /* RDR 18 */ | |
140 | { 0, 0, 0 }, /* RDR 19 */ | |
141 | { 158, 3, 24 }, /* RDR 20 */ | |
142 | { 158, 3, 24 }, /* RDR 21 */ | |
143 | { 194, 4, 48 }, /* RDR 22 */ | |
144 | { 194, 4, 48 }, /* RDR 23 */ | |
145 | { 71, 2, 0 }, /* RDR 24 */ | |
146 | { 71, 2, 0 }, /* RDR 25 */ | |
147 | { 28, 1, 0 }, /* RDR 26 */ | |
148 | { 33, 1, 0 }, /* RDR 27 */ | |
149 | { 88, 2, 0 }, /* RDR 28 */ | |
150 | { 32, 1, 0 }, /* RDR 29 */ | |
151 | { 24, 1, 0 }, /* RDR 30 */ | |
152 | { 16, 1, 0 }, /* RDR 31 */ | |
153 | }; | |
154 | ||
155 | /* | |
156 | * A non-zero write_control in the above tables is a byte offset into | |
157 | * this array. | |
158 | */ | |
cb6fc18e | 159 | static const uint64_t perf_bitmasks[] = { |
1da177e4 LT |
160 | 0x0000000000000000ul, /* first dbl word must be zero */ |
161 | 0xfdffe00000000000ul, /* RDR0 bitmask */ | |
162 | 0x003f000000000000ul, /* RDR1 bitmask */ | |
163 | 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */ | |
164 | 0xfffffffffffffffful, | |
165 | 0xfffffffc00000000ul, | |
166 | 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */ | |
167 | 0xfffffffffffffffful, | |
168 | 0xfffffffffffffffcul, | |
169 | 0xff00000000000000ul | |
170 | }; | |
171 | ||
172 | /* | |
173 | * Write control bitmasks for Pa-8700 processor given | |
174 | * somethings have changed slightly. | |
175 | */ | |
cb6fc18e | 176 | static const uint64_t perf_bitmasks_piranha[] = { |
1da177e4 LT |
177 | 0x0000000000000000ul, /* first dbl word must be zero */ |
178 | 0xfdffe00000000000ul, /* RDR0 bitmask */ | |
179 | 0x003f000000000000ul, /* RDR1 bitmask */ | |
180 | 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */ | |
181 | 0xfffffffffffffffful, | |
182 | 0xfffffffc00000000ul, | |
183 | 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */ | |
184 | 0xfffffffffffffffful, | |
185 | 0xfffffffffffffffful, | |
186 | 0xfffc000000000000ul | |
187 | }; | |
188 | ||
cb6fc18e | 189 | static const uint64_t *bitmask_array; /* array of bitmasks to use */ |
1da177e4 LT |
190 | |
191 | /****************************************************************************** | |
192 | * Function Prototypes | |
193 | *****************************************************************************/ | |
194 | static int perf_config(uint32_t *image_ptr); | |
195 | static int perf_release(struct inode *inode, struct file *file); | |
196 | static int perf_open(struct inode *inode, struct file *file); | |
197 | static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos); | |
198 | static ssize_t perf_write(struct file *file, const char __user *buf, size_t count, | |
199 | loff_t *ppos); | |
ad7dd338 | 200 | static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg); |
1da177e4 LT |
201 | static void perf_start_counters(void); |
202 | static int perf_stop_counters(uint32_t *raddr); | |
cb6fc18e | 203 | static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num); |
1da177e4 LT |
204 | static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer); |
205 | static int perf_rdr_clear(uint32_t rdr_num); | |
206 | static int perf_write_image(uint64_t *memaddr); | |
207 | static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer); | |
208 | ||
209 | /* External Assembly Routines */ | |
210 | extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width); | |
211 | extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width); | |
212 | extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer); | |
213 | extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer); | |
214 | extern void perf_intrigue_enable_perf_counters (void); | |
215 | extern void perf_intrigue_disable_perf_counters (void); | |
216 | ||
217 | /****************************************************************************** | |
218 | * Function Definitions | |
219 | *****************************************************************************/ | |
220 | ||
221 | ||
222 | /* | |
223 | * configure: | |
224 | * | |
225 | * Configure the cpu with a given data image. First turn off the counters, | |
226 | * then download the image, then turn the counters back on. | |
227 | */ | |
228 | static int perf_config(uint32_t *image_ptr) | |
229 | { | |
230 | long error; | |
231 | uint32_t raddr[4]; | |
232 | ||
233 | /* Stop the counters*/ | |
234 | error = perf_stop_counters(raddr); | |
235 | if (error != 0) { | |
236 | printk("perf_config: perf_stop_counters = %ld\n", error); | |
237 | return -EINVAL; | |
238 | } | |
239 | ||
240 | printk("Preparing to write image\n"); | |
241 | /* Write the image to the chip */ | |
242 | error = perf_write_image((uint64_t *)image_ptr); | |
243 | if (error != 0) { | |
244 | printk("perf_config: DOWNLOAD = %ld\n", error); | |
245 | return -EINVAL; | |
246 | } | |
247 | ||
248 | printk("Preparing to start counters\n"); | |
249 | ||
250 | /* Start the counters */ | |
251 | perf_start_counters(); | |
252 | ||
253 | return sizeof(uint32_t); | |
254 | } | |
255 | ||
256 | /* | |
257 | * Open the device and initialize all of its memory. The device is only | |
258 | * opened once, but can be "queried" by multiple processes that know its | |
259 | * file descriptor. | |
260 | */ | |
261 | static int perf_open(struct inode *inode, struct file *file) | |
262 | { | |
263 | spin_lock(&perf_lock); | |
264 | if (perf_enabled) { | |
265 | spin_unlock(&perf_lock); | |
266 | return -EBUSY; | |
267 | } | |
268 | perf_enabled = 1; | |
269 | spin_unlock(&perf_lock); | |
270 | ||
271 | return 0; | |
272 | } | |
273 | ||
274 | /* | |
275 | * Close the device. | |
276 | */ | |
277 | static int perf_release(struct inode *inode, struct file *file) | |
278 | { | |
279 | spin_lock(&perf_lock); | |
280 | perf_enabled = 0; | |
281 | spin_unlock(&perf_lock); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | /* | |
287 | * Read does nothing for this driver | |
288 | */ | |
289 | static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos) | |
290 | { | |
291 | return 0; | |
292 | } | |
293 | ||
294 | /* | |
295 | * write: | |
296 | * | |
297 | * This routine downloads the image to the chip. It must be | |
298 | * called on the processor that the download should happen | |
299 | * on. | |
300 | */ | |
301 | static ssize_t perf_write(struct file *file, const char __user *buf, size_t count, | |
302 | loff_t *ppos) | |
303 | { | |
304 | int err; | |
305 | size_t image_size; | |
306 | uint32_t image_type; | |
307 | uint32_t interface_type; | |
308 | uint32_t test; | |
309 | ||
310 | if (perf_processor_interface == ONYX_INTF) | |
311 | image_size = PCXU_IMAGE_SIZE; | |
312 | else if (perf_processor_interface == CUDA_INTF) | |
313 | image_size = PCXW_IMAGE_SIZE; | |
314 | else | |
315 | return -EFAULT; | |
316 | ||
317 | if (!capable(CAP_SYS_ADMIN)) | |
318 | return -EACCES; | |
319 | ||
320 | if (count != sizeof(uint32_t)) | |
321 | return -EIO; | |
322 | ||
323 | if ((err = copy_from_user(&image_type, buf, sizeof(uint32_t))) != 0) | |
324 | return err; | |
325 | ||
326 | /* Get the interface type and test type */ | |
327 | interface_type = (image_type >> 16) & 0xffff; | |
328 | test = (image_type & 0xffff); | |
329 | ||
330 | /* Make sure everything makes sense */ | |
331 | ||
332 | /* First check the machine type is correct for | |
333 | the requested image */ | |
334 | if (((perf_processor_interface == CUDA_INTF) && | |
335 | (interface_type != CUDA_INTF)) || | |
336 | ((perf_processor_interface == ONYX_INTF) && | |
337 | (interface_type != ONYX_INTF))) | |
338 | return -EINVAL; | |
339 | ||
340 | /* Next check to make sure the requested image | |
341 | is valid */ | |
342 | if (((interface_type == CUDA_INTF) && | |
343 | (test >= MAX_CUDA_IMAGES)) || | |
344 | ((interface_type == ONYX_INTF) && | |
345 | (test >= MAX_ONYX_IMAGES))) | |
346 | return -EINVAL; | |
347 | ||
348 | /* Copy the image into the processor */ | |
349 | if (interface_type == CUDA_INTF) | |
350 | return perf_config(cuda_images[test]); | |
351 | else | |
352 | return perf_config(onyx_images[test]); | |
353 | ||
354 | return count; | |
355 | } | |
356 | ||
357 | /* | |
358 | * Patch the images that need to know the IVA addresses. | |
359 | */ | |
360 | static void perf_patch_images(void) | |
361 | { | |
362 | #if 0 /* FIXME!! */ | |
363 | /* | |
364 | * NOTE: this routine is VERY specific to the current TLB image. | |
365 | * If the image is changed, this routine might also need to be changed. | |
366 | */ | |
367 | extern void $i_itlb_miss_2_0(); | |
368 | extern void $i_dtlb_miss_2_0(); | |
369 | extern void PA2_0_iva(); | |
370 | ||
371 | /* | |
372 | * We can only use the lower 32-bits, the upper 32-bits should be 0 | |
373 | * anyway given this is in the kernel | |
374 | */ | |
375 | uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0); | |
376 | uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0); | |
377 | uint32_t IVAaddress = (uint32_t)&PA2_0_iva; | |
378 | ||
379 | if (perf_processor_interface == ONYX_INTF) { | |
380 | /* clear last 2 bytes */ | |
381 | onyx_images[TLBMISS][15] &= 0xffffff00; | |
382 | /* set 2 bytes */ | |
383 | onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); | |
384 | onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00; | |
385 | onyx_images[TLBMISS][17] = itlb_addr; | |
386 | ||
387 | /* clear last 2 bytes */ | |
388 | onyx_images[TLBHANDMISS][15] &= 0xffffff00; | |
389 | /* set 2 bytes */ | |
390 | onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); | |
391 | onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00; | |
392 | onyx_images[TLBHANDMISS][17] = itlb_addr; | |
393 | ||
394 | /* clear last 2 bytes */ | |
395 | onyx_images[BIG_CPI][15] &= 0xffffff00; | |
396 | /* set 2 bytes */ | |
397 | onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24)); | |
398 | onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00; | |
399 | onyx_images[BIG_CPI][17] = itlb_addr; | |
400 | ||
401 | onyx_images[PANIC][15] &= 0xffffff00; /* clear last 2 bytes */ | |
402 | onyx_images[PANIC][15] |= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */ | |
403 | onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00; | |
404 | ||
405 | ||
406 | } else if (perf_processor_interface == CUDA_INTF) { | |
407 | /* Cuda interface */ | |
408 | cuda_images[TLBMISS][16] = | |
409 | (cuda_images[TLBMISS][16]&0xffff0000) | | |
410 | ((dtlb_addr >> 8)&0x0000ffff); | |
411 | cuda_images[TLBMISS][17] = | |
412 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); | |
413 | cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000; | |
414 | ||
415 | cuda_images[TLBHANDMISS][16] = | |
416 | (cuda_images[TLBHANDMISS][16]&0xffff0000) | | |
417 | ((dtlb_addr >> 8)&0x0000ffff); | |
418 | cuda_images[TLBHANDMISS][17] = | |
419 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); | |
420 | cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000; | |
421 | ||
422 | cuda_images[BIG_CPI][16] = | |
423 | (cuda_images[BIG_CPI][16]&0xffff0000) | | |
424 | ((dtlb_addr >> 8)&0x0000ffff); | |
425 | cuda_images[BIG_CPI][17] = | |
426 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); | |
427 | cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000; | |
428 | } else { | |
429 | /* Unknown type */ | |
430 | } | |
431 | #endif | |
432 | } | |
433 | ||
434 | ||
435 | /* | |
436 | * ioctl routine | |
437 | * All routines effect the processor that they are executed on. Thus you | |
438 | * must be running on the processor that you wish to change. | |
439 | */ | |
440 | ||
ad7dd338 | 441 | static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
442 | { |
443 | long error_start; | |
ad7dd338 CH |
444 | uint32_t raddr[4]; |
445 | int error = 0; | |
1da177e4 LT |
446 | |
447 | switch (cmd) { | |
448 | ||
449 | case PA_PERF_ON: | |
450 | /* Start the counters */ | |
451 | perf_start_counters(); | |
ad7dd338 | 452 | break; |
1da177e4 LT |
453 | |
454 | case PA_PERF_OFF: | |
455 | error_start = perf_stop_counters(raddr); | |
456 | if (error_start != 0) { | |
457 | printk(KERN_ERR "perf_off: perf_stop_counters = %ld\n", error_start); | |
ad7dd338 CH |
458 | error = -EFAULT; |
459 | break; | |
1da177e4 LT |
460 | } |
461 | ||
462 | /* copy out the Counters */ | |
463 | if (copy_to_user((void __user *)arg, raddr, | |
464 | sizeof (raddr)) != 0) { | |
ad7dd338 CH |
465 | error = -EFAULT; |
466 | break; | |
1da177e4 | 467 | } |
ad7dd338 | 468 | break; |
1da177e4 LT |
469 | |
470 | case PA_PERF_VERSION: | |
471 | /* Return the version # */ | |
ad7dd338 CH |
472 | error = put_user(PERF_VERSION, (int *)arg); |
473 | break; | |
1da177e4 LT |
474 | |
475 | default: | |
ad7dd338 | 476 | error = -ENOTTY; |
1da177e4 | 477 | } |
ad7dd338 | 478 | |
ad7dd338 | 479 | return error; |
1da177e4 LT |
480 | } |
481 | ||
482 | static struct file_operations perf_fops = { | |
483 | .llseek = no_llseek, | |
484 | .read = perf_read, | |
485 | .write = perf_write, | |
ad7dd338 CH |
486 | .unlocked_ioctl = perf_ioctl, |
487 | .compat_ioctl = perf_ioctl, | |
1da177e4 LT |
488 | .open = perf_open, |
489 | .release = perf_release | |
490 | }; | |
491 | ||
492 | static struct miscdevice perf_dev = { | |
493 | MISC_DYNAMIC_MINOR, | |
494 | PA_PERF_DEV, | |
495 | &perf_fops | |
496 | }; | |
497 | ||
498 | /* | |
499 | * Initialize the module | |
500 | */ | |
501 | static int __init perf_init(void) | |
502 | { | |
503 | int ret; | |
504 | ||
505 | /* Determine correct processor interface to use */ | |
506 | bitmask_array = perf_bitmasks; | |
507 | ||
508 | if (boot_cpu_data.cpu_type == pcxu || | |
509 | boot_cpu_data.cpu_type == pcxu_) { | |
510 | perf_processor_interface = ONYX_INTF; | |
511 | } else if (boot_cpu_data.cpu_type == pcxw || | |
512 | boot_cpu_data.cpu_type == pcxw_ || | |
513 | boot_cpu_data.cpu_type == pcxw2 || | |
514 | boot_cpu_data.cpu_type == mako) { | |
515 | perf_processor_interface = CUDA_INTF; | |
516 | if (boot_cpu_data.cpu_type == pcxw2 || | |
517 | boot_cpu_data.cpu_type == mako) | |
518 | bitmask_array = perf_bitmasks_piranha; | |
519 | } else { | |
520 | perf_processor_interface = UNKNOWN_INTF; | |
521 | printk("Performance monitoring counters not supported on this processor\n"); | |
522 | return -ENODEV; | |
523 | } | |
524 | ||
525 | ret = misc_register(&perf_dev); | |
526 | if (ret) { | |
527 | printk(KERN_ERR "Performance monitoring counters: " | |
528 | "cannot register misc device.\n"); | |
529 | return ret; | |
530 | } | |
531 | ||
532 | /* Patch the images to match the system */ | |
533 | perf_patch_images(); | |
534 | ||
535 | spin_lock_init(&perf_lock); | |
536 | ||
537 | /* TODO: this only lets us access the first cpu.. what to do for SMP? */ | |
538 | cpu_device = cpu_data[0].dev; | |
539 | printk("Performance monitoring counters enabled for %s\n", | |
540 | cpu_data[0].dev->name); | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
545 | /* | |
546 | * perf_start_counters(void) | |
547 | * | |
548 | * Start the counters. | |
549 | */ | |
550 | static void perf_start_counters(void) | |
551 | { | |
552 | /* Enable performance monitor counters */ | |
553 | perf_intrigue_enable_perf_counters(); | |
554 | } | |
555 | ||
556 | /* | |
557 | * perf_stop_counters | |
558 | * | |
559 | * Stop the performance counters and save counts | |
560 | * in a per_processor array. | |
561 | */ | |
562 | static int perf_stop_counters(uint32_t *raddr) | |
563 | { | |
564 | uint64_t userbuf[MAX_RDR_WORDS]; | |
565 | ||
566 | /* Disable performance counters */ | |
567 | perf_intrigue_disable_perf_counters(); | |
568 | ||
569 | if (perf_processor_interface == ONYX_INTF) { | |
570 | uint64_t tmp64; | |
571 | /* | |
572 | * Read the counters | |
573 | */ | |
574 | if (!perf_rdr_read_ubuf(16, userbuf)) | |
575 | return -13; | |
576 | ||
577 | /* Counter0 is bits 1398 thru 1429 */ | |
578 | tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000; | |
579 | tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff; | |
580 | /* OR sticky0 (bit 1430) to counter0 bit 32 */ | |
581 | tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000; | |
582 | raddr[0] = (uint32_t)tmp64; | |
583 | ||
584 | /* Counter1 is bits 1431 thru 1462 */ | |
585 | tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff; | |
586 | /* OR sticky1 (bit 1463) to counter1 bit 32 */ | |
587 | tmp64 |= (userbuf[22] << 23) & 0x0000000080000000; | |
588 | raddr[1] = (uint32_t)tmp64; | |
589 | ||
590 | /* Counter2 is bits 1464 thru 1495 */ | |
591 | tmp64 = (userbuf[22] << 24) & 0x00000000ff000000; | |
592 | tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff; | |
593 | /* OR sticky2 (bit 1496) to counter2 bit 32 */ | |
594 | tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000; | |
595 | raddr[2] = (uint32_t)tmp64; | |
596 | ||
597 | /* Counter3 is bits 1497 thru 1528 */ | |
598 | tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff; | |
599 | /* OR sticky3 (bit 1529) to counter3 bit 32 */ | |
600 | tmp64 |= (userbuf[23] << 25) & 0x0000000080000000; | |
601 | raddr[3] = (uint32_t)tmp64; | |
602 | ||
603 | /* | |
604 | * Zero out the counters | |
605 | */ | |
606 | ||
607 | /* | |
608 | * The counters and sticky-bits comprise the last 132 bits | |
609 | * (1398 - 1529) of RDR16 on a U chip. We'll zero these | |
610 | * out the easy way: zero out last 10 bits of dword 21, | |
611 | * all of dword 22 and 58 bits (plus 6 don't care bits) of | |
612 | * dword 23. | |
613 | */ | |
614 | userbuf[21] &= 0xfffffffffffffc00ul; /* 0 to last 10 bits */ | |
615 | userbuf[22] = 0; | |
616 | userbuf[23] = 0; | |
617 | ||
618 | /* | |
619 | * Write back the zero'ed bytes + the image given | |
620 | * the read was destructive. | |
621 | */ | |
622 | perf_rdr_write(16, userbuf); | |
623 | } else { | |
624 | ||
625 | /* | |
626 | * Read RDR-15 which contains the counters and sticky bits | |
627 | */ | |
628 | if (!perf_rdr_read_ubuf(15, userbuf)) { | |
629 | return -13; | |
630 | } | |
631 | ||
632 | /* | |
633 | * Clear out the counters | |
634 | */ | |
635 | perf_rdr_clear(15); | |
636 | ||
637 | /* | |
638 | * Copy the counters | |
639 | */ | |
640 | raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL); | |
641 | raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL); | |
642 | raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL); | |
643 | raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL); | |
644 | } | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
649 | /* | |
650 | * perf_rdr_get_entry | |
651 | * | |
652 | * Retrieve a pointer to the description of what this | |
653 | * RDR contains. | |
654 | */ | |
cb6fc18e | 655 | static const struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num) |
1da177e4 LT |
656 | { |
657 | if (perf_processor_interface == ONYX_INTF) { | |
658 | return &perf_rdr_tbl_U[rdr_num]; | |
659 | } else { | |
660 | return &perf_rdr_tbl_W[rdr_num]; | |
661 | } | |
662 | } | |
663 | ||
664 | /* | |
665 | * perf_rdr_read_ubuf | |
666 | * | |
667 | * Read the RDR value into the buffer specified. | |
668 | */ | |
669 | static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer) | |
670 | { | |
671 | uint64_t data, data_mask = 0; | |
672 | uint32_t width, xbits, i; | |
cb6fc18e | 673 | const struct rdr_tbl_ent *tentry; |
1da177e4 LT |
674 | |
675 | tentry = perf_rdr_get_entry(rdr_num); | |
676 | if ((width = tentry->width) == 0) | |
677 | return 0; | |
678 | ||
679 | /* Clear out buffer */ | |
680 | i = tentry->num_words; | |
681 | while (i--) { | |
682 | buffer[i] = 0; | |
683 | } | |
684 | ||
685 | /* Check for bits an even number of 64 */ | |
686 | if ((xbits = width & 0x03f) != 0) { | |
687 | data_mask = 1; | |
688 | data_mask <<= (64 - xbits); | |
689 | data_mask--; | |
690 | } | |
691 | ||
692 | /* Grab all of the data */ | |
693 | i = tentry->num_words; | |
694 | while (i--) { | |
695 | ||
696 | if (perf_processor_interface == ONYX_INTF) { | |
697 | data = perf_rdr_shift_in_U(rdr_num, width); | |
698 | } else { | |
699 | data = perf_rdr_shift_in_W(rdr_num, width); | |
700 | } | |
701 | if (xbits) { | |
702 | buffer[i] |= (data << (64 - xbits)); | |
703 | if (i) { | |
704 | buffer[i-1] |= ((data >> xbits) & data_mask); | |
705 | } | |
706 | } else { | |
707 | buffer[i] = data; | |
708 | } | |
709 | } | |
710 | ||
711 | return 1; | |
712 | } | |
713 | ||
714 | /* | |
715 | * perf_rdr_clear | |
716 | * | |
717 | * Zero out the given RDR register | |
718 | */ | |
719 | static int perf_rdr_clear(uint32_t rdr_num) | |
720 | { | |
cb6fc18e | 721 | const struct rdr_tbl_ent *tentry; |
1da177e4 LT |
722 | int32_t i; |
723 | ||
724 | tentry = perf_rdr_get_entry(rdr_num); | |
725 | ||
726 | if (tentry->width == 0) { | |
727 | return -1; | |
728 | } | |
729 | ||
730 | i = tentry->num_words; | |
731 | while (i--) { | |
732 | if (perf_processor_interface == ONYX_INTF) { | |
733 | perf_rdr_shift_out_U(rdr_num, 0UL); | |
734 | } else { | |
735 | perf_rdr_shift_out_W(rdr_num, 0UL); | |
736 | } | |
737 | } | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
742 | ||
743 | /* | |
744 | * perf_write_image | |
745 | * | |
746 | * Write the given image out to the processor | |
747 | */ | |
748 | static int perf_write_image(uint64_t *memaddr) | |
749 | { | |
750 | uint64_t buffer[MAX_RDR_WORDS]; | |
751 | uint64_t *bptr; | |
752 | uint32_t dwords; | |
cb6fc18e HD |
753 | const uint32_t *intrigue_rdr; |
754 | const uint64_t *intrigue_bitmask; | |
755 | uint64_t tmp64; | |
53f01bba | 756 | void __iomem *runway; |
cb6fc18e | 757 | const struct rdr_tbl_ent *tentry; |
1da177e4 LT |
758 | int i; |
759 | ||
760 | /* Clear out counters */ | |
761 | if (perf_processor_interface == ONYX_INTF) { | |
762 | ||
763 | perf_rdr_clear(16); | |
764 | ||
765 | /* Toggle performance monitor */ | |
766 | perf_intrigue_enable_perf_counters(); | |
767 | perf_intrigue_disable_perf_counters(); | |
768 | ||
769 | intrigue_rdr = perf_rdrs_U; | |
770 | } else { | |
771 | perf_rdr_clear(15); | |
772 | intrigue_rdr = perf_rdrs_W; | |
773 | } | |
774 | ||
775 | /* Write all RDRs */ | |
776 | while (*intrigue_rdr != -1) { | |
777 | tentry = perf_rdr_get_entry(*intrigue_rdr); | |
778 | perf_rdr_read_ubuf(*intrigue_rdr, buffer); | |
779 | bptr = &buffer[0]; | |
780 | dwords = tentry->num_words; | |
781 | if (tentry->write_control) { | |
782 | intrigue_bitmask = &bitmask_array[tentry->write_control >> 3]; | |
783 | while (dwords--) { | |
784 | tmp64 = *intrigue_bitmask & *memaddr++; | |
785 | tmp64 |= (~(*intrigue_bitmask++)) & *bptr; | |
786 | *bptr++ = tmp64; | |
787 | } | |
788 | } else { | |
789 | while (dwords--) { | |
790 | *bptr++ = *memaddr++; | |
791 | } | |
792 | } | |
793 | ||
794 | perf_rdr_write(*intrigue_rdr, buffer); | |
795 | intrigue_rdr++; | |
796 | } | |
797 | ||
798 | /* | |
799 | * Now copy out the Runway stuff which is not in RDRs | |
800 | */ | |
801 | ||
802 | if (cpu_device == NULL) | |
803 | { | |
804 | printk(KERN_ERR "write_image: cpu_device not yet initialized!\n"); | |
805 | return -1; | |
806 | } | |
807 | ||
53f01bba | 808 | runway = ioremap(cpu_device->hpa.start, 4096); |
1da177e4 LT |
809 | |
810 | /* Merge intrigue bits into Runway STATUS 0 */ | |
53f01bba MW |
811 | tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful; |
812 | __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul), | |
813 | runway + RUNWAY_STATUS); | |
1da177e4 LT |
814 | |
815 | /* Write RUNWAY DEBUG registers */ | |
816 | for (i = 0; i < 8; i++) { | |
53f01bba | 817 | __raw_writeq(*memaddr++, runway + RUNWAY_DEBUG); |
1da177e4 LT |
818 | } |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
823 | /* | |
824 | * perf_rdr_write | |
825 | * | |
826 | * Write the given RDR register with the contents | |
827 | * of the given buffer. | |
828 | */ | |
829 | static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer) | |
830 | { | |
cb6fc18e | 831 | const struct rdr_tbl_ent *tentry; |
1da177e4 LT |
832 | int32_t i; |
833 | ||
834 | printk("perf_rdr_write\n"); | |
835 | tentry = perf_rdr_get_entry(rdr_num); | |
836 | if (tentry->width == 0) { return; } | |
837 | ||
838 | i = tentry->num_words; | |
839 | while (i--) { | |
840 | if (perf_processor_interface == ONYX_INTF) { | |
841 | perf_rdr_shift_out_U(rdr_num, buffer[i]); | |
842 | } else { | |
843 | perf_rdr_shift_out_W(rdr_num, buffer[i]); | |
844 | } | |
845 | } | |
846 | printk("perf_rdr_write done\n"); | |
847 | } | |
848 | ||
849 | module_init(perf_init); |