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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | ** SMP Support | |
3 | ** | |
4 | ** Copyright (C) 1999 Walt Drummond <drummond@valinux.com> | |
5 | ** Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com> | |
6 | ** Copyright (C) 2001,2004 Grant Grundler <grundler@parisc-linux.org> | |
7 | ** | |
8 | ** Lots of stuff stolen from arch/alpha/kernel/smp.c | |
9 | ** ...and then parisc stole from arch/ia64/kernel/smp.c. Thanks David! :^) | |
10 | ** | |
7022672e | 11 | ** Thanks to John Curry and Ullas Ponnadi. I learned a lot from their work. |
1da177e4 LT |
12 | ** -grant (1/12/2001) |
13 | ** | |
14 | ** This program is free software; you can redistribute it and/or modify | |
15 | ** it under the terms of the GNU General Public License as published by | |
16 | ** the Free Software Foundation; either version 2 of the License, or | |
17 | ** (at your option) any later version. | |
18 | */ | |
1da177e4 LT |
19 | #include <linux/types.h> |
20 | #include <linux/spinlock.h> | |
1da177e4 LT |
21 | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/smp.h> | |
28 | #include <linux/kernel_stat.h> | |
29 | #include <linux/mm.h> | |
4e950f6f | 30 | #include <linux/err.h> |
1da177e4 LT |
31 | #include <linux/delay.h> |
32 | #include <linux/bitops.h> | |
d75f054a | 33 | #include <linux/ftrace.h> |
1da177e4 LT |
34 | |
35 | #include <asm/system.h> | |
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 LT |
37 | #include <asm/current.h> |
38 | #include <asm/delay.h> | |
1b2425e3 | 39 | #include <asm/tlbflush.h> |
1da177e4 LT |
40 | |
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> /* for CPU_IRQ_REGION and friends */ | |
43 | #include <asm/mmu_context.h> | |
44 | #include <asm/page.h> | |
45 | #include <asm/pgtable.h> | |
46 | #include <asm/pgalloc.h> | |
47 | #include <asm/processor.h> | |
48 | #include <asm/ptrace.h> | |
49 | #include <asm/unistd.h> | |
50 | #include <asm/cacheflush.h> | |
51 | ||
5492a0f0 KM |
52 | #undef DEBUG_SMP |
53 | #ifdef DEBUG_SMP | |
54 | static int smp_debug_lvl = 0; | |
55 | #define smp_debug(lvl, printargs...) \ | |
56 | if (lvl >= smp_debug_lvl) \ | |
57 | printk(printargs); | |
58 | #else | |
ef017beb | 59 | #define smp_debug(lvl, ...) do { } while(0) |
5492a0f0 | 60 | #endif /* DEBUG_SMP */ |
1da177e4 | 61 | |
1da177e4 LT |
62 | volatile struct task_struct *smp_init_current_idle_task; |
63 | ||
ef017beb HD |
64 | /* track which CPU is booting */ |
65 | static volatile int cpu_now_booting __cpuinitdata; | |
1da177e4 | 66 | |
ef017beb | 67 | static int parisc_max_cpus __cpuinitdata = 1; |
1da177e4 | 68 | |
6ad6c424 | 69 | static DEFINE_PER_CPU(spinlock_t, ipi_lock); |
1da177e4 | 70 | |
1da177e4 LT |
71 | enum ipi_message_type { |
72 | IPI_NOP=0, | |
73 | IPI_RESCHEDULE=1, | |
74 | IPI_CALL_FUNC, | |
dbcf4787 | 75 | IPI_CALL_FUNC_SINGLE, |
1da177e4 LT |
76 | IPI_CPU_START, |
77 | IPI_CPU_STOP, | |
78 | IPI_CPU_TEST | |
79 | }; | |
80 | ||
81 | ||
82 | /********** SMP inter processor interrupt and communication routines */ | |
83 | ||
84 | #undef PER_CPU_IRQ_REGION | |
85 | #ifdef PER_CPU_IRQ_REGION | |
86 | /* XXX REVISIT Ignore for now. | |
87 | ** *May* need this "hook" to register IPI handler | |
88 | ** once we have perCPU ExtIntr switch tables. | |
89 | */ | |
90 | static void | |
91 | ipi_init(int cpuid) | |
92 | { | |
1da177e4 LT |
93 | #error verify IRQ_OFFSET(IPI_IRQ) is ipi_interrupt() in new IRQ region |
94 | ||
95 | if(cpu_online(cpuid) ) | |
96 | { | |
97 | switch_to_idle_task(current); | |
98 | } | |
99 | ||
100 | return; | |
101 | } | |
102 | #endif | |
103 | ||
104 | ||
105 | /* | |
106 | ** Yoink this CPU from the runnable list... | |
107 | ** | |
108 | */ | |
109 | static void | |
110 | halt_processor(void) | |
111 | { | |
1da177e4 LT |
112 | /* REVISIT : redirect I/O Interrupts to another CPU? */ |
113 | /* REVISIT : does PM *know* this CPU isn't available? */ | |
9bc181d8 | 114 | set_cpu_online(smp_processor_id(), false); |
1da177e4 LT |
115 | local_irq_disable(); |
116 | for (;;) | |
117 | ; | |
1da177e4 LT |
118 | } |
119 | ||
120 | ||
d75f054a | 121 | irqreturn_t __irq_entry |
c7753f18 | 122 | ipi_interrupt(int irq, void *dev_id) |
1da177e4 LT |
123 | { |
124 | int this_cpu = smp_processor_id(); | |
ef017beb | 125 | struct cpuinfo_parisc *p = &per_cpu(cpu_data, this_cpu); |
1da177e4 LT |
126 | unsigned long ops; |
127 | unsigned long flags; | |
128 | ||
129 | /* Count this now; we may make a call that never returns. */ | |
130 | p->ipi_count++; | |
131 | ||
132 | mb(); /* Order interrupt and bit testing. */ | |
133 | ||
134 | for (;;) { | |
3c97b5e9 KM |
135 | spinlock_t *lock = &per_cpu(ipi_lock, this_cpu); |
136 | spin_lock_irqsave(lock, flags); | |
1da177e4 LT |
137 | ops = p->pending_ipi; |
138 | p->pending_ipi = 0; | |
3c97b5e9 | 139 | spin_unlock_irqrestore(lock, flags); |
1da177e4 LT |
140 | |
141 | mb(); /* Order bit clearing and data access. */ | |
142 | ||
143 | if (!ops) | |
144 | break; | |
145 | ||
146 | while (ops) { | |
147 | unsigned long which = ffz(~ops); | |
148 | ||
d911aed8 JB |
149 | ops &= ~(1 << which); |
150 | ||
1da177e4 | 151 | switch (which) { |
d911aed8 | 152 | case IPI_NOP: |
5492a0f0 | 153 | smp_debug(100, KERN_DEBUG "CPU%d IPI_NOP\n", this_cpu); |
d911aed8 JB |
154 | break; |
155 | ||
1da177e4 | 156 | case IPI_RESCHEDULE: |
5492a0f0 | 157 | smp_debug(100, KERN_DEBUG "CPU%d IPI_RESCHEDULE\n", this_cpu); |
184748cc | 158 | scheduler_ipi(); |
1da177e4 LT |
159 | break; |
160 | ||
161 | case IPI_CALL_FUNC: | |
5492a0f0 | 162 | smp_debug(100, KERN_DEBUG "CPU%d IPI_CALL_FUNC\n", this_cpu); |
dbcf4787 JA |
163 | generic_smp_call_function_interrupt(); |
164 | break; | |
165 | ||
166 | case IPI_CALL_FUNC_SINGLE: | |
167 | smp_debug(100, KERN_DEBUG "CPU%d IPI_CALL_FUNC_SINGLE\n", this_cpu); | |
168 | generic_smp_call_function_single_interrupt(); | |
1da177e4 LT |
169 | break; |
170 | ||
171 | case IPI_CPU_START: | |
5492a0f0 | 172 | smp_debug(100, KERN_DEBUG "CPU%d IPI_CPU_START\n", this_cpu); |
1da177e4 LT |
173 | break; |
174 | ||
175 | case IPI_CPU_STOP: | |
5492a0f0 | 176 | smp_debug(100, KERN_DEBUG "CPU%d IPI_CPU_STOP\n", this_cpu); |
1da177e4 | 177 | halt_processor(); |
1da177e4 LT |
178 | break; |
179 | ||
180 | case IPI_CPU_TEST: | |
5492a0f0 | 181 | smp_debug(100, KERN_DEBUG "CPU%d is alive!\n", this_cpu); |
1da177e4 LT |
182 | break; |
183 | ||
184 | default: | |
185 | printk(KERN_CRIT "Unknown IPI num on CPU%d: %lu\n", | |
186 | this_cpu, which); | |
1da177e4 LT |
187 | return IRQ_NONE; |
188 | } /* Switch */ | |
7085689e JB |
189 | /* let in any pending interrupts */ |
190 | local_irq_enable(); | |
191 | local_irq_disable(); | |
1da177e4 LT |
192 | } /* while (ops) */ |
193 | } | |
194 | return IRQ_HANDLED; | |
195 | } | |
196 | ||
197 | ||
198 | static inline void | |
199 | ipi_send(int cpu, enum ipi_message_type op) | |
200 | { | |
ef017beb | 201 | struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpu); |
3c97b5e9 | 202 | spinlock_t *lock = &per_cpu(ipi_lock, cpu); |
1da177e4 LT |
203 | unsigned long flags; |
204 | ||
3c97b5e9 | 205 | spin_lock_irqsave(lock, flags); |
1da177e4 | 206 | p->pending_ipi |= 1 << op; |
ef017beb | 207 | gsc_writel(IPI_IRQ - CPU_IRQ_BASE, p->hpa); |
3c97b5e9 | 208 | spin_unlock_irqrestore(lock, flags); |
1da177e4 LT |
209 | } |
210 | ||
dbcf4787 | 211 | static void |
91887a36 | 212 | send_IPI_mask(const struct cpumask *mask, enum ipi_message_type op) |
dbcf4787 JA |
213 | { |
214 | int cpu; | |
215 | ||
91887a36 | 216 | for_each_cpu(cpu, mask) |
dbcf4787 JA |
217 | ipi_send(cpu, op); |
218 | } | |
1da177e4 LT |
219 | |
220 | static inline void | |
221 | send_IPI_single(int dest_cpu, enum ipi_message_type op) | |
222 | { | |
7f2347a4 | 223 | BUG_ON(dest_cpu == NO_PROC_ID); |
1da177e4 LT |
224 | |
225 | ipi_send(dest_cpu, op); | |
226 | } | |
227 | ||
228 | static inline void | |
229 | send_IPI_allbutself(enum ipi_message_type op) | |
230 | { | |
231 | int i; | |
232 | ||
394e3902 AM |
233 | for_each_online_cpu(i) { |
234 | if (i != smp_processor_id()) | |
1da177e4 LT |
235 | send_IPI_single(i, op); |
236 | } | |
237 | } | |
238 | ||
239 | ||
240 | inline void | |
241 | smp_send_stop(void) { send_IPI_allbutself(IPI_CPU_STOP); } | |
242 | ||
243 | static inline void | |
244 | smp_send_start(void) { send_IPI_allbutself(IPI_CPU_START); } | |
245 | ||
246 | void | |
247 | smp_send_reschedule(int cpu) { send_IPI_single(cpu, IPI_RESCHEDULE); } | |
248 | ||
d911aed8 JB |
249 | void |
250 | smp_send_all_nop(void) | |
251 | { | |
252 | send_IPI_allbutself(IPI_NOP); | |
253 | } | |
254 | ||
91887a36 | 255 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
1da177e4 | 256 | { |
dbcf4787 | 257 | send_IPI_mask(mask, IPI_CALL_FUNC); |
1da177e4 LT |
258 | } |
259 | ||
dbcf4787 JA |
260 | void arch_send_call_function_single_ipi(int cpu) |
261 | { | |
262 | send_IPI_single(cpu, IPI_CALL_FUNC_SINGLE); | |
263 | } | |
1da177e4 LT |
264 | |
265 | /* | |
266 | * Flush all other CPU's tlb and then mine. Do this with on_each_cpu() | |
267 | * as we want to ensure all TLB's flushed before proceeding. | |
268 | */ | |
269 | ||
1da177e4 LT |
270 | void |
271 | smp_flush_tlb_all(void) | |
272 | { | |
15c8b6c1 | 273 | on_each_cpu(flush_tlb_all_local, NULL, 1); |
1da177e4 LT |
274 | } |
275 | ||
1da177e4 LT |
276 | /* |
277 | * Called by secondaries to update state and initialize CPU registers. | |
278 | */ | |
279 | static void __init | |
280 | smp_cpu_init(int cpunum) | |
281 | { | |
56f335c8 | 282 | extern int init_per_cpu(int); /* arch/parisc/kernel/processor.c */ |
1da177e4 | 283 | extern void init_IRQ(void); /* arch/parisc/kernel/irq.c */ |
56f335c8 | 284 | extern void start_cpu_itimer(void); /* arch/parisc/kernel/time.c */ |
1da177e4 LT |
285 | |
286 | /* Set modes and Enable floating point coprocessor */ | |
287 | (void) init_per_cpu(cpunum); | |
288 | ||
289 | disable_sr_hashing(); | |
290 | ||
291 | mb(); | |
292 | ||
293 | /* Well, support 2.4 linux scheme as well. */ | |
9bc181d8 | 294 | if (cpu_isset(cpunum, cpu_online_map)) |
1da177e4 LT |
295 | { |
296 | extern void machine_halt(void); /* arch/parisc.../process.c */ | |
297 | ||
298 | printk(KERN_CRIT "CPU#%d already initialized!\n", cpunum); | |
299 | machine_halt(); | |
300 | } | |
9bc181d8 | 301 | set_cpu_online(cpunum, true); |
1da177e4 LT |
302 | |
303 | /* Initialise the idle task for this CPU */ | |
304 | atomic_inc(&init_mm.mm_count); | |
305 | current->active_mm = &init_mm; | |
7f2347a4 | 306 | BUG_ON(current->mm); |
1da177e4 LT |
307 | enter_lazy_tlb(&init_mm, current); |
308 | ||
7022672e | 309 | init_IRQ(); /* make sure no IRQs are enabled or pending */ |
56f335c8 | 310 | start_cpu_itimer(); |
1da177e4 LT |
311 | } |
312 | ||
313 | ||
314 | /* | |
315 | * Slaves start using C here. Indirectly called from smp_slave_stext. | |
316 | * Do what start_kernel() and main() do for boot strap processor (aka monarch) | |
317 | */ | |
318 | void __init smp_callin(void) | |
319 | { | |
320 | int slave_id = cpu_now_booting; | |
1da177e4 LT |
321 | |
322 | smp_cpu_init(slave_id); | |
5bfb5d69 | 323 | preempt_disable(); |
1da177e4 | 324 | |
1da177e4 | 325 | flush_cache_all_local(); /* start with known state */ |
1b2425e3 | 326 | flush_tlb_all_local(NULL); |
1da177e4 LT |
327 | |
328 | local_irq_enable(); /* Interrupts have been off until now */ | |
329 | ||
330 | cpu_idle(); /* Wait for timer to schedule some work */ | |
331 | ||
332 | /* NOTREACHED */ | |
333 | panic("smp_callin() AAAAaaaaahhhh....\n"); | |
334 | } | |
335 | ||
336 | /* | |
337 | * Bring one cpu online. | |
338 | */ | |
8dff980f | 339 | int __cpuinit smp_boot_one_cpu(int cpuid) |
1da177e4 | 340 | { |
ef017beb | 341 | const struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpuid); |
1da177e4 LT |
342 | struct task_struct *idle; |
343 | long timeout; | |
344 | ||
345 | /* | |
346 | * Create an idle task for this CPU. Note the address wed* give | |
347 | * to kernel_thread is irrelevant -- it's going to start | |
348 | * where OS_BOOT_RENDEVZ vector in SAL says to start. But | |
349 | * this gets all the other task-y sort of data structures set | |
350 | * up like we wish. We need to pull the just created idle task | |
351 | * off the run queue and stuff it into the init_tasks[] array. | |
352 | * Sheesh . . . | |
353 | */ | |
354 | ||
355 | idle = fork_idle(cpuid); | |
356 | if (IS_ERR(idle)) | |
357 | panic("SMP: fork failed for CPU:%d", cpuid); | |
358 | ||
40f1f0de | 359 | task_thread_info(idle)->cpu = cpuid; |
1da177e4 LT |
360 | |
361 | /* Let _start know what logical CPU we're booting | |
362 | ** (offset into init_tasks[],cpu_data[]) | |
363 | */ | |
364 | cpu_now_booting = cpuid; | |
365 | ||
366 | /* | |
367 | ** boot strap code needs to know the task address since | |
368 | ** it also contains the process stack. | |
369 | */ | |
370 | smp_init_current_idle_task = idle ; | |
371 | mb(); | |
372 | ||
ef017beb | 373 | printk(KERN_INFO "Releasing cpu %d now, hpa=%lx\n", cpuid, p->hpa); |
1da177e4 LT |
374 | |
375 | /* | |
376 | ** This gets PDC to release the CPU from a very tight loop. | |
377 | ** | |
378 | ** From the PA-RISC 2.0 Firmware Architecture Reference Specification: | |
379 | ** "The MEM_RENDEZ vector specifies the location of OS_RENDEZ which | |
380 | ** is executed after receiving the rendezvous signal (an interrupt to | |
381 | ** EIR{0}). MEM_RENDEZ is valid only when it is nonzero and the | |
382 | ** contents of memory are valid." | |
383 | */ | |
ef017beb | 384 | gsc_writel(TIMER_IRQ - CPU_IRQ_BASE, p->hpa); |
1da177e4 LT |
385 | mb(); |
386 | ||
387 | /* | |
388 | * OK, wait a bit for that CPU to finish staggering about. | |
389 | * Slave will set a bit when it reaches smp_cpu_init(). | |
390 | * Once the "monarch CPU" sees the bit change, it can move on. | |
391 | */ | |
392 | for (timeout = 0; timeout < 10000; timeout++) { | |
393 | if(cpu_online(cpuid)) { | |
394 | /* Which implies Slave has started up */ | |
395 | cpu_now_booting = 0; | |
396 | smp_init_current_idle_task = NULL; | |
397 | goto alive ; | |
398 | } | |
399 | udelay(100); | |
400 | barrier(); | |
401 | } | |
402 | ||
403 | put_task_struct(idle); | |
404 | idle = NULL; | |
405 | ||
406 | printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid); | |
407 | return -1; | |
408 | ||
409 | alive: | |
410 | /* Remember the Slave data */ | |
5492a0f0 | 411 | smp_debug(100, KERN_DEBUG "SMP: CPU:%d came alive after %ld _us\n", |
1da177e4 | 412 | cpuid, timeout * 100); |
1da177e4 LT |
413 | return 0; |
414 | } | |
415 | ||
ef017beb | 416 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 417 | { |
ef017beb | 418 | int bootstrap_processor = per_cpu(cpu_data, 0).cpuid; |
1da177e4 | 419 | |
1da177e4 | 420 | /* Setup BSP mappings */ |
ef017beb | 421 | printk(KERN_INFO "SMP: bootstrap CPU ID is %d\n", bootstrap_processor); |
1da177e4 | 422 | |
9bc181d8 RR |
423 | set_cpu_online(bootstrap_processor, true); |
424 | set_cpu_present(bootstrap_processor, true); | |
1da177e4 LT |
425 | } |
426 | ||
427 | ||
428 | ||
429 | /* | |
430 | ** inventory.c:do_inventory() hasn't yet been run and thus we | |
7022672e | 431 | ** don't 'discover' the additional CPUs until later. |
1da177e4 LT |
432 | */ |
433 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
434 | { | |
6ad6c424 TG |
435 | int cpu; |
436 | ||
437 | for_each_possible_cpu(cpu) | |
438 | spin_lock_init(&per_cpu(ipi_lock, cpu)); | |
439 | ||
9bc181d8 | 440 | init_cpu_present(cpumask_of(0)); |
1da177e4 LT |
441 | |
442 | parisc_max_cpus = max_cpus; | |
443 | if (!max_cpus) | |
444 | printk(KERN_INFO "SMP mode deactivated.\n"); | |
445 | } | |
446 | ||
447 | ||
448 | void smp_cpus_done(unsigned int cpu_max) | |
449 | { | |
450 | return; | |
451 | } | |
452 | ||
453 | ||
b282b6f8 | 454 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 LT |
455 | { |
456 | if (cpu != 0 && cpu < parisc_max_cpus) | |
457 | smp_boot_one_cpu(cpu); | |
458 | ||
459 | return cpu_online(cpu) ? 0 : -ENOSYS; | |
460 | } | |
461 | ||
1da177e4 LT |
462 | #ifdef CONFIG_PROC_FS |
463 | int __init | |
464 | setup_profiling_timer(unsigned int multiplier) | |
465 | { | |
466 | return -EINVAL; | |
467 | } | |
468 | #endif |