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Commit | Line | Data |
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071327ec | 1 | /* |
1da177e4 LT |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * | |
7 | * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle | |
8 | * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) | |
9 | * Copyright 1999 Hewlett Packard Co. | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <linux/mm.h> | |
14 | #include <linux/ptrace.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/interrupt.h> | |
a38671d6 | 17 | #include <linux/extable.h> |
70ffdb93 | 18 | #include <linux/uaccess.h> |
1da177e4 | 19 | |
1da177e4 LT |
20 | #include <asm/traps.h> |
21 | ||
1da177e4 LT |
22 | /* Various important other fields */ |
23 | #define bit22set(x) (x & 0x00000200) | |
24 | #define bits23_25set(x) (x & 0x000001c0) | |
25 | #define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80) | |
26 | /* extended opcode is 0x6a */ | |
27 | ||
28 | #define BITSSET 0x1c0 /* for identifying LDCW */ | |
29 | ||
30 | ||
31 | DEFINE_PER_CPU(struct exception_data, exception_data); | |
32 | ||
fef47e2a HD |
33 | int show_unhandled_signals = 1; |
34 | ||
1da177e4 LT |
35 | /* |
36 | * parisc_acctyp(unsigned int inst) -- | |
37 | * Given a PA-RISC memory access instruction, determine if the | |
38 | * the instruction would perform a memory read or memory write | |
39 | * operation. | |
40 | * | |
41 | * This function assumes that the given instruction is a memory access | |
42 | * instruction (i.e. you should really only call it if you know that | |
43 | * the instruction has generated some sort of a memory access fault). | |
44 | * | |
45 | * Returns: | |
46 | * VM_READ if read operation | |
47 | * VM_WRITE if write operation | |
48 | * VM_EXEC if execute operation | |
49 | */ | |
50 | static unsigned long | |
51 | parisc_acctyp(unsigned long code, unsigned int inst) | |
52 | { | |
53 | if (code == 6 || code == 16) | |
54 | return VM_EXEC; | |
55 | ||
56 | switch (inst & 0xf0000000) { | |
57 | case 0x40000000: /* load */ | |
58 | case 0x50000000: /* new load */ | |
59 | return VM_READ; | |
60 | ||
61 | case 0x60000000: /* store */ | |
62 | case 0x70000000: /* new store */ | |
63 | return VM_WRITE; | |
64 | ||
65 | case 0x20000000: /* coproc */ | |
66 | case 0x30000000: /* coproc2 */ | |
67 | if (bit22set(inst)) | |
68 | return VM_WRITE; | |
69 | ||
70 | case 0x0: /* indexed/memory management */ | |
71 | if (bit22set(inst)) { | |
72 | /* | |
73 | * Check for the 'Graphics Flush Read' instruction. | |
74 | * It resembles an FDC instruction, except for bits | |
75 | * 20 and 21. Any combination other than zero will | |
76 | * utilize the block mover functionality on some | |
77 | * older PA-RISC platforms. The case where a block | |
78 | * move is performed from VM to graphics IO space | |
79 | * should be treated as a READ. | |
80 | * | |
81 | * The significance of bits 20,21 in the FDC | |
82 | * instruction is: | |
83 | * | |
84 | * 00 Flush data cache (normal instruction behavior) | |
85 | * 01 Graphics flush write (IO space -> VM) | |
86 | * 10 Graphics flush read (VM -> IO space) | |
87 | * 11 Graphics flush read/write (VM <-> IO space) | |
88 | */ | |
89 | if (isGraphicsFlushRead(inst)) | |
90 | return VM_READ; | |
91 | return VM_WRITE; | |
92 | } else { | |
93 | /* | |
94 | * Check for LDCWX and LDCWS (semaphore instructions). | |
95 | * If bits 23 through 25 are all 1's it is one of | |
96 | * the above two instructions and is a write. | |
97 | * | |
98 | * Note: With the limited bits we are looking at, | |
99 | * this will also catch PROBEW and PROBEWI. However, | |
100 | * these should never get in here because they don't | |
101 | * generate exceptions of the type: | |
102 | * Data TLB miss fault/data page fault | |
103 | * Data memory protection trap | |
104 | */ | |
105 | if (bits23_25set(inst) == BITSSET) | |
106 | return VM_WRITE; | |
107 | } | |
108 | return VM_READ; /* Default */ | |
109 | } | |
110 | return VM_READ; /* Default */ | |
111 | } | |
112 | ||
113 | #undef bit22set | |
114 | #undef bits23_25set | |
115 | #undef isGraphicsFlushRead | |
116 | #undef BITSSET | |
117 | ||
118 | ||
119 | #if 0 | |
120 | /* This is the treewalk to find a vma which is the highest that has | |
121 | * a start < addr. We're using find_vma_prev instead right now, but | |
122 | * we might want to use this at some point in the future. Probably | |
123 | * not, but I want it committed to CVS so I don't lose it :-) | |
124 | */ | |
125 | while (tree != vm_avl_empty) { | |
126 | if (tree->vm_start > addr) { | |
127 | tree = tree->vm_avl_left; | |
128 | } else { | |
129 | prev = tree; | |
130 | if (prev->vm_next == NULL) | |
131 | break; | |
132 | if (prev->vm_next->vm_start > addr) | |
133 | break; | |
134 | tree = tree->vm_avl_right; | |
135 | } | |
136 | } | |
137 | #endif | |
138 | ||
c61c25eb KM |
139 | int fixup_exception(struct pt_regs *regs) |
140 | { | |
141 | const struct exception_table_entry *fix; | |
142 | ||
143 | fix = search_exception_tables(regs->iaoq[0]); | |
144 | if (fix) { | |
145 | struct exception_data *d; | |
496252f7 | 146 | d = this_cpu_ptr(&exception_data); |
c61c25eb | 147 | d->fault_ip = regs->iaoq[0]; |
2ef4dfd9 | 148 | d->fault_gp = regs->gr[27]; |
c61c25eb KM |
149 | d->fault_space = regs->isr; |
150 | d->fault_addr = regs->ior; | |
151 | ||
0de79858 HD |
152 | regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup; |
153 | regs->iaoq[0] &= ~3; | |
c61c25eb KM |
154 | /* |
155 | * NOTE: In some cases the faulting instruction | |
156 | * may be in the delay slot of a branch. We | |
157 | * don't want to take the branch, so we don't | |
158 | * increment iaoq[1], instead we set it to be | |
159 | * iaoq[0]+4, and clear the B bit in the PSW | |
160 | */ | |
161 | regs->iaoq[1] = regs->iaoq[0] + 4; | |
162 | regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */ | |
163 | ||
164 | return 1; | |
165 | } | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
b391667e HD |
170 | /* |
171 | * parisc hardware trap list | |
172 | * | |
173 | * Documented in section 3 "Addressing and Access Control" of the | |
174 | * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual" | |
175 | * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf | |
176 | * | |
177 | * For implementation see handle_interruption() in traps.c | |
178 | */ | |
179 | static const char * const trap_description[] = { | |
180 | [1] "High-priority machine check (HPMC)", | |
181 | [2] "Power failure interrupt", | |
182 | [3] "Recovery counter trap", | |
183 | [5] "Low-priority machine check", | |
184 | [6] "Instruction TLB miss fault", | |
185 | [7] "Instruction access rights / protection trap", | |
186 | [8] "Illegal instruction trap", | |
187 | [9] "Break instruction trap", | |
188 | [10] "Privileged operation trap", | |
189 | [11] "Privileged register trap", | |
190 | [12] "Overflow trap", | |
191 | [13] "Conditional trap", | |
192 | [14] "FP Assist Exception trap", | |
193 | [15] "Data TLB miss fault", | |
194 | [16] "Non-access ITLB miss fault", | |
195 | [17] "Non-access DTLB miss fault", | |
196 | [18] "Data memory protection/unaligned access trap", | |
197 | [19] "Data memory break trap", | |
198 | [20] "TLB dirty bit trap", | |
199 | [21] "Page reference trap", | |
200 | [22] "Assist emulation trap", | |
201 | [25] "Taken branch trap", | |
202 | [26] "Data memory access rights trap", | |
203 | [27] "Data memory protection ID trap", | |
204 | [28] "Unaligned data reference trap", | |
205 | }; | |
206 | ||
0a862485 HD |
207 | const char *trap_name(unsigned long code) |
208 | { | |
209 | const char *t = NULL; | |
210 | ||
211 | if (code < ARRAY_SIZE(trap_description)) | |
212 | t = trap_description[code]; | |
213 | ||
214 | return t ? t : "Unknown trap"; | |
215 | } | |
216 | ||
fef47e2a HD |
217 | /* |
218 | * Print out info about fatal segfaults, if the show_unhandled_signals | |
219 | * sysctl is set: | |
220 | */ | |
221 | static inline void | |
222 | show_signal_msg(struct pt_regs *regs, unsigned long code, | |
223 | unsigned long address, struct task_struct *tsk, | |
224 | struct vm_area_struct *vma) | |
225 | { | |
226 | if (!unhandled_signal(tsk, SIGSEGV)) | |
227 | return; | |
228 | ||
229 | if (!printk_ratelimit()) | |
230 | return; | |
231 | ||
232 | pr_warn("\n"); | |
233 | pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx", | |
234 | tsk->comm, code, address); | |
235 | print_vma_addr(KERN_CONT " in ", regs->iaoq[0]); | |
b391667e | 236 | |
0a862485 | 237 | pr_cont(" trap #%lu: %s%c", code, trap_name(code), |
b391667e HD |
238 | vma ? ',':'\n'); |
239 | ||
fef47e2a | 240 | if (vma) |
b391667e | 241 | pr_warn(KERN_CONT " vm_start = 0x%08lx, vm_end = 0x%08lx\n", |
fef47e2a HD |
242 | vma->vm_start, vma->vm_end); |
243 | ||
244 | show_regs(regs); | |
245 | } | |
246 | ||
1da177e4 LT |
247 | void do_page_fault(struct pt_regs *regs, unsigned long code, |
248 | unsigned long address) | |
249 | { | |
250 | struct vm_area_struct *vma, *prev_vma; | |
2d8b22de JDA |
251 | struct task_struct *tsk; |
252 | struct mm_struct *mm; | |
1da177e4 | 253 | unsigned long acc_type; |
83c54070 | 254 | int fault; |
2d8b22de | 255 | unsigned int flags; |
1da177e4 | 256 | |
699817c3 | 257 | if (faulthandler_disabled()) |
1da177e4 LT |
258 | goto no_context; |
259 | ||
2d8b22de JDA |
260 | tsk = current; |
261 | mm = tsk->mm; | |
262 | if (!mm) | |
263 | goto no_context; | |
264 | ||
265 | flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; | |
759496ba JW |
266 | if (user_mode(regs)) |
267 | flags |= FAULT_FLAG_USER; | |
0772dac1 FP |
268 | |
269 | acc_type = parisc_acctyp(code, regs->iir); | |
759496ba JW |
270 | if (acc_type & VM_WRITE) |
271 | flags |= FAULT_FLAG_WRITE; | |
38057477 | 272 | retry: |
1da177e4 LT |
273 | down_read(&mm->mmap_sem); |
274 | vma = find_vma_prev(mm, address, &prev_vma); | |
275 | if (!vma || address < vma->vm_start) | |
276 | goto check_expansion; | |
277 | /* | |
278 | * Ok, we have a good vm_area for this memory access. We still need to | |
279 | * check the access permissions. | |
280 | */ | |
281 | ||
282 | good_area: | |
283 | ||
1da177e4 LT |
284 | if ((vma->vm_flags & acc_type) != acc_type) |
285 | goto bad_area; | |
286 | ||
287 | /* | |
288 | * If for any reason at all we couldn't handle the fault, make | |
289 | * sure we exit gracefully rather than endlessly redo the | |
290 | * fault. | |
291 | */ | |
292 | ||
dcddffd4 | 293 | fault = handle_mm_fault(vma, address, flags); |
38057477 KC |
294 | |
295 | if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) | |
296 | return; | |
297 | ||
83c54070 | 298 | if (unlikely(fault & VM_FAULT_ERROR)) { |
1da177e4 | 299 | /* |
67a5a59d | 300 | * We hit a shared mapping outside of the file, or some |
6e346228 LT |
301 | * other thing happened to us that made us unable to |
302 | * handle the page fault gracefully. | |
1da177e4 | 303 | */ |
83c54070 NP |
304 | if (fault & VM_FAULT_OOM) |
305 | goto out_of_memory; | |
33692f27 LT |
306 | else if (fault & VM_FAULT_SIGSEGV) |
307 | goto bad_area; | |
83c54070 NP |
308 | else if (fault & VM_FAULT_SIGBUS) |
309 | goto bad_area; | |
310 | BUG(); | |
1da177e4 | 311 | } |
38057477 KC |
312 | if (flags & FAULT_FLAG_ALLOW_RETRY) { |
313 | if (fault & VM_FAULT_MAJOR) | |
314 | current->maj_flt++; | |
315 | else | |
316 | current->min_flt++; | |
317 | if (fault & VM_FAULT_RETRY) { | |
318 | flags &= ~FAULT_FLAG_ALLOW_RETRY; | |
319 | ||
320 | /* | |
321 | * No need to up_read(&mm->mmap_sem) as we would | |
322 | * have already released it in __lock_page_or_retry | |
323 | * in mm/filemap.c. | |
324 | */ | |
325 | ||
326 | goto retry; | |
327 | } | |
328 | } | |
1da177e4 LT |
329 | up_read(&mm->mmap_sem); |
330 | return; | |
331 | ||
332 | check_expansion: | |
333 | vma = prev_vma; | |
334 | if (vma && (expand_stack(vma, address) == 0)) | |
335 | goto good_area; | |
336 | ||
337 | /* | |
338 | * Something tried to access memory that isn't in our memory map.. | |
339 | */ | |
340 | bad_area: | |
341 | up_read(&mm->mmap_sem); | |
342 | ||
343 | if (user_mode(regs)) { | |
344 | struct siginfo si; | |
345 | ||
fef47e2a HD |
346 | show_signal_msg(regs, code, address, tsk, vma); |
347 | ||
1f2048fd HD |
348 | switch (code) { |
349 | case 15: /* Data TLB miss fault/Data page fault */ | |
49d1cb2b HD |
350 | /* send SIGSEGV when outside of vma */ |
351 | if (!vma || | |
352 | address < vma->vm_start || address > vma->vm_end) { | |
353 | si.si_signo = SIGSEGV; | |
354 | si.si_code = SEGV_MAPERR; | |
355 | break; | |
356 | } | |
357 | ||
358 | /* send SIGSEGV for wrong permissions */ | |
359 | if ((vma->vm_flags & acc_type) != acc_type) { | |
360 | si.si_signo = SIGSEGV; | |
361 | si.si_code = SEGV_ACCERR; | |
362 | break; | |
363 | } | |
364 | ||
365 | /* probably address is outside of mapped file */ | |
366 | /* fall through */ | |
1f2048fd HD |
367 | case 17: /* NA data TLB miss / page fault */ |
368 | case 18: /* Unaligned access - PCXS only */ | |
369 | si.si_signo = SIGBUS; | |
49d1cb2b | 370 | si.si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR; |
1f2048fd HD |
371 | break; |
372 | case 16: /* Non-access instruction TLB miss fault */ | |
373 | case 26: /* PCXL: Data memory access rights trap */ | |
374 | default: | |
375 | si.si_signo = SIGSEGV; | |
49d1cb2b HD |
376 | si.si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR; |
377 | break; | |
1f2048fd | 378 | } |
1da177e4 | 379 | si.si_errno = 0; |
1da177e4 | 380 | si.si_addr = (void __user *) address; |
1f2048fd | 381 | force_sig_info(si.si_signo, &si, current); |
1da177e4 LT |
382 | return; |
383 | } | |
384 | ||
385 | no_context: | |
386 | ||
c61c25eb KM |
387 | if (!user_mode(regs) && fixup_exception(regs)) { |
388 | return; | |
1da177e4 LT |
389 | } |
390 | ||
391 | parisc_terminate("Bad Address (null pointer deref?)", regs, code, address); | |
392 | ||
393 | out_of_memory: | |
394 | up_read(&mm->mmap_sem); | |
53e30d02 NP |
395 | if (!user_mode(regs)) |
396 | goto no_context; | |
397 | pagefault_out_of_memory(); | |
1da177e4 | 398 | } |