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Commit | Line | Data |
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071327ec | 1 | /* |
1da177e4 LT |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * | |
7 | * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle | |
8 | * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) | |
9 | * Copyright 1999 Hewlett Packard Co. | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <linux/mm.h> | |
14 | #include <linux/ptrace.h> | |
15 | #include <linux/sched.h> | |
b17b0153 | 16 | #include <linux/sched/debug.h> |
1da177e4 | 17 | #include <linux/interrupt.h> |
a38671d6 | 18 | #include <linux/extable.h> |
70ffdb93 | 19 | #include <linux/uaccess.h> |
1da177e4 | 20 | |
1da177e4 LT |
21 | #include <asm/traps.h> |
22 | ||
1da177e4 LT |
23 | /* Various important other fields */ |
24 | #define bit22set(x) (x & 0x00000200) | |
25 | #define bits23_25set(x) (x & 0x000001c0) | |
26 | #define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80) | |
27 | /* extended opcode is 0x6a */ | |
28 | ||
29 | #define BITSSET 0x1c0 /* for identifying LDCW */ | |
30 | ||
31 | ||
32 | DEFINE_PER_CPU(struct exception_data, exception_data); | |
33 | ||
fef47e2a HD |
34 | int show_unhandled_signals = 1; |
35 | ||
1da177e4 LT |
36 | /* |
37 | * parisc_acctyp(unsigned int inst) -- | |
38 | * Given a PA-RISC memory access instruction, determine if the | |
39 | * the instruction would perform a memory read or memory write | |
40 | * operation. | |
41 | * | |
42 | * This function assumes that the given instruction is a memory access | |
43 | * instruction (i.e. you should really only call it if you know that | |
44 | * the instruction has generated some sort of a memory access fault). | |
45 | * | |
46 | * Returns: | |
47 | * VM_READ if read operation | |
48 | * VM_WRITE if write operation | |
49 | * VM_EXEC if execute operation | |
50 | */ | |
51 | static unsigned long | |
52 | parisc_acctyp(unsigned long code, unsigned int inst) | |
53 | { | |
54 | if (code == 6 || code == 16) | |
55 | return VM_EXEC; | |
56 | ||
57 | switch (inst & 0xf0000000) { | |
58 | case 0x40000000: /* load */ | |
59 | case 0x50000000: /* new load */ | |
60 | return VM_READ; | |
61 | ||
62 | case 0x60000000: /* store */ | |
63 | case 0x70000000: /* new store */ | |
64 | return VM_WRITE; | |
65 | ||
66 | case 0x20000000: /* coproc */ | |
67 | case 0x30000000: /* coproc2 */ | |
68 | if (bit22set(inst)) | |
69 | return VM_WRITE; | |
70 | ||
71 | case 0x0: /* indexed/memory management */ | |
72 | if (bit22set(inst)) { | |
73 | /* | |
74 | * Check for the 'Graphics Flush Read' instruction. | |
75 | * It resembles an FDC instruction, except for bits | |
76 | * 20 and 21. Any combination other than zero will | |
77 | * utilize the block mover functionality on some | |
78 | * older PA-RISC platforms. The case where a block | |
79 | * move is performed from VM to graphics IO space | |
80 | * should be treated as a READ. | |
81 | * | |
82 | * The significance of bits 20,21 in the FDC | |
83 | * instruction is: | |
84 | * | |
85 | * 00 Flush data cache (normal instruction behavior) | |
86 | * 01 Graphics flush write (IO space -> VM) | |
87 | * 10 Graphics flush read (VM -> IO space) | |
88 | * 11 Graphics flush read/write (VM <-> IO space) | |
89 | */ | |
90 | if (isGraphicsFlushRead(inst)) | |
91 | return VM_READ; | |
92 | return VM_WRITE; | |
93 | } else { | |
94 | /* | |
95 | * Check for LDCWX and LDCWS (semaphore instructions). | |
96 | * If bits 23 through 25 are all 1's it is one of | |
97 | * the above two instructions and is a write. | |
98 | * | |
99 | * Note: With the limited bits we are looking at, | |
100 | * this will also catch PROBEW and PROBEWI. However, | |
101 | * these should never get in here because they don't | |
102 | * generate exceptions of the type: | |
103 | * Data TLB miss fault/data page fault | |
104 | * Data memory protection trap | |
105 | */ | |
106 | if (bits23_25set(inst) == BITSSET) | |
107 | return VM_WRITE; | |
108 | } | |
109 | return VM_READ; /* Default */ | |
110 | } | |
111 | return VM_READ; /* Default */ | |
112 | } | |
113 | ||
114 | #undef bit22set | |
115 | #undef bits23_25set | |
116 | #undef isGraphicsFlushRead | |
117 | #undef BITSSET | |
118 | ||
119 | ||
120 | #if 0 | |
121 | /* This is the treewalk to find a vma which is the highest that has | |
122 | * a start < addr. We're using find_vma_prev instead right now, but | |
123 | * we might want to use this at some point in the future. Probably | |
124 | * not, but I want it committed to CVS so I don't lose it :-) | |
125 | */ | |
126 | while (tree != vm_avl_empty) { | |
127 | if (tree->vm_start > addr) { | |
128 | tree = tree->vm_avl_left; | |
129 | } else { | |
130 | prev = tree; | |
131 | if (prev->vm_next == NULL) | |
132 | break; | |
133 | if (prev->vm_next->vm_start > addr) | |
134 | break; | |
135 | tree = tree->vm_avl_right; | |
136 | } | |
137 | } | |
138 | #endif | |
139 | ||
c61c25eb KM |
140 | int fixup_exception(struct pt_regs *regs) |
141 | { | |
142 | const struct exception_table_entry *fix; | |
143 | ||
144 | fix = search_exception_tables(regs->iaoq[0]); | |
145 | if (fix) { | |
146 | struct exception_data *d; | |
496252f7 | 147 | d = this_cpu_ptr(&exception_data); |
c61c25eb | 148 | d->fault_ip = regs->iaoq[0]; |
2ef4dfd9 | 149 | d->fault_gp = regs->gr[27]; |
c61c25eb KM |
150 | d->fault_space = regs->isr; |
151 | d->fault_addr = regs->ior; | |
152 | ||
d19f5e41 HD |
153 | /* |
154 | * Fix up get_user() and put_user(). | |
155 | * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant | |
156 | * bit in the relative address of the fixup routine to indicate | |
157 | * that %r8 should be loaded with -EFAULT to report a userspace | |
158 | * access error. | |
159 | */ | |
160 | if (fix->fixup & 1) { | |
161 | regs->gr[8] = -EFAULT; | |
162 | ||
163 | /* zero target register for get_user() */ | |
164 | if (parisc_acctyp(0, regs->iir) == VM_READ) { | |
165 | int treg = regs->iir & 0x1f; | |
166 | regs->gr[treg] = 0; | |
167 | } | |
168 | } | |
169 | ||
0de79858 HD |
170 | regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup; |
171 | regs->iaoq[0] &= ~3; | |
c61c25eb KM |
172 | /* |
173 | * NOTE: In some cases the faulting instruction | |
174 | * may be in the delay slot of a branch. We | |
175 | * don't want to take the branch, so we don't | |
176 | * increment iaoq[1], instead we set it to be | |
177 | * iaoq[0]+4, and clear the B bit in the PSW | |
178 | */ | |
179 | regs->iaoq[1] = regs->iaoq[0] + 4; | |
180 | regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */ | |
181 | ||
182 | return 1; | |
183 | } | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
b391667e HD |
188 | /* |
189 | * parisc hardware trap list | |
190 | * | |
191 | * Documented in section 3 "Addressing and Access Control" of the | |
192 | * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual" | |
193 | * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf | |
194 | * | |
195 | * For implementation see handle_interruption() in traps.c | |
196 | */ | |
197 | static const char * const trap_description[] = { | |
198 | [1] "High-priority machine check (HPMC)", | |
199 | [2] "Power failure interrupt", | |
200 | [3] "Recovery counter trap", | |
201 | [5] "Low-priority machine check", | |
202 | [6] "Instruction TLB miss fault", | |
203 | [7] "Instruction access rights / protection trap", | |
204 | [8] "Illegal instruction trap", | |
205 | [9] "Break instruction trap", | |
206 | [10] "Privileged operation trap", | |
207 | [11] "Privileged register trap", | |
208 | [12] "Overflow trap", | |
209 | [13] "Conditional trap", | |
210 | [14] "FP Assist Exception trap", | |
211 | [15] "Data TLB miss fault", | |
212 | [16] "Non-access ITLB miss fault", | |
213 | [17] "Non-access DTLB miss fault", | |
214 | [18] "Data memory protection/unaligned access trap", | |
215 | [19] "Data memory break trap", | |
216 | [20] "TLB dirty bit trap", | |
217 | [21] "Page reference trap", | |
218 | [22] "Assist emulation trap", | |
219 | [25] "Taken branch trap", | |
220 | [26] "Data memory access rights trap", | |
221 | [27] "Data memory protection ID trap", | |
222 | [28] "Unaligned data reference trap", | |
223 | }; | |
224 | ||
0a862485 HD |
225 | const char *trap_name(unsigned long code) |
226 | { | |
227 | const char *t = NULL; | |
228 | ||
229 | if (code < ARRAY_SIZE(trap_description)) | |
230 | t = trap_description[code]; | |
231 | ||
232 | return t ? t : "Unknown trap"; | |
233 | } | |
234 | ||
fef47e2a HD |
235 | /* |
236 | * Print out info about fatal segfaults, if the show_unhandled_signals | |
237 | * sysctl is set: | |
238 | */ | |
239 | static inline void | |
240 | show_signal_msg(struct pt_regs *regs, unsigned long code, | |
241 | unsigned long address, struct task_struct *tsk, | |
242 | struct vm_area_struct *vma) | |
243 | { | |
244 | if (!unhandled_signal(tsk, SIGSEGV)) | |
245 | return; | |
246 | ||
247 | if (!printk_ratelimit()) | |
248 | return; | |
249 | ||
250 | pr_warn("\n"); | |
251 | pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx", | |
252 | tsk->comm, code, address); | |
253 | print_vma_addr(KERN_CONT " in ", regs->iaoq[0]); | |
b391667e | 254 | |
b4a9eb4c | 255 | pr_cont("\ntrap #%lu: %s%c", code, trap_name(code), |
b391667e HD |
256 | vma ? ',':'\n'); |
257 | ||
fef47e2a | 258 | if (vma) |
8351badf DC |
259 | pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n", |
260 | vma->vm_start, vma->vm_end); | |
fef47e2a HD |
261 | |
262 | show_regs(regs); | |
263 | } | |
264 | ||
1da177e4 LT |
265 | void do_page_fault(struct pt_regs *regs, unsigned long code, |
266 | unsigned long address) | |
267 | { | |
268 | struct vm_area_struct *vma, *prev_vma; | |
2d8b22de JDA |
269 | struct task_struct *tsk; |
270 | struct mm_struct *mm; | |
1da177e4 | 271 | unsigned long acc_type; |
83c54070 | 272 | int fault; |
2d8b22de | 273 | unsigned int flags; |
1da177e4 | 274 | |
699817c3 | 275 | if (faulthandler_disabled()) |
1da177e4 LT |
276 | goto no_context; |
277 | ||
2d8b22de JDA |
278 | tsk = current; |
279 | mm = tsk->mm; | |
280 | if (!mm) | |
281 | goto no_context; | |
282 | ||
283 | flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; | |
759496ba JW |
284 | if (user_mode(regs)) |
285 | flags |= FAULT_FLAG_USER; | |
0772dac1 FP |
286 | |
287 | acc_type = parisc_acctyp(code, regs->iir); | |
759496ba JW |
288 | if (acc_type & VM_WRITE) |
289 | flags |= FAULT_FLAG_WRITE; | |
38057477 | 290 | retry: |
1da177e4 LT |
291 | down_read(&mm->mmap_sem); |
292 | vma = find_vma_prev(mm, address, &prev_vma); | |
293 | if (!vma || address < vma->vm_start) | |
294 | goto check_expansion; | |
295 | /* | |
296 | * Ok, we have a good vm_area for this memory access. We still need to | |
297 | * check the access permissions. | |
298 | */ | |
299 | ||
300 | good_area: | |
301 | ||
1da177e4 LT |
302 | if ((vma->vm_flags & acc_type) != acc_type) |
303 | goto bad_area; | |
304 | ||
305 | /* | |
306 | * If for any reason at all we couldn't handle the fault, make | |
307 | * sure we exit gracefully rather than endlessly redo the | |
308 | * fault. | |
309 | */ | |
310 | ||
dcddffd4 | 311 | fault = handle_mm_fault(vma, address, flags); |
38057477 KC |
312 | |
313 | if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) | |
314 | return; | |
315 | ||
83c54070 | 316 | if (unlikely(fault & VM_FAULT_ERROR)) { |
1da177e4 | 317 | /* |
67a5a59d | 318 | * We hit a shared mapping outside of the file, or some |
6e346228 LT |
319 | * other thing happened to us that made us unable to |
320 | * handle the page fault gracefully. | |
1da177e4 | 321 | */ |
83c54070 NP |
322 | if (fault & VM_FAULT_OOM) |
323 | goto out_of_memory; | |
33692f27 LT |
324 | else if (fault & VM_FAULT_SIGSEGV) |
325 | goto bad_area; | |
83c54070 NP |
326 | else if (fault & VM_FAULT_SIGBUS) |
327 | goto bad_area; | |
328 | BUG(); | |
1da177e4 | 329 | } |
38057477 KC |
330 | if (flags & FAULT_FLAG_ALLOW_RETRY) { |
331 | if (fault & VM_FAULT_MAJOR) | |
332 | current->maj_flt++; | |
333 | else | |
334 | current->min_flt++; | |
335 | if (fault & VM_FAULT_RETRY) { | |
336 | flags &= ~FAULT_FLAG_ALLOW_RETRY; | |
337 | ||
338 | /* | |
339 | * No need to up_read(&mm->mmap_sem) as we would | |
340 | * have already released it in __lock_page_or_retry | |
341 | * in mm/filemap.c. | |
342 | */ | |
343 | ||
344 | goto retry; | |
345 | } | |
346 | } | |
1da177e4 LT |
347 | up_read(&mm->mmap_sem); |
348 | return; | |
349 | ||
350 | check_expansion: | |
351 | vma = prev_vma; | |
352 | if (vma && (expand_stack(vma, address) == 0)) | |
353 | goto good_area; | |
354 | ||
355 | /* | |
356 | * Something tried to access memory that isn't in our memory map.. | |
357 | */ | |
358 | bad_area: | |
359 | up_read(&mm->mmap_sem); | |
360 | ||
361 | if (user_mode(regs)) { | |
362 | struct siginfo si; | |
363 | ||
fef47e2a HD |
364 | show_signal_msg(regs, code, address, tsk, vma); |
365 | ||
1f2048fd HD |
366 | switch (code) { |
367 | case 15: /* Data TLB miss fault/Data page fault */ | |
49d1cb2b HD |
368 | /* send SIGSEGV when outside of vma */ |
369 | if (!vma || | |
370 | address < vma->vm_start || address > vma->vm_end) { | |
371 | si.si_signo = SIGSEGV; | |
372 | si.si_code = SEGV_MAPERR; | |
373 | break; | |
374 | } | |
375 | ||
376 | /* send SIGSEGV for wrong permissions */ | |
377 | if ((vma->vm_flags & acc_type) != acc_type) { | |
378 | si.si_signo = SIGSEGV; | |
379 | si.si_code = SEGV_ACCERR; | |
380 | break; | |
381 | } | |
382 | ||
383 | /* probably address is outside of mapped file */ | |
384 | /* fall through */ | |
1f2048fd HD |
385 | case 17: /* NA data TLB miss / page fault */ |
386 | case 18: /* Unaligned access - PCXS only */ | |
387 | si.si_signo = SIGBUS; | |
49d1cb2b | 388 | si.si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR; |
1f2048fd HD |
389 | break; |
390 | case 16: /* Non-access instruction TLB miss fault */ | |
391 | case 26: /* PCXL: Data memory access rights trap */ | |
392 | default: | |
393 | si.si_signo = SIGSEGV; | |
49d1cb2b HD |
394 | si.si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR; |
395 | break; | |
1f2048fd | 396 | } |
1da177e4 | 397 | si.si_errno = 0; |
1da177e4 | 398 | si.si_addr = (void __user *) address; |
1f2048fd | 399 | force_sig_info(si.si_signo, &si, current); |
1da177e4 LT |
400 | return; |
401 | } | |
402 | ||
403 | no_context: | |
404 | ||
c61c25eb KM |
405 | if (!user_mode(regs) && fixup_exception(regs)) { |
406 | return; | |
1da177e4 LT |
407 | } |
408 | ||
409 | parisc_terminate("Bad Address (null pointer deref?)", regs, code, address); | |
410 | ||
411 | out_of_memory: | |
412 | up_read(&mm->mmap_sem); | |
53e30d02 NP |
413 | if (!user_mode(regs)) |
414 | goto no_context; | |
415 | pagefault_out_of_memory(); | |
1da177e4 | 416 | } |