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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e9ee2924 VG |
2 | /* |
3 | * Device Tree Source for AMCC Arches (dual 460GT board) | |
4 | * | |
5 | * (C) Copyright 2008 Applied Micro Circuits Corporation | |
6 | * Victor Gallardo <vgallardo@amcc.com> | |
7 | * Adam Graham <agraham@amcc.com> | |
8 | * | |
9 | * Based on the glacier.dts file | |
10 | * Stefan Roese <sr@denx.de> | |
11 | * Copyright 2008 DENX Software Engineering | |
12 | * | |
13 | * See file CREDITS for list of people who contributed to this | |
14 | * project. | |
e9ee2924 VG |
15 | */ |
16 | ||
17 | /dts-v1/; | |
18 | ||
19 | / { | |
20 | #address-cells = <2>; | |
21 | #size-cells = <1>; | |
22 | model = "amcc,arches"; | |
23 | compatible = "amcc,arches"; | |
24 | dcr-parent = <&{/cpus/cpu@0}>; | |
25 | ||
26 | aliases { | |
27 | ethernet0 = &EMAC0; | |
28 | ethernet1 = &EMAC1; | |
29 | ethernet2 = &EMAC2; | |
30 | serial0 = &UART0; | |
31 | }; | |
32 | ||
33 | cpus { | |
34 | #address-cells = <1>; | |
35 | #size-cells = <0>; | |
36 | ||
37 | cpu@0 { | |
38 | device_type = "cpu"; | |
39 | model = "PowerPC,460GT"; | |
40 | reg = <0x00000000>; | |
41 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
42 | timebase-frequency = <0>; /* Filled in by U-Boot */ | |
43 | i-cache-line-size = <32>; | |
44 | d-cache-line-size = <32>; | |
45 | i-cache-size = <32768>; | |
46 | d-cache-size = <32768>; | |
47 | dcr-controller; | |
48 | dcr-access-method = "native"; | |
6f57518c | 49 | next-level-cache = <&L2C0>; |
e9ee2924 VG |
50 | }; |
51 | }; | |
52 | ||
53 | memory { | |
54 | device_type = "memory"; | |
55 | reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ | |
56 | }; | |
57 | ||
58 | UIC0: interrupt-controller0 { | |
59 | compatible = "ibm,uic-460gt","ibm,uic"; | |
60 | interrupt-controller; | |
61 | cell-index = <0>; | |
62 | dcr-reg = <0x0c0 0x009>; | |
63 | #address-cells = <0>; | |
64 | #size-cells = <0>; | |
65 | #interrupt-cells = <2>; | |
66 | }; | |
67 | ||
68 | UIC1: interrupt-controller1 { | |
69 | compatible = "ibm,uic-460gt","ibm,uic"; | |
70 | interrupt-controller; | |
71 | cell-index = <1>; | |
72 | dcr-reg = <0x0d0 0x009>; | |
73 | #address-cells = <0>; | |
74 | #size-cells = <0>; | |
75 | #interrupt-cells = <2>; | |
76 | interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ | |
77 | interrupt-parent = <&UIC0>; | |
78 | }; | |
79 | ||
80 | UIC2: interrupt-controller2 { | |
81 | compatible = "ibm,uic-460gt","ibm,uic"; | |
82 | interrupt-controller; | |
83 | cell-index = <2>; | |
84 | dcr-reg = <0x0e0 0x009>; | |
85 | #address-cells = <0>; | |
86 | #size-cells = <0>; | |
87 | #interrupt-cells = <2>; | |
88 | interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ | |
89 | interrupt-parent = <&UIC0>; | |
90 | }; | |
91 | ||
92 | UIC3: interrupt-controller3 { | |
93 | compatible = "ibm,uic-460gt","ibm,uic"; | |
94 | interrupt-controller; | |
95 | cell-index = <3>; | |
96 | dcr-reg = <0x0f0 0x009>; | |
97 | #address-cells = <0>; | |
98 | #size-cells = <0>; | |
99 | #interrupt-cells = <2>; | |
100 | interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ | |
101 | interrupt-parent = <&UIC0>; | |
102 | }; | |
103 | ||
104 | SDR0: sdr { | |
105 | compatible = "ibm,sdr-460gt"; | |
106 | dcr-reg = <0x00e 0x002>; | |
107 | }; | |
108 | ||
109 | CPR0: cpr { | |
110 | compatible = "ibm,cpr-460gt"; | |
111 | dcr-reg = <0x00c 0x002>; | |
112 | }; | |
113 | ||
f661be6c SR |
114 | L2C0: l2c { |
115 | compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; | |
116 | dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ | |
117 | 0x030 0x008>; /* L2 cache DCR's */ | |
118 | cache-line-size = <32>; /* 32 bytes */ | |
119 | cache-size = <262144>; /* L2, 256K */ | |
120 | interrupt-parent = <&UIC1>; | |
121 | interrupts = <11 1>; | |
122 | }; | |
123 | ||
e9ee2924 VG |
124 | plb { |
125 | compatible = "ibm,plb-460gt", "ibm,plb4"; | |
126 | #address-cells = <2>; | |
127 | #size-cells = <1>; | |
128 | ranges; | |
129 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
130 | ||
131 | SDRAM0: sdram { | |
132 | compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; | |
133 | dcr-reg = <0x010 0x002>; | |
134 | }; | |
135 | ||
6f57518c SR |
136 | CRYPTO: crypto@180000 { |
137 | compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; | |
138 | reg = <4 0x00180000 0x80400>; | |
139 | interrupt-parent = <&UIC0>; | |
140 | interrupts = <0x1d 0x4>; | |
141 | }; | |
142 | ||
e9ee2924 VG |
143 | MAL0: mcmal { |
144 | compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; | |
145 | dcr-reg = <0x180 0x062>; | |
146 | num-tx-chans = <3>; | |
147 | num-rx-chans = <24>; | |
148 | #address-cells = <0>; | |
149 | #size-cells = <0>; | |
150 | interrupt-parent = <&UIC2>; | |
151 | interrupts = < /*TXEOB*/ 0x6 0x4 | |
152 | /*RXEOB*/ 0x7 0x4 | |
153 | /*SERR*/ 0x3 0x4 | |
154 | /*TXDE*/ 0x4 0x4 | |
155 | /*RXDE*/ 0x5 0x4>; | |
156 | desc-base-addr-high = <0x8>; | |
157 | }; | |
158 | ||
159 | POB0: opb { | |
160 | compatible = "ibm,opb-460gt", "ibm,opb"; | |
161 | #address-cells = <1>; | |
162 | #size-cells = <1>; | |
163 | ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; | |
164 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
165 | ||
166 | EBC0: ebc { | |
167 | compatible = "ibm,ebc-460gt", "ibm,ebc"; | |
168 | dcr-reg = <0x012 0x002>; | |
169 | #address-cells = <2>; | |
170 | #size-cells = <1>; | |
171 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
172 | /* ranges property is supplied by U-Boot */ | |
173 | interrupts = <0x6 0x4>; | |
174 | interrupt-parent = <&UIC1>; | |
f661be6c SR |
175 | |
176 | nor_flash@0,0 { | |
177 | compatible = "amd,s29gl256n", "cfi-flash"; | |
178 | bank-width = <2>; | |
179 | reg = <0x00000000 0x00000000 0x02000000>; | |
180 | #address-cells = <1>; | |
181 | #size-cells = <1>; | |
182 | partition@0 { | |
183 | label = "kernel"; | |
184 | reg = <0x00000000 0x001e0000>; | |
185 | }; | |
186 | partition@1e0000 { | |
187 | label = "dtb"; | |
188 | reg = <0x001e0000 0x00020000>; | |
189 | }; | |
190 | partition@200000 { | |
191 | label = "root"; | |
192 | reg = <0x00200000 0x00200000>; | |
193 | }; | |
194 | partition@400000 { | |
195 | label = "user"; | |
196 | reg = <0x00400000 0x01b60000>; | |
197 | }; | |
198 | partition@1f60000 { | |
199 | label = "env"; | |
200 | reg = <0x01f60000 0x00040000>; | |
201 | }; | |
202 | partition@1fa0000 { | |
203 | label = "u-boot"; | |
204 | reg = <0x01fa0000 0x00060000>; | |
205 | }; | |
206 | }; | |
e9ee2924 VG |
207 | }; |
208 | ||
209 | UART0: serial@ef600300 { | |
210 | device_type = "serial"; | |
211 | compatible = "ns16550"; | |
212 | reg = <0xef600300 0x00000008>; | |
213 | virtual-reg = <0xef600300>; | |
214 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
215 | current-speed = <0>; /* Filled in by U-Boot */ | |
216 | interrupt-parent = <&UIC1>; | |
217 | interrupts = <0x1 0x4>; | |
218 | }; | |
219 | ||
220 | IIC0: i2c@ef600700 { | |
221 | compatible = "ibm,iic-460gt", "ibm,iic"; | |
222 | reg = <0xef600700 0x00000014>; | |
223 | interrupt-parent = <&UIC0>; | |
224 | interrupts = <0x2 0x4>; | |
f661be6c SR |
225 | #address-cells = <1>; |
226 | #size-cells = <0>; | |
227 | sttm@4a { | |
228 | compatible = "ad,ad7414"; | |
229 | reg = <0x4a>; | |
230 | interrupt-parent = <&UIC1>; | |
231 | interrupts = <0x0 0x8>; | |
232 | }; | |
e9ee2924 VG |
233 | }; |
234 | ||
235 | IIC1: i2c@ef600800 { | |
236 | compatible = "ibm,iic-460gt", "ibm,iic"; | |
237 | reg = <0xef600800 0x00000014>; | |
238 | interrupt-parent = <&UIC0>; | |
239 | interrupts = <0x3 0x4>; | |
240 | }; | |
241 | ||
242 | TAH0: emac-tah@ef601350 { | |
243 | compatible = "ibm,tah-460gt", "ibm,tah"; | |
244 | reg = <0xef601350 0x00000030>; | |
245 | }; | |
246 | ||
247 | TAH1: emac-tah@ef601450 { | |
248 | compatible = "ibm,tah-460gt", "ibm,tah"; | |
249 | reg = <0xef601450 0x00000030>; | |
250 | }; | |
251 | ||
252 | EMAC0: ethernet@ef600e00 { | |
253 | device_type = "network"; | |
254 | compatible = "ibm,emac-460gt", "ibm,emac4sync"; | |
255 | interrupt-parent = <&EMAC0>; | |
256 | interrupts = <0x0 0x1>; | |
257 | #interrupt-cells = <1>; | |
258 | #address-cells = <0>; | |
259 | #size-cells = <0>; | |
260 | interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 | |
261 | /*Wake*/ 0x1 &UIC2 0x14 0x4>; | |
262 | reg = <0xef600e00 0x000000c4>; | |
263 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ | |
264 | mal-device = <&MAL0>; | |
265 | mal-tx-channel = <0>; | |
266 | mal-rx-channel = <0>; | |
267 | cell-index = <0>; | |
268 | max-frame-size = <9000>; | |
269 | rx-fifo-size = <4096>; | |
270 | tx-fifo-size = <2048>; | |
6f57518c | 271 | rx-fifo-size-gige = <16384>; |
e9ee2924 VG |
272 | phy-mode = "sgmii"; |
273 | phy-map = <0xffffffff>; | |
274 | gpcs-address = <0x0000000a>; | |
275 | tah-device = <&TAH0>; | |
276 | tah-channel = <0>; | |
277 | has-inverted-stacr-oc; | |
278 | has-new-stacr-staopc; | |
279 | }; | |
280 | ||
281 | EMAC1: ethernet@ef600f00 { | |
282 | device_type = "network"; | |
283 | compatible = "ibm,emac-460gt", "ibm,emac4sync"; | |
284 | interrupt-parent = <&EMAC1>; | |
285 | interrupts = <0x0 0x1>; | |
286 | #interrupt-cells = <1>; | |
287 | #address-cells = <0>; | |
288 | #size-cells = <0>; | |
289 | interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 | |
290 | /*Wake*/ 0x1 &UIC2 0x15 0x4>; | |
291 | reg = <0xef600f00 0x000000c4>; | |
292 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ | |
293 | mal-device = <&MAL0>; | |
294 | mal-tx-channel = <1>; | |
295 | mal-rx-channel = <8>; | |
296 | cell-index = <1>; | |
297 | max-frame-size = <9000>; | |
298 | rx-fifo-size = <4096>; | |
299 | tx-fifo-size = <2048>; | |
6f57518c | 300 | rx-fifo-size-gige = <16384>; |
e9ee2924 VG |
301 | phy-mode = "sgmii"; |
302 | phy-map = <0x00000000>; | |
303 | gpcs-address = <0x0000000b>; | |
304 | tah-device = <&TAH1>; | |
305 | tah-channel = <1>; | |
306 | has-inverted-stacr-oc; | |
307 | has-new-stacr-staopc; | |
308 | mdio-device = <&EMAC0>; | |
309 | }; | |
310 | ||
311 | EMAC2: ethernet@ef601100 { | |
312 | device_type = "network"; | |
313 | compatible = "ibm,emac-460gt", "ibm,emac4sync"; | |
314 | interrupt-parent = <&EMAC2>; | |
315 | interrupts = <0x0 0x1>; | |
316 | #interrupt-cells = <1>; | |
317 | #address-cells = <0>; | |
318 | #size-cells = <0>; | |
319 | interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 | |
320 | /*Wake*/ 0x1 &UIC2 0x16 0x4>; | |
321 | reg = <0xef601100 0x000000c4>; | |
322 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ | |
323 | mal-device = <&MAL0>; | |
324 | mal-tx-channel = <2>; | |
325 | mal-rx-channel = <16>; | |
326 | cell-index = <2>; | |
327 | max-frame-size = <9000>; | |
328 | rx-fifo-size = <4096>; | |
329 | tx-fifo-size = <2048>; | |
6f57518c SR |
330 | rx-fifo-size-gige = <16384>; |
331 | tx-fifo-size-gige = <16384>; /* emac2&3 only */ | |
e9ee2924 VG |
332 | phy-mode = "sgmii"; |
333 | phy-map = <0x00000001>; | |
334 | gpcs-address = <0x0000000C>; | |
335 | has-inverted-stacr-oc; | |
336 | has-new-stacr-staopc; | |
337 | mdio-device = <&EMAC0>; | |
338 | }; | |
339 | }; | |
340 | }; | |
341 | }; |