[mirror_ubuntu-focal-kernel.git] / arch / powerpc / boot / dts / fsl / mpc8540ads.dts

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC8540 ADS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 */

/dts-v1/;

/include/ "e500v2_power_isa.dtsi"

/ {
	model = "MPC8540ADS";
	compatible = "MPC8540ADS", "MPC85xxADS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8540@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;	//  33 MHz, from uboot
			bus-frequency = <0>;	// 166 MHz
			clock-frequency = <0>;	// 825 MHz, from uboot
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x8000000>;	// 128M at 0x0
	};

	soc8540@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x100000>;
		bus-frequency = <0>;

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <8>;
		};

		ecm@1000 {
			compatible = "fsl,mpc8540-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,mpc8540-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8540-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x0>;
				};
				phy1: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x1>;
				};
				phy3: ethernet-phy@3 {
					interrupt-parent = <&mpic>;
					interrupts = <7 1>;
					reg = <0x3>;
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet2: ethernet@26000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <2>;
			device_type = "network";
			model = "FEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			ranges = <0x0 0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <41 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi2>;
			phy-handle = <&phy3>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi2: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>; 	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};
		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	pci0: pci@e0008000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x02 */
			0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
			0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
			0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
			0x1000 0x0 0x0 0x4 &mpic 0x4 0x1

			/* IDSEL 0x03 */
			0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
			0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x1800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x04 */
			0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
			0x2000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x05 */
			0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x2800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x0c */
			0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
			0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
			0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
			0x6000 0x0 0x0 0x4 &mpic 0x4 0x1

			/* IDSEL 0x0d */
			0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
			0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x6800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x0e */
			0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
			0x7000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x0f */
			0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x7800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x12 */
			0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x4 0x1

			/* IDSEL 0x13 */
			0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
			0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x9800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x14 */
			0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
			0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
			0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
			0xa000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x15 */
			0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
2654d638 AF	2	/*
	3	* MPC8540 ADS Device Tree Source
	4	*
32f960e9	5	* Copyright 2006, 2008 Freescale Semiconductor Inc.
2654d638 AF	6	*/
2654d638 AF	7
32f960e9	8	/dts-v1/;
2654d638	9
dc37374b	10	/include/ "e500v2_power_isa.dtsi"
2eb28006	11
2654d638 AF	12	/ {
2654d638 AF	13	model = "MPC8540ADS";
52094879	14	compatible = "MPC8540ADS", "MPC85xxADS";
2654d638 AF	15	#address-cells = <1>;
2654d638 AF	16	#size-cells = <1>;
2654d638	17
ea082fa9 KG	18	aliases {
	19	ethernet0 = &enet0;
	20	ethernet1 = &enet1;
	21	ethernet2 = &enet2;
	22	serial0 = &serial0;
	23	serial1 = &serial1;
	24	pci0 = &pci0;
	25	};
	26
2654d638	27	cpus {
2654d638 AF	28	#address-cells = <1>;
2654d638 AF	29	#size-cells = <0>;
2654d638 AF	30
	31	PowerPC,8540@0 {
	32	device_type = "cpu";
32f960e9 KG	33	reg = <0x0>;
	34	d-cache-line-size = <32>; // 32 bytes
	35	i-cache-line-size = <32>; // 32 bytes
	36	d-cache-size = <0x8000>; // L1, 32K
	37	i-cache-size = <0x8000>; // L1, 32K
2654d638 AF	38	timebase-frequency = <0>; // 33 MHz, from uboot
	39	bus-frequency = <0>; // 166 MHz
	40	clock-frequency = <0>; // 825 MHz, from uboot
c054065b	41	next-level-cache = <&L2>;
2654d638 AF	42	};
	43	};
	44
	45	memory {
	46	device_type = "memory";
32f960e9	47	reg = <0x0 0x8000000>; // 128M at 0x0
2654d638 AF	48	};
	49
	50	soc8540@e0000000 {
	51	#address-cells = <1>;
	52	#size-cells = <1>;
2654d638	53	device_type = "soc";
cf0d19fb	54	compatible = "simple-bus";
32f960e9	55	ranges = <0x0 0xe0000000 0x100000>;
2654d638 AF	56	bus-frequency = <0>;
2654d638 AF	57
e1a22897 KG	58	ecm-law@0 {
	59	compatible = "fsl,ecm-law";
	60	reg = <0x0 0x1000>;
	61	fsl,num-laws = <8>;
	62	};
	63
	64	ecm@1000 {
	65	compatible = "fsl,mpc8540-ecm", "fsl,ecm";
	66	reg = <0x1000 0x1000>;
	67	interrupts = <17 2>;
	68	interrupt-parent = <&mpic>;
	69	};
	70
50cf6707	71	memory-controller@2000 {
8a4ab218	72	compatible = "fsl,mpc8540-memory-controller";
32f960e9	73	reg = <0x2000 0x1000>;
50cf6707	74	interrupt-parent = <&mpic>;
32f960e9	75	interrupts = <18 2>;
50cf6707 DJ	76	};
50cf6707 DJ	77
c054065b	78	L2: l2-cache-controller@20000 {
8a4ab218	79	compatible = "fsl,mpc8540-l2-cache-controller";
32f960e9 KG	80	reg = <0x20000 0x1000>;
	81	cache-line-size = <32>; // 32 bytes
	82	cache-size = <0x40000>; // L2, 256K
50cf6707	83	interrupt-parent = <&mpic>;
32f960e9	84	interrupts = <16 2>;
50cf6707 DJ	85	};
50cf6707 DJ	86
2654d638	87	i2c@3000 {
ec9686c4 KG	88	#address-cells = <1>;
	89	#size-cells = <0>;
	90	cell-index = <0>;
2654d638	91	compatible = "fsl-i2c";
32f960e9 KG	92	reg = <0x3000 0x100>;
32f960e9 KG	93	interrupts = <43 2>;
52094879	94	interrupt-parent = <&mpic>;
2654d638 AF	95	dfsrr;
	96	};
	97
dee80553 KG	98	dma@21300 {
	99	#address-cells = <1>;
	100	#size-cells = <1>;
	101	compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
	102	reg = <0x21300 0x4>;
	103	ranges = <0x0 0x21100 0x200>;
	104	cell-index = <0>;
	105	dma-channel@0 {
	106	compatible = "fsl,mpc8540-dma-channel",
	107	"fsl,eloplus-dma-channel";
	108	reg = <0x0 0x80>;
	109	cell-index = <0>;
	110	interrupt-parent = <&mpic>;
	111	interrupts = <20 2>;
	112	};
	113	dma-channel@80 {
	114	compatible = "fsl,mpc8540-dma-channel",
	115	"fsl,eloplus-dma-channel";
	116	reg = <0x80 0x80>;
	117	cell-index = <1>;
	118	interrupt-parent = <&mpic>;
	119	interrupts = <21 2>;
	120	};
	121	dma-channel@100 {
	122	compatible = "fsl,mpc8540-dma-channel",
	123	"fsl,eloplus-dma-channel";
	124	reg = <0x100 0x80>;
	125	cell-index = <2>;
	126	interrupt-parent = <&mpic>;
	127	interrupts = <22 2>;
	128	};
	129	dma-channel@180 {
	130	compatible = "fsl,mpc8540-dma-channel",
	131	"fsl,eloplus-dma-channel";
	132	reg = <0x180 0x80>;
	133	cell-index = <3>;
	134	interrupt-parent = <&mpic>;
	135	interrupts = <23 2>;
	136	};
	137	};
	138
e77b28eb	139	enet0: ethernet@24000 {
84ba4a58 AV	140	#address-cells = <1>;
84ba4a58 AV	141	#size-cells = <1>;
e77b28eb	142	cell-index = <0>;
2654d638 AF	143	device_type = "network";
	144	model = "TSEC";
	145	compatible = "gianfar";
32f960e9	146	reg = <0x24000 0x1000>;
84ba4a58	147	ranges = <0x0 0x24000 0x1000>;
eae98266	148	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	149	interrupts = <29 2 30 2 34 2>;
52094879	150	interrupt-parent = <&mpic>;
b31a1d8b	151	tbi-handle = <&tbi0>;
52094879	152	phy-handle = <&phy0>;
84ba4a58 AV	153
	154	mdio@520 {
	155	#address-cells = <1>;
	156	#size-cells = <0>;
	157	compatible = "fsl,gianfar-mdio";
	158	reg = <0x520 0x20>;
	159
	160	phy0: ethernet-phy@0 {
	161	interrupt-parent = <&mpic>;
	162	interrupts = <5 1>;
	163	reg = <0x0>;
84ba4a58 AV	164	};
	165	phy1: ethernet-phy@1 {
	166	interrupt-parent = <&mpic>;
	167	interrupts = <5 1>;
	168	reg = <0x1>;
84ba4a58 AV	169	};
	170	phy3: ethernet-phy@3 {
	171	interrupt-parent = <&mpic>;
	172	interrupts = <7 1>;
	173	reg = <0x3>;
84ba4a58 AV	174	};
	175	tbi0: tbi-phy@11 {
	176	reg = <0x11>;
	177	device_type = "tbi-phy";
	178	};
	179	};
2654d638 AF	180	};
2654d638 AF	181
e77b28eb	182	enet1: ethernet@25000 {
84ba4a58 AV	183	#address-cells = <1>;
84ba4a58 AV	184	#size-cells = <1>;
e77b28eb	185	cell-index = <1>;
2654d638 AF	186	device_type = "network";
	187	model = "TSEC";
	188	compatible = "gianfar";
32f960e9	189	reg = <0x25000 0x1000>;
84ba4a58	190	ranges = <0x0 0x25000 0x1000>;
eae98266	191	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	192	interrupts = <35 2 36 2 40 2>;
52094879	193	interrupt-parent = <&mpic>;
b31a1d8b	194	tbi-handle = <&tbi1>;
52094879	195	phy-handle = <&phy1>;
84ba4a58 AV	196
	197	mdio@520 {
	198	#address-cells = <1>;
	199	#size-cells = <0>;
	200	compatible = "fsl,gianfar-tbi";
	201	reg = <0x520 0x20>;
	202
	203	tbi1: tbi-phy@11 {
	204	reg = <0x11>;
	205	device_type = "tbi-phy";
	206	};
	207	};
2654d638 AF	208	};
2654d638 AF	209
e77b28eb	210	enet2: ethernet@26000 {
84ba4a58 AV	211	#address-cells = <1>;
84ba4a58 AV	212	#size-cells = <1>;
e77b28eb	213	cell-index = <2>;
2654d638	214	device_type = "network";
aa74a30b	215	model = "FEC";
2654d638	216	compatible = "gianfar";
32f960e9	217	reg = <0x26000 0x1000>;
84ba4a58	218	ranges = <0x0 0x26000 0x1000>;
eae98266	219	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	220	interrupts = <41 2>;
52094879	221	interrupt-parent = <&mpic>;
b31a1d8b	222	tbi-handle = <&tbi2>;
52094879	223	phy-handle = <&phy3>;
84ba4a58 AV	224
	225	mdio@520 {
	226	#address-cells = <1>;
	227	#size-cells = <0>;
	228	compatible = "fsl,gianfar-tbi";
	229	reg = <0x520 0x20>;
	230
	231	tbi2: tbi-phy@11 {
	232	reg = <0x11>;
	233	device_type = "tbi-phy";
	234	};
	235	};
2654d638 AF	236	};
2654d638 AF	237
ea082fa9 KG	238	serial0: serial@4500 {
ea082fa9 KG	239	cell-index = <0>;
2654d638	240	device_type = "serial";
f706bed1	241	compatible = "fsl,ns16550", "ns16550";
32f960e9	242	reg = <0x4500 0x100>; // reg base, size
2654d638	243	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	244	interrupts = <42 2>;
52094879	245	interrupt-parent = <&mpic>;
2654d638 AF	246	};
2654d638 AF	247
ea082fa9 KG	248	serial1: serial@4600 {
ea082fa9 KG	249	cell-index = <1>;
2654d638	250	device_type = "serial";
f706bed1	251	compatible = "fsl,ns16550", "ns16550";
32f960e9	252	reg = <0x4600 0x100>; // reg base, size
2654d638	253	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	254	interrupts = <42 2>;
52094879	255	interrupt-parent = <&mpic>;
2654d638	256	};
1b3c5cda	257	mpic: pic@40000 {
1b3c5cda KG	258	interrupt-controller;
	259	#address-cells = <0>;
	260	#interrupt-cells = <2>;
32f960e9	261	reg = <0x40000 0x40000>;
1b3c5cda KG	262	compatible = "chrp,open-pic";
1b3c5cda KG	263	device_type = "open-pic";
1b3c5cda KG	264	};
1b3c5cda KG	265	};
2654d638	266
ea082fa9	267	pci0: pci@e0008000 {
32f960e9	268	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda	269	interrupt-map = <
2654d638	270
1b3c5cda	271	/* IDSEL 0x02 */
32f960e9 KG	272	0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
	273	0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
	274	0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
	275	0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
2654d638	276
1b3c5cda	277	/* IDSEL 0x03 */
32f960e9 KG	278	0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
	279	0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
	280	0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
	281	0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
2654d638	282
1b3c5cda	283	/* IDSEL 0x04 */
32f960e9 KG	284	0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
	285	0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
	286	0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
	287	0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
2654d638	288
1b3c5cda	289	/* IDSEL 0x05 */
32f960e9 KG	290	0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
	291	0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
	292	0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
	293	0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
2654d638	294
1b3c5cda	295	/* IDSEL 0x0c */
32f960e9 KG	296	0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
	297	0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
	298	0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
	299	0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
2654d638	300
1b3c5cda	301	/* IDSEL 0x0d */
32f960e9 KG	302	0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
	303	0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
	304	0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
	305	0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
2654d638	306
1b3c5cda	307	/* IDSEL 0x0e */
32f960e9 KG	308	0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
	309	0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
	310	0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
	311	0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
2654d638	312
1b3c5cda	313	/* IDSEL 0x0f */
32f960e9 KG	314	0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
	315	0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
	316	0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
	317	0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
2654d638	318
1b3c5cda	319	/* IDSEL 0x12 */
32f960e9 KG	320	0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
	321	0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
	322	0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
	323	0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
2654d638	324
1b3c5cda	325	/* IDSEL 0x13 */
32f960e9 KG	326	0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
	327	0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
	328	0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
	329	0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
2654d638	330
1b3c5cda	331	/* IDSEL 0x14 */
32f960e9 KG	332	0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
	333	0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
	334	0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
	335	0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
2654d638	336
1b3c5cda	337	/* IDSEL 0x15 */
32f960e9 KG	338	0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
	339	0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
	340	0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
	341	0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
1b3c5cda	342	interrupt-parent = <&mpic>;
32f960e9	343	interrupts = <24 2>;
1b3c5cda	344	bus-range = <0 0>;
32f960e9 KG	345	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	346	0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
	347	clock-frequency = <66666666>;
1b3c5cda KG	348	#interrupt-cells = <1>;
	349	#size-cells = <2>;
	350	#address-cells = <3>;
32f960e9	351	reg = <0xe0008000 0x1000>;
1b3c5cda KG	352	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
1b3c5cda KG	353	device_type = "pci";
2654d638 AF	354	};
2654d638 AF	355	};