[mirror_ubuntu-focal-kernel.git] / arch / powerpc / boot / dts / fsl / mpc8548si-post.dtsi

/*
 * MPC8548 Silicon/SoC Device Tree Source (post include)
 *
 * Copyright 2011 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

&lbc {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
	interrupts = <19 2 0 0>;
};

/* controller at 0x8000 */
&pci0 {
	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
	device_type = "pci";
	interrupts = <24 0x2 0 0>;
	bus-range = <0 0xff>;
	#interrupt-cells = <1>;
	#size-cells = <2>;
	#address-cells = <3>;
};

/* controller at 0x9000 */
&pci1 {
	compatible = "fsl,mpc8540-pci";
	device_type = "pci";
	interrupts = <25 0x2 0 0>;
	bus-range = <0 0xff>;
	#interrupt-cells = <1>;
	#size-cells = <2>;
	#address-cells = <3>;
};

/* controller at 0xa000 */
&pci2 {
	compatible = "fsl,mpc8548-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0 255>;
	clock-frequency = <33333333>;
	interrupts = <26 2 0 0>;

	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <26 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
			>;
	};
};

&rio {
	compatible = "fsl,srio";
	interrupts = <48 2 0 0>;
	#address-cells = <2>;
	#size-cells = <2>;
	fsl,srio-rmu-handle = <&rmu>;
	ranges;

	port1 {
		#address-cells = <2>;
		#size-cells = <2>;
		cell-index = <1>;
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	compatible = "fsl,mpc8548-immr", "simple-bus";
	bus-frequency = <0>;		// Filled out by uboot.

	ecm-law@0 {
		compatible = "fsl,ecm-law";
		reg = <0x0 0x1000>;
		fsl,num-laws = <10>;
	};

	ecm@1000 {
		compatible = "fsl,mpc8548-ecm", "fsl,ecm";
		reg = <0x1000 0x1000>;
		interrupts = <17 2 0 0>;
	};

	memory-controller@2000 {
		compatible = "fsl,mpc8548-memory-controller";
		reg = <0x2000 0x1000>;
		interrupts = <18 2 0 0>;
	};

/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-duart-0.dtsi"

	L2: l2-cache-controller@20000 {
		compatible = "fsl,mpc8548-l2-cache-controller";
		reg = <0x20000 0x1000>;
		cache-line-size = <32>;	// 32 bytes
		cache-size = <0x80000>; // L2, 512K
		interrupts = <16 2 0 0>;
	};

/include/ "pq3-dma-0.dtsi"
/include/ "pq3-etsec1-0.dtsi"
/include/ "pq3-etsec1-1.dtsi"
/include/ "pq3-etsec1-2.dtsi"
/include/ "pq3-etsec1-3.dtsi"

/include/ "pq3-sec2.1-0.dtsi"
/include/ "pq3-mpic.dtsi"
/include/ "pq3-rmu-0.dtsi"

	global-utilities@e0000 {
		compatible = "fsl,mpc8548-guts";
		reg = <0xe0000 0x1000>;
		fsl,has-rstcr;
	};
};
Commit	Line	Data
53e23dcb KG	1	/*
	2	* MPC8548 Silicon/SoC Device Tree Source (post include)
	3	*
	4	* Copyright 2011 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	&lbc {
	36	#address-cells = <2>;
	37	#size-cells = <1>;
	38	compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
	39	interrupts = <19 2 0 0>;
	40	};
	41
	42	/* controller at 0x8000 */
	43	&pci0 {
	44	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
	45	device_type = "pci";
	46	interrupts = <24 0x2 0 0>;
	47	bus-range = <0 0xff>;
	48	#interrupt-cells = <1>;
	49	#size-cells = <2>;
	50	#address-cells = <3>;
	51	};
	52
	53	/* controller at 0x9000 */
	54	&pci1 {
	55	compatible = "fsl,mpc8540-pci";
	56	device_type = "pci";
	57	interrupts = <25 0x2 0 0>;
	58	bus-range = <0 0xff>;
	59	#interrupt-cells = <1>;
	60	#size-cells = <2>;
	61	#address-cells = <3>;
	62	};
	63
	64	/* controller at 0xa000 */
65	&pci2 {
66	compatible = "fsl,mpc8548-pcie";
67	device_type = "pci";
68	#size-cells = <2>;
69	#address-cells = <3>;
70	bus-range = <0 255>;
71	clock-frequency = <33333333>;
72	interrupts = <26 2 0 0>;
73
74	pcie@0 {
75	reg = <0 0 0 0 0>;
76	#interrupt-cells = <1>;
77	#size-cells = <2>;
78	#address-cells = <3>;
79	device_type = "pci";
80	interrupts = <26 2 0 0>;
81	interrupt-map-mask = <0xf800 0 0 7>;
82	interrupt-map = <
83	/* IDSEL 0x0 */
84	0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
85	0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
86	0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
87	0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
88	>;
89	};
90	};
91
8232a4de	92	&rio {
	93	compatible = "fsl,srio";
	94	interrupts = <48 2 0 0>;
	95	#address-cells = <2>;
	96	#size-cells = <2>;
	97	fsl,srio-rmu-handle = <&rmu>;
	98	ranges;
	99
	100	port1 {
	101	#address-cells = <2>;
	102	#size-cells = <2>;
	103	cell-index = <1>;
	104	};
	105	};
	106
53e23dcb KG	107	&soc {
	108	#address-cells = <1>;
	109	#size-cells = <1>;
	110	device_type = "soc";
	111	compatible = "fsl,mpc8548-immr", "simple-bus";
	112	bus-frequency = <0>; // Filled out by uboot.
	113
	114	ecm-law@0 {
	115	compatible = "fsl,ecm-law";
	116	reg = <0x0 0x1000>;
	117	fsl,num-laws = <10>;
	118	};
	119
	120	ecm@1000 {
	121	compatible = "fsl,mpc8548-ecm", "fsl,ecm";
	122	reg = <0x1000 0x1000>;
	123	interrupts = <17 2 0 0>;
	124	};
	125
	126	memory-controller@2000 {
	127	compatible = "fsl,mpc8548-memory-controller";
	128	reg = <0x2000 0x1000>;
	129	interrupts = <18 2 0 0>;
	130	};
	131
	132	/include/ "pq3-i2c-0.dtsi"
	133	/include/ "pq3-i2c-1.dtsi"
	134	/include/ "pq3-duart-0.dtsi"
	135
	136	L2: l2-cache-controller@20000 {
	137	compatible = "fsl,mpc8548-l2-cache-controller";
	138	reg = <0x20000 0x1000>;
	139	cache-line-size = <32>; // 32 bytes
	140	cache-size = <0x80000>; // L2, 512K
	141	interrupts = <16 2 0 0>;
	142	};
	143
	144	/include/ "pq3-dma-0.dtsi"
	145	/include/ "pq3-etsec1-0.dtsi"
	146	/include/ "pq3-etsec1-1.dtsi"
	147	/include/ "pq3-etsec1-2.dtsi"
	148	/include/ "pq3-etsec1-3.dtsi"
	149
	150	/include/ "pq3-sec2.1-0.dtsi"
	151	/include/ "pq3-mpic.dtsi"
8232a4de	152	/include/ "pq3-rmu-0.dtsi"
53e23dcb KG	153
	154	global-utilities@e0000 {
	155	compatible = "fsl,mpc8548-guts";
	156	reg = <0xe0000 0x1000>;
	157	fsl,has-rstcr;
	158	};
	159	};