[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / boot / dts / fsl / mpc8641_hpcn.dts

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC8641 HPCN Device Tree Source
 *
 * Copyright 2006 Freescale Semiconductor Inc.
 */

/include/ "mpc8641si-pre.dtsi"

/ {
	model = "MPC8641HPCN";
	compatible = "fsl,mpc8641hpcn";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>;	// 1G at 0x0
	};

	lbc: localbus@ffe05000 {
		reg = <0xffe05000 0x1000>;

		ranges = <0 0 0xef800000 0x00800000
			  2 0 0xffdf8000 0x00008000
			  3 0 0xffdf0000 0x00008000>;

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x00800000>;
			bank-width = <2>;
			device-width = <2>;
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				label = "kernel";
				reg = <0x00000000 0x00300000>;
			};
			partition@300000 {
				label = "firmware b";
				reg = <0x00300000 0x00100000>;
				read-only;
			};
			partition@400000 {
				label = "fs";
				reg = <0x00400000 0x00300000>;
			};
			partition@700000 {
				label = "firmware a";
				reg = <0x00700000 0x00100000>;
				read-only;
			};
		};
	};

	soc: soc8641@ffe00000 {
		ranges = <0x00000000 0xffe00000 0x00100000>;

		enet0: ethernet@24000 {
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		mdio@24520 {
			phy0: ethernet-phy@0 {
				interrupts = <10 1 0 0>;
				reg = <0>;
			};
			phy1: ethernet-phy@1 {
				interrupts = <10 1 0 0>;
				reg = <1>;
			};
			phy2: ethernet-phy@2 {
				interrupts = <10 1 0 0>;
				reg = <2>;
			};
			phy3: ethernet-phy@3 {
				interrupts = <10 1 0 0>;
				reg = <3>;
			};
			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		enet1: ethernet@25000 {
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
		};

		mdio@25520 {
			tbi1: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};
		
		enet2: ethernet@26000 {
			tbi-handle = <&tbi2>;
			phy-handle = <&phy2>;
			phy-connection-type = "rgmii-id";
		};

		mdio@26520 {
			tbi2: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		enet3: ethernet@27000 {
			tbi-handle = <&tbi3>;
			phy-handle = <&phy3>;
			phy-connection-type = "rgmii-id";
		};

		mdio@27520 {
			tbi3: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		rmu: rmu@d3000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,srio-rmu";
			reg = <0xd3000 0x500>;
			ranges = <0x0 0xd3000 0x500>;

			message-unit@0 {
				compatible = "fsl,srio-msg-unit";
				reg = <0x0 0x100>;
				interrupts = <
					53 2 0 0  /* msg1_tx_irq */
					54 2 0 0>;/* msg1_rx_irq */
			};
			message-unit@100 {
				compatible = "fsl,srio-msg-unit";
				reg = <0x100 0x100>;
				interrupts = <
					55 2 0 0  /* msg2_tx_irq */
					56 2 0 0>;/* msg2_rx_irq */
			};
			doorbell-unit@400 {
				compatible = "fsl,srio-dbell-unit";
				reg = <0x400 0x80>;
				interrupts = <
					49 2 0 0  /* bell_outb_irq */
					50 2 0 0>;/* bell_inb_irq */
			};
			port-write-unit@4e0 {
				compatible = "fsl,srio-port-write-unit";
				reg = <0x4e0 0x20>;
				interrupts = <48 2 0 0>;
			};
		};
	};

	pci0: pcie@ffe08000 {
		reg = <0xffe08000 0x1000>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
		interrupt-map-mask = <0xff00 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 func 0 - PCI slot 1 */
			0x8800 0 0 1 &mpic 2 1 0 0
			0x8800 0 0 2 &mpic 3 1 0 0
			0x8800 0 0 3 &mpic 4 1 0 0
			0x8800 0 0 4 &mpic 1 1 0 0

			/* IDSEL 0x11 func 1 - PCI slot 1 */
			0x8900 0 0 1 &mpic 2 1 0 0
			0x8900 0 0 2 &mpic 3 1 0 0
			0x8900 0 0 3 &mpic 4 1 0 0
			0x8900 0 0 4 &mpic 1 1 0 0

			/* IDSEL 0x11 func 2 - PCI slot 1 */
			0x8a00 0 0 1 &mpic 2 1 0 0
			0x8a00 0 0 2 &mpic 3 1 0 0
			0x8a00 0 0 3 &mpic 4 1 0 0
			0x8a00 0 0 4 &mpic 1 1 0 0

			/* IDSEL 0x11 func 3 - PCI slot 1 */
			0x8b00 0 0 1 &mpic 2 1 0 0
			0x8b00 0 0 2 &mpic 3 1 0 0
			0x8b00 0 0 3 &mpic 4 1 0 0
			0x8b00 0 0 4 &mpic 1 1 0 0

			/* IDSEL 0x11 func 4 - PCI slot 1 */
			0x8c00 0 0 1 &mpic 2 1 0 0
			0x8c00 0 0 2 &mpic 3 1 0 0
			0x8c00 0 0 3 &mpic 4 1 0 0
			0x8c00 0 0 4 &mpic 1 1 0 0

			/* IDSEL 0x11 func 5 - PCI slot 1 */
			0x8d00 0 0 1 &mpic 2 1 0 0
			0x8d00 0 0 2 &mpic 3 1 0 0
			0x8d00 0 0 3 &mpic 4 1 0 0
			0x8d00 0 0 4 &mpic 1 1 0 0

			/* IDSEL 0x11 func 6 - PCI slot 1 */
			0x8e00 0 0 1 &mpic 2 1 0 0
			0x8e00 0 0 2 &mpic 3 1 0 0
			0x8e00 0 0 3 &mpic 4 1 0 0
			0x8e00 0 0 4 &mpic 1 1 0 0

			/* IDSEL 0x11 func 7 - PCI slot 1 */
			0x8f00 0 0 1 &mpic 2 1 0 0
			0x8f00 0 0 2 &mpic 3 1 0 0
			0x8f00 0 0 3 &mpic 4 1 0 0
			0x8f00 0 0 4 &mpic 1 1 0 0

			/* IDSEL 0x12 func 0 - PCI slot 2 */
			0x9000 0 0 1 &mpic 3 1 0 0
			0x9000 0 0 2 &mpic 4 1 0 0
			0x9000 0 0 3 &mpic 1 1 0 0
			0x9000 0 0 4 &mpic 2 1 0 0

			/* IDSEL 0x12 func 1 - PCI slot 2 */
			0x9100 0 0 1 &mpic 3 1 0 0
			0x9100 0 0 2 &mpic 4 1 0 0
			0x9100 0 0 3 &mpic 1 1 0 0
			0x9100 0 0 4 &mpic 2 1 0 0

			/* IDSEL 0x12 func 2 - PCI slot 2 */
			0x9200 0 0 1 &mpic 3 1 0 0
			0x9200 0 0 2 &mpic 4 1 0 0
			0x9200 0 0 3 &mpic 1 1 0 0
			0x9200 0 0 4 &mpic 2 1 0 0

			/* IDSEL 0x12 func 3 - PCI slot 2 */
			0x9300 0 0 1 &mpic 3 1 0 0
			0x9300 0 0 2 &mpic 4 1 0 0
			0x9300 0 0 3 &mpic 1 1 0 0
			0x9300 0 0 4 &mpic 2 1 0 0

			/* IDSEL 0x12 func 4 - PCI slot 2 */
			0x9400 0 0 1 &mpic 3 1 0 0
			0x9400 0 0 2 &mpic 4 1 0 0
			0x9400 0 0 3 &mpic 1 1 0 0
			0x9400 0 0 4 &mpic 2 1 0 0

			/* IDSEL 0x12 func 5 - PCI slot 2 */
			0x9500 0 0 1 &mpic 3 1 0 0
			0x9500 0 0 2 &mpic 4 1 0 0
			0x9500 0 0 3 &mpic 1 1 0 0
			0x9500 0 0 4 &mpic 2 1 0 0

			/* IDSEL 0x12 func 6 - PCI slot 2 */
			0x9600 0 0 1 &mpic 3 1 0 0
			0x9600 0 0 2 &mpic 4 1 0 0
			0x9600 0 0 3 &mpic 1 1 0 0
			0x9600 0 0 4 &mpic 2 1 0 0

			/* IDSEL 0x12 func 7 - PCI slot 2 */
			0x9700 0 0 1 &mpic 3 1 0 0
			0x9700 0 0 2 &mpic 4 1 0 0
			0x9700 0 0 3 &mpic 1 1 0 0
			0x9700 0 0 4 &mpic 2 1 0 0

			// IDSEL 0x1c  USB
			0xe000 0 0 1 &i8259 12 2
			0xe100 0 0 2 &i8259 9 2
			0xe200 0 0 3 &i8259 10 2
			0xe300 0 0 4 &i8259 11 2

			// IDSEL 0x1d  Audio
			0xe800 0 0 1 &i8259 6 2

			// IDSEL 0x1e Legacy
			0xf000 0 0 1 &i8259 7 2
			0xf100 0 0 1 &i8259 7 2

			// IDSEL 0x1f IDE/SATA
			0xf800 0 0 1 &i8259 14 2
			0xf900 0 0 1 &i8259 5 2
			>;

		pcie@0 {
			ranges = <0x02000000 0x0 0x80000000
				  0x02000000 0x0 0x80000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00010000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0x80000000
					  0x02000000 0x0 0x80000000
					  0x0 0x20000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00010000>;
				isa@1e {
					device_type = "isa";
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0 0 0 0>;
					ranges = <1 0 0x01000000 0 0
						  0x00001000>;
					interrupt-parent = <&i8259>;

					i8259: interrupt-controller@20 {
						reg = <1 0x20 2
						       1 0xa0 2
						       1 0x4d0 2>;
						interrupt-controller;
						device_type = "interrupt-controller";
						#address-cells = <0>;
						#interrupt-cells = <2>;
						compatible = "chrp,iic";
						interrupts = <9 2 0 0>;
					};

					i8042@60 {
						#size-cells = <0>;
						#address-cells = <1>;
						reg = <1 0x60 1 1 0x64 1>;
						interrupts = <1 3 12 3>;
						interrupt-parent = <&i8259>;

						keyboard@0 {
							reg = <0>;
							compatible = "pnpPNP,303";
						};

						mouse@1 {
							reg = <1>;
							compatible = "pnpPNP,f03";
						};
					};

					rtc@70 {
						compatible =
							"pnpPNP,b00";
						reg = <1 0x70 2>;
					};

					gpio@400 {
						reg = <1 0x400 0x80>;
					};
				};
			};
		};

	};

	pci1: pcie@ffe09000 {
		reg = <0xffe09000 0x1000>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;

		pcie@0 {
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00010000>;
		};
	};
/*
 * Only one of Rapid IO or PCI can be present due to HW limitations and
 * due to the fact that the 2 now share address space in the new memory
 * map.  The most likely case is that we have PCI, so comment out the
 * rapidio node.  Leave it here for reference.

	rapidio@ffec0000 {
		reg = <0xffec0000 0x11000>;
		compatible = "fsl,srio";
		interrupts = <48 2 0 0>;
		#address-cells = <2>;
		#size-cells = <2>;
		fsl,srio-rmu-handle = <&rmu>;
		ranges;

		port1 {
			#address-cells = <2>;
			#size-cells = <2>;
			cell-index = <1>;
			ranges = <0 0 0x80000000 0 0x20000000>;
		};
	};
*/

};

/include/ "mpc8641si-post.dtsi"
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
707ba16f JL	2	/*
	3	* MPC8641 HPCN Device Tree Source
	4	*
	5	* Copyright 2006 Freescale Semiconductor Inc.
707ba16f JL	6	*/
707ba16f JL	7
334479d1	8	/include/ "mpc8641si-pre.dtsi"
707ba16f JL	9
	10	/ {
	11	model = "MPC8641HPCN";
06f35b4b	12	compatible = "fsl,mpc8641hpcn";
707ba16f	13
707ba16f JL	14	memory {
707ba16f JL	15	device_type = "memory";
6e050d4e	16	reg = <0x00000000 0x40000000>; // 1G at 0x0
707ba16f JL	17	};
707ba16f JL	18
334479d1	19	lbc: localbus@ffe05000 {
47f80a32	20	reg = <0xffe05000 0x1000>;
0ac247d5	21
47f80a32 BB	22	ranges = <0 0 0xef800000 0x00800000
	23	2 0 0xffdf8000 0x00008000
	24	3 0 0xffdf0000 0x00008000>;
0ac247d5 WF	25
	26	flash@0,0 {
	27	compatible = "cfi-flash";
6e050d4e	28	reg = <0 0 0x00800000>;
0ac247d5 WF	29	bank-width = <2>;
	30	device-width = <2>;
	31	#address-cells = <1>;
	32	#size-cells = <1>;
	33	partition@0 {
	34	label = "kernel";
6e050d4e	35	reg = <0x00000000 0x00300000>;
0ac247d5 WF	36	};
	37	partition@300000 {
	38	label = "firmware b";
6e050d4e	39	reg = <0x00300000 0x00100000>;
0ac247d5 WF	40	read-only;
	41	};
	42	partition@400000 {
	43	label = "fs";
6e050d4e	44	reg = <0x00400000 0x00300000>;
0ac247d5 WF	45	};
	46	partition@700000 {
	47	label = "firmware a";
6e050d4e	48	reg = <0x00700000 0x00100000>;
0ac247d5 WF	49	read-only;
	50	};
	51	};
	52	};
	53
334479d1	54	soc: soc8641@ffe00000 {
47f80a32	55	ranges = <0x00000000 0xffe00000 0x00100000>;
da385780	56
334479d1 AIB	57	enet0: ethernet@24000 {
	58	tbi-handle = <&tbi0>;
	59	phy-handle = <&phy0>;
	60	phy-connection-type = "rgmii-id";
707ba16f JL	61	};
707ba16f JL	62
334479d1 AIB	63	mdio@24520 {
	64	phy0: ethernet-phy@0 {
	65	interrupts = <10 1 0 0>;
	66	reg = <0>;
dee80553	67	};
334479d1 AIB	68	phy1: ethernet-phy@1 {
	69	interrupts = <10 1 0 0>;
	70	reg = <1>;
dee80553	71	};
334479d1 AIB	72	phy2: ethernet-phy@2 {
	73	interrupts = <10 1 0 0>;
	74	reg = <2>;
dee80553	75	};
334479d1 AIB	76	phy3: ethernet-phy@3 {
	77	interrupts = <10 1 0 0>;
	78	reg = <3>;
dee80553	79	};
334479d1 AIB	80	tbi0: tbi-phy@11 {
	81	reg = <0x11>;
	82	device_type = "tbi-phy";
d8bc55fb	83	};
707ba16f JL	84	};
707ba16f JL	85
1c1d1672	86	enet1: ethernet@25000 {
b31a1d8b	87	tbi-handle = <&tbi1>;
6d9065d8	88	phy-handle = <&phy1>;
cc65185d	89	phy-connection-type = "rgmii-id";
334479d1	90	};
d8bc55fb	91
334479d1 AIB	92	mdio@25520 {
	93	tbi1: tbi-phy@11 {
	94	reg = <0x11>;
	95	device_type = "tbi-phy";
d8bc55fb	96	};
707ba16f JL	97	};
707ba16f JL	98
1c1d1672	99	enet2: ethernet@26000 {
b31a1d8b	100	tbi-handle = <&tbi2>;
6d9065d8	101	phy-handle = <&phy2>;
cc65185d	102	phy-connection-type = "rgmii-id";
334479d1	103	};
d8bc55fb	104
334479d1 AIB	105	mdio@26520 {
	106	tbi2: tbi-phy@11 {
	107	reg = <0x11>;
	108	device_type = "tbi-phy";
d8bc55fb	109	};
707ba16f JL	110	};
707ba16f JL	111
1c1d1672	112	enet3: ethernet@27000 {
b31a1d8b	113	tbi-handle = <&tbi3>;
6d9065d8	114	phy-handle = <&phy3>;
cc65185d	115	phy-connection-type = "rgmii-id";
707ba16f	116	};
1c1d1672	117
334479d1 AIB	118	mdio@27520 {
	119	tbi3: tbi-phy@11 {
	120	reg = <0x11>;
	121	device_type = "tbi-phy";
	122	};
1b3c5cda	123	};
e1c1575f	124
54986964 KG	125	rmu: rmu@d3000 {
	126	#address-cells = <1>;
	127	#size-cells = <1>;
	128	compatible = "fsl,srio-rmu";
	129	reg = <0xd3000 0x500>;
	130	ranges = <0x0 0xd3000 0x500>;
	131
	132	message-unit@0 {
	133	compatible = "fsl,srio-msg-unit";
	134	reg = <0x0 0x100>;
	135	interrupts = <
595207b9 AIB	136	53 2 0 0 /* msg1_tx_irq */
595207b9 AIB	137	54 2 0 0>;/* msg1_rx_irq */
54986964 KG	138	};
	139	message-unit@100 {
	140	compatible = "fsl,srio-msg-unit";
	141	reg = <0x100 0x100>;
	142	interrupts = <
595207b9 AIB	143	55 2 0 0 /* msg2_tx_irq */
595207b9 AIB	144	56 2 0 0>;/* msg2_rx_irq */
54986964 KG	145	};
	146	doorbell-unit@400 {
	147	compatible = "fsl,srio-dbell-unit";
	148	reg = <0x400 0x80>;
	149	interrupts = <
334479d1	150	49 2 0 0 /* bell_outb_irq */
595207b9	151	50 2 0 0>;/* bell_inb_irq */
54986964 KG	152	};
	153	port-write-unit@4e0 {
	154	compatible = "fsl,srio-port-write-unit";
	155	reg = <0x4e0 0x20>;
595207b9	156	interrupts = <48 2 0 0>;
54986964 KG	157	};
54986964 KG	158	};
1b3c5cda	159	};
707ba16f	160
47f80a32	161	pci0: pcie@ffe08000 {
47f80a32	162	reg = <0xffe08000 0x1000>;
6e050d4e	163	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
47f80a32	164	0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
6e050d4e	165	interrupt-map-mask = <0xff00 0 0 7>;
1b3c5cda	166	interrupt-map = <
bebfa06c	167	/* IDSEL 0x11 func 0 - PCI slot 1 */
ccdde478 SW	168	0x8800 0 0 1 &mpic 2 1 0 0
	169	0x8800 0 0 2 &mpic 3 1 0 0
	170	0x8800 0 0 3 &mpic 4 1 0 0
	171	0x8800 0 0 4 &mpic 1 1 0 0
bebfa06c KG	172
bebfa06c KG	173	/* IDSEL 0x11 func 1 - PCI slot 1 */
ccdde478 SW	174	0x8900 0 0 1 &mpic 2 1 0 0
	175	0x8900 0 0 2 &mpic 3 1 0 0
	176	0x8900 0 0 3 &mpic 4 1 0 0
	177	0x8900 0 0 4 &mpic 1 1 0 0
bebfa06c KG	178
bebfa06c KG	179	/* IDSEL 0x11 func 2 - PCI slot 1 */
ccdde478 SW	180	0x8a00 0 0 1 &mpic 2 1 0 0
	181	0x8a00 0 0 2 &mpic 3 1 0 0
	182	0x8a00 0 0 3 &mpic 4 1 0 0
	183	0x8a00 0 0 4 &mpic 1 1 0 0
bebfa06c KG	184
bebfa06c KG	185	/* IDSEL 0x11 func 3 - PCI slot 1 */
ccdde478 SW	186	0x8b00 0 0 1 &mpic 2 1 0 0
	187	0x8b00 0 0 2 &mpic 3 1 0 0
	188	0x8b00 0 0 3 &mpic 4 1 0 0
	189	0x8b00 0 0 4 &mpic 1 1 0 0
bebfa06c KG	190
bebfa06c KG	191	/* IDSEL 0x11 func 4 - PCI slot 1 */
ccdde478 SW	192	0x8c00 0 0 1 &mpic 2 1 0 0
	193	0x8c00 0 0 2 &mpic 3 1 0 0
	194	0x8c00 0 0 3 &mpic 4 1 0 0
	195	0x8c00 0 0 4 &mpic 1 1 0 0
bebfa06c KG	196
bebfa06c KG	197	/* IDSEL 0x11 func 5 - PCI slot 1 */
ccdde478 SW	198	0x8d00 0 0 1 &mpic 2 1 0 0
	199	0x8d00 0 0 2 &mpic 3 1 0 0
	200	0x8d00 0 0 3 &mpic 4 1 0 0
	201	0x8d00 0 0 4 &mpic 1 1 0 0
bebfa06c KG	202
bebfa06c KG	203	/* IDSEL 0x11 func 6 - PCI slot 1 */
ccdde478 SW	204	0x8e00 0 0 1 &mpic 2 1 0 0
	205	0x8e00 0 0 2 &mpic 3 1 0 0
	206	0x8e00 0 0 3 &mpic 4 1 0 0
	207	0x8e00 0 0 4 &mpic 1 1 0 0
bebfa06c KG	208
bebfa06c KG	209	/* IDSEL 0x11 func 7 - PCI slot 1 */
ccdde478 SW	210	0x8f00 0 0 1 &mpic 2 1 0 0
	211	0x8f00 0 0 2 &mpic 3 1 0 0
	212	0x8f00 0 0 3 &mpic 4 1 0 0
	213	0x8f00 0 0 4 &mpic 1 1 0 0
bebfa06c KG	214
bebfa06c KG	215	/* IDSEL 0x12 func 0 - PCI slot 2 */
ccdde478 SW	216	0x9000 0 0 1 &mpic 3 1 0 0
	217	0x9000 0 0 2 &mpic 4 1 0 0
	218	0x9000 0 0 3 &mpic 1 1 0 0
	219	0x9000 0 0 4 &mpic 2 1 0 0
bebfa06c KG	220
bebfa06c KG	221	/* IDSEL 0x12 func 1 - PCI slot 2 */
ccdde478 SW	222	0x9100 0 0 1 &mpic 3 1 0 0
	223	0x9100 0 0 2 &mpic 4 1 0 0
	224	0x9100 0 0 3 &mpic 1 1 0 0
	225	0x9100 0 0 4 &mpic 2 1 0 0
bebfa06c KG	226
bebfa06c KG	227	/* IDSEL 0x12 func 2 - PCI slot 2 */
ccdde478 SW	228	0x9200 0 0 1 &mpic 3 1 0 0
	229	0x9200 0 0 2 &mpic 4 1 0 0
	230	0x9200 0 0 3 &mpic 1 1 0 0
	231	0x9200 0 0 4 &mpic 2 1 0 0
bebfa06c KG	232
bebfa06c KG	233	/* IDSEL 0x12 func 3 - PCI slot 2 */
ccdde478 SW	234	0x9300 0 0 1 &mpic 3 1 0 0
	235	0x9300 0 0 2 &mpic 4 1 0 0
	236	0x9300 0 0 3 &mpic 1 1 0 0
	237	0x9300 0 0 4 &mpic 2 1 0 0
bebfa06c KG	238
bebfa06c KG	239	/* IDSEL 0x12 func 4 - PCI slot 2 */
ccdde478 SW	240	0x9400 0 0 1 &mpic 3 1 0 0
	241	0x9400 0 0 2 &mpic 4 1 0 0
	242	0x9400 0 0 3 &mpic 1 1 0 0
	243	0x9400 0 0 4 &mpic 2 1 0 0
bebfa06c KG	244
bebfa06c KG	245	/* IDSEL 0x12 func 5 - PCI slot 2 */
ccdde478 SW	246	0x9500 0 0 1 &mpic 3 1 0 0
	247	0x9500 0 0 2 &mpic 4 1 0 0
	248	0x9500 0 0 3 &mpic 1 1 0 0
	249	0x9500 0 0 4 &mpic 2 1 0 0
bebfa06c KG	250
bebfa06c KG	251	/* IDSEL 0x12 func 6 - PCI slot 2 */
ccdde478 SW	252	0x9600 0 0 1 &mpic 3 1 0 0
	253	0x9600 0 0 2 &mpic 4 1 0 0
	254	0x9600 0 0 3 &mpic 1 1 0 0
	255	0x9600 0 0 4 &mpic 2 1 0 0
bebfa06c KG	256
bebfa06c KG	257	/* IDSEL 0x12 func 7 - PCI slot 2 */
ccdde478 SW	258	0x9700 0 0 1 &mpic 3 1 0 0
	259	0x9700 0 0 2 &mpic 4 1 0 0
	260	0x9700 0 0 3 &mpic 1 1 0 0
	261	0x9700 0 0 4 &mpic 2 1 0 0
707ba16f	262
1b3c5cda	263	// IDSEL 0x1c USB
6e050d4e JL	264	0xe000 0 0 1 &i8259 12 2
	265	0xe100 0 0 2 &i8259 9 2
	266	0xe200 0 0 3 &i8259 10 2
ba1616d9	267	0xe300 0 0 4 &i8259 11 2
707ba16f	268
1b3c5cda	269	// IDSEL 0x1d Audio
6e050d4e	270	0xe800 0 0 1 &i8259 6 2
707ba16f	271
1b3c5cda	272	// IDSEL 0x1e Legacy
6e050d4e JL	273	0xf000 0 0 1 &i8259 7 2
6e050d4e JL	274	0xf100 0 0 1 &i8259 7 2
1b3c5cda KG	275
1b3c5cda KG	276	// IDSEL 0x1f IDE/SATA
6e050d4e JL	277	0xf800 0 0 1 &i8259 14 2
6e050d4e JL	278	0xf900 0 0 1 &i8259 5 2
1b3c5cda KG	279	>;
	280
	281	pcie@0 {
6e050d4e JL	282	ranges = <0x02000000 0x0 0x80000000
	283	0x02000000 0x0 0x80000000
	284	0x0 0x20000000
1b3c5cda	285
6e050d4e JL	286	0x01000000 0x0 0x00000000
6e050d4e JL	287	0x01000000 0x0 0x00000000
47f80a32	288	0x0 0x00010000>;
dfac6faf WF	289	uli1575@0 {
	290	reg = <0 0 0 0 0>;
	291	#size-cells = <2>;
	292	#address-cells = <3>;
6e050d4e JL	293	ranges = <0x02000000 0x0 0x80000000
	294	0x02000000 0x0 0x80000000
	295	0x0 0x20000000
	296	0x01000000 0x0 0x00000000
	297	0x01000000 0x0 0x00000000
47f80a32	298	0x0 0x00010000>;
1b3c5cda KG	299	isa@1e {
1b3c5cda KG	300	device_type = "isa";
1b3c5cda KG	301	#size-cells = <1>;
1b3c5cda KG	302	#address-cells = <2>;
6e050d4e JL	303	reg = <0xf000 0 0 0 0>;
	304	ranges = <1 0 0x01000000 0 0
	305	0x00001000>;
1b3c5cda	306	interrupt-parent = <&i8259>;
dfac6faf	307
1b3c5cda	308	i8259: interrupt-controller@20 {
6e050d4e JL	309	reg = <1 0x20 2
	310	1 0xa0 2
	311	1 0x4d0 2>;
1b3c5cda KG	312	interrupt-controller;
	313	device_type = "interrupt-controller";
	314	#address-cells = <0>;
dfac6faf	315	#interrupt-cells = <2>;
1b3c5cda	316	compatible = "chrp,iic";
595207b9	317	interrupts = <9 2 0 0>;
1b3c5cda	318	};
dfac6faf	319
1b3c5cda KG	320	i8042@60 {
	321	#size-cells = <0>;
	322	#address-cells = <1>;
6e050d4e JL	323	reg = <1 0x60 1 1 0x64 1>;
6e050d4e JL	324	interrupts = <1 3 12 3>;
595207b9	325	interrupt-parent = <&i8259>;
dfac6faf	326
1b3c5cda KG	327	keyboard@0 {
	328	reg = <0>;
	329	compatible = "pnpPNP,303";
dfac6faf WF	330	};
dfac6faf WF	331
1b3c5cda KG	332	mouse@1 {
	333	reg = <1>;
	334	compatible = "pnpPNP,f03";
dfac6faf	335	};
1b3c5cda	336	};
dfac6faf	337
1b3c5cda KG	338	rtc@70 {
	339	compatible =
	340	"pnpPNP,b00";
6e050d4e	341	reg = <1 0x70 2>;
1b3c5cda KG	342	};
	343
	344	gpio@400 {
6e050d4e	345	reg = <1 0x400 0x80>;
dfac6faf WF	346	};
dfac6faf WF	347	};
707ba16f	348	};
707ba16f	349	};
e0e3c8d4	350
1b3c5cda KG	351	};
1b3c5cda KG	352
47f80a32	353	pci1: pcie@ffe09000 {
47f80a32	354	reg = <0xffe09000 0x1000>;
6e050d4e	355	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
47f80a32	356	0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
a66639d4	357
1b3c5cda	358	pcie@0 {
6e050d4e JL	359	ranges = <0x02000000 0x0 0xa0000000
	360	0x02000000 0x0 0xa0000000
	361	0x0 0x20000000
e0e3c8d4	362
6e050d4e JL	363	0x01000000 0x0 0x00000000
6e050d4e JL	364	0x01000000 0x0 0x00000000
47f80a32	365	0x0 0x00010000>;
707ba16f JL	366	};
707ba16f JL	367	};
47f80a32	368	/*
54986964 KG	369	* Only one of Rapid IO or PCI can be present due to HW limitations and
	370	* due to the fact that the 2 now share address space in the new memory
	371	* map. The most likely case is that we have PCI, so comment out the
	372	* rapidio node. Leave it here for reference.
	373
	374	rapidio@ffec0000 {
	375	reg = <0xffec0000 0x11000>;
	376	compatible = "fsl,srio";
595207b9	377	interrupts = <48 2 0 0>;
56fde1ff ZW	378	#address-cells = <2>;
56fde1ff ZW	379	#size-cells = <2>;
54986964 KG	380	fsl,srio-rmu-handle = <&rmu>;
	381	ranges;
	382
	383	port1 {
	384	#address-cells = <2>;
	385	#size-cells = <2>;
	386	cell-index = <1>;
	387	ranges = <0 0 0x80000000 0 0x20000000>;
	388	};
56fde1ff	389	};
47f80a32 BB	390	*/
47f80a32 BB	391
707ba16f	392	};
334479d1 AIB	393
334479d1 AIB	394	/include/ "mpc8641si-post.dtsi"